Composite package substrate

Abstract

A composite packaging substrate comprises a ceramic substrate, an electronic component, a substrate, a resin layer, a third circuit layer and a fourth circuit layer. The first surface of the ceramic substrate is provided with a groove, and the groove comprises a first through hole penetrating through the ceramic substrate and a first metal column filled in the first through hole. The first circuit layer and the second circuit layer are formed on the first surface and the second surface of the ceramic substrate. The electronic components are arranged in the grooves. The upper surface of the substrate is provided with a positioning area for positioning the ceramic substrate, a second through hole penetrating through the substrate and a second metal column filled in the second through hole. The resin layer covers the surfaces of the substrate and the ceramic substrate and is provided with a first opening. The third circuit layer is located on the surface of the resin layer and is filled in the first opening to be connected with the first circuit layer. The fourth circuit layer is located on a part of the lower surface of the substrate and connected with the second metal columns.

Description

Technical Field

[0001] The present disclosure relates to the field of chip packaging, and in particular to a composite packaging substrate. Background Art

[0002] As the line width of semiconductor chips becomes finer and finer, the density and complexity of chip packaging have been greatly improved, and the allowable filling difference has been reduced. Therefore, in advanced packaging, any slight deviation, such as the bending of the substrate, will affect the yield of the entire product.

[0003] The biggest challenge for advanced packaging today is the flatness and stability of the material substrate, especially in the face of large temperature changes in the welding process. At present, the industry hopes to increase the thickness of the core board to improve the assembly process, actual product operation, and the coplanarity and stability of the packaging plane. However, the core board is currently made of glass fiber, and thermal stability is its biggest disadvantage. When facing small chips and large-area packaging, high coplanarity and stability are necessary characteristics. Therefore, improving the temperature resistance and mechanical strength of the carrier board is a major challenge today. Summary of the invention

[0004] In order to solve the problems faced by the prior art, a composite packaging substrate is provided herein. The composite packaging substrate comprises a plurality of ceramic substrates, a plurality of electronic components, a substrate, a resin layer, a third circuit layer and a fourth circuit layer.

[0005] Each ceramic substrate includes a first surface, a second surface, a plurality of first through holes, a plurality of first metal pillars, a first circuit layer, and a second circuit layer. A groove is provided on the first surface. The first through hole penetrates the first surface and the second surface. The first metal pillar is filled in the first through hole. The first circuit layer is formed on a portion of the first surface and connected to the first metal pillar. The second circuit layer is formed on a portion of the second surface and connected to the first metal pillar. Each electronic component is installed in the groove and connected to the first metal pillar in the groove.

[0006] The substrate has an upper surface, a lower surface, a plurality of second through holes and a plurality of second metal pillars. A plurality of positioning areas are defined on the upper surface, and the ceramic substrates are respectively located on the positioning areas. The second through holes penetrate the upper surface and the lower surface. The second metal pillars are filled in the second through holes and are connected to the second circuit layer of each ceramic substrate. The resin layer covers the upper surface of the substrate and the first surface of the ceramic substrate, and the resin layer includes a plurality of first openings. The third circuit layer is located on a portion of the surface of the resin layer and in the first opening, and is connected to the first circuit layer of each ceramic substrate. The fourth circuit layer is located on a portion of the lower surface of the substrate and is connected to the second metal pillars.

[0007] In some embodiments, the electronic component is a chip, an active component, or a passive component.

[0008] In some embodiments, the first opening corresponds to the second metal pillar.

[0009] In some embodiments, a plurality of grooves are formed on the upper surface of the substrate, the grooves define positioning areas, and the ceramic substrates are respectively clamped in the grooves.

[0010] In some embodiments, the composite package substrate further includes a first solder mask layer, a first pad layer, a second solder mask layer and a second pad layer. The first solder mask layer is located on the resin layer and has a plurality of first pad openings. The first pad layer is filled in the first pad opening and is electrically connected to the third circuit layer. The second solder mask layer is located on the lower surface of the substrate and has a plurality of second pad openings. The second pad layer is filled in the second pad opening and is electrically connected to the fourth circuit layer.

[0011] More specifically, in some embodiments, the first pad layer includes a plurality of first pads, the first pads protrude from the first solder mask layer, the second pad layer includes a plurality of second pads, the second pads protrude from the second solder mask layer, and a first spacing between the first pads is smaller than a second spacing between the second pads.

[0012] Furthermore, in some embodiments, the composite package substrate further includes a first protective layer, a first redistribution layer, a second protective layer and a second redistribution layer. The first protective layer is located between the resin layer and the first solder mask layer, covers the third circuit layer, and has a plurality of second openings. The first redistribution layer is located on a portion of the first protective layer and fills the second opening, connecting the third circuit layer and the first pad layer. The second protective layer is located between the lower surface of the substrate and the second solder mask layer, covers the fourth circuit layer, and has a plurality of third openings. The second redistribution layer is located on a portion of the second protective layer and fills the third opening, connecting the fourth circuit layer and the second pad layer.

[0013] In some embodiments, a coating is further included between the sidewall surface of the second through hole and the second metal column filled therein. More specifically, the coating is a resin coating.

[0014] In some embodiments, each ceramic substrate has a length and a width ranging from 3 to 100 cm and a thickness ranging from 0.1 to 1 mm.

[0015] As shown in the above embodiments, by providing a more stable substrate core structure through a ceramic substrate, it is possible to effectively maintain thermal stability when heated and increase mechanical strength, thereby providing high coplanarity and stability for small chips and large area packages. Furthermore, by embedding electronic components together in the ceramic substrate, the product component density can be further increased, making it more suitable for application in advanced chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1is a top view of the composite packaging substrate;

[0017] Figure 2 is a partial cross-sectional view of the ceramic substrate in the figure;

[0018] Figure 3 is a partial cross-sectional view of a first embodiment of a composite packaging substrate;

[0019] Figure 4 is a partial cross-sectional view of a second embodiment of a composite packaging substrate;

[0020] Figure 5 and Figure 6 Partial cross-sectional views of different embodiments of the ceramic substrate.

[0021]

Explanation of symbols

[0022] 1: Composite packaging substrate

[0023] 10: Ceramic substrate

[0024] 11: First surface

[0025] 111: Groove

[0026] 12: Second surface

[0027] 13: First through hole

[0028] 131: Side wall

[0029] 133: Coating

[0030] 14: First metal column

[0031] 15: First circuit layer

[0032] 16: Second circuit layer

[0033] 20: Electronic components

[0034] 30:Substrate

[0035] 31: Upper surface

[0036] 311: Groove

[0037] 32: Lower surface

[0038] 33: Second through hole

[0039] 34: Second metal column

[0040] 351: Positioning area

[0041] 40: Resin layer

[0042] 41: First Opening

[0043] 50: The third circuit layer

[0044] 60: Fourth circuit layer

[0045] 71: First solder mask layer

[0046] 711: first pad opening

[0047] 73: First pad layer

[0048] 731: first pad

[0049] 75: Second solder mask layer

[0050] 751: second pad opening

[0051] 77: Second solder pad layer

[0052] 771: Second welding pad

[0053] 81: First protective layer

[0054] 811: Second opening

[0055] 83: First redistribution layer

[0056] 85: Second protective layer

[0057] 851: The third opening

[0058] 87: Second redistribution layer

[0059] D1: First spacing

[0060] D2: Second spacing DETAILED DESCRIPTION

[0061] It should be understood that when an element is referred to as being "disposed" or "connected" to another element, it may mean that the element is directly located on the other element, or there may be an intermediate element through which the element and the other element are connected. Conversely, when an element is referred to as being "directly disposed / connected to another element" or "directly disposed / connected to another element", it should be understood that it is clearly defined that there are no intermediate elements.

[0062] In addition, the terms "first", "second", "third" are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part, rather than to indicate a necessary order of precedence. In addition, relative terms such as "lower" and "upper" may be used herein to describe the relationship between one element and another element, and it should be understood that the relative terms are intended to include different orientations of the device in addition to the orientation shown in the figure. For example, if a device in a figure is flipped, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. This only represents a relative orientation relationship, not an absolute orientation relationship.

[0063] Figure 1 A top view of the composite packaging substrate. Figure 2 It is a partial cross-sectional view of the ceramic substrate in the figure. Figure 3 FIG. 1 is a partial cross-sectional view of the first embodiment of the composite packaging substrate. Figures 1 to 3 As shown, the composite package substrate 1 includes a plurality of ceramic substrates 10, a plurality of electronic components 20, a substrate 30, a resin layer 40, a third circuit layer 50 and a fourth circuit layer 60. Here, Figure 1 Only to clearly show the relative positions of the substrate 30 and the ceramic substrate 10 , other elements are omitted. Figure 3 for Figure 1 The cross section of AA in Figure 2 The cross-sectional structure of the ceramic substrate 10 is described in an enlarged manner.

[0064] like Figure 1 As shown, the ceramic substrate 10 is positioned in the positioning area 351 of the substrate 30. Through the combination of small pieces and multiple pieces of ceramic substrates 10, it can provide anti-bending effect, and at the same time disperse stress, avoid stress concentration, and avoid a single ceramic substrate 10 from being brittle and cracked by impact during the process. Preferably, in some embodiments, the length and width of the ceramic substrate 10 range from 3 to 100 cm, and the thickness is 0.1 to 1 mm. More preferably, the length and width of the ceramic substrate 10 range from 10 to 20 cm, and the thickness is 0.1 to 0.3 mm.

[0065] Then, if Figure 2As shown, the ceramic substrate 10 includes a first surface 11, a second surface 12, a plurality of first through holes 13, a plurality of first metal pillars 14, a first circuit layer 15, and a second circuit layer 16. A groove 111 is provided on the first surface 11. The first through hole 13 passes through the first surface 11 and the second surface 12. A portion of the first through hole 13 is also formed in the groove 111. The first metal pillar 14 is filled in the first through hole 13. The electronic component 20 is installed in the groove 111 and connected to the first metal pillar 14 in the groove 111. After the installation of the electronic component 20 is completed, the first circuit layer 15 is formed on a portion of the first surface 11. The first circuit layer 15 is connected to the first metal pillar 14. The second circuit layer 16 is formed on a portion of the second surface 12 and is connected to the first metal pillar 14. Here, the first metal pillar 14, the first circuit layer 15, and the second circuit layer 16 can be covered by dry film and then directly completed by electroplating.

[0066] Here, the electronic component 20 can be a chip, an active component, or a passive component. One or more grooves 111 on the ceramic substrate 10 can be selected according to the electronic component 20 . Only one groove is shown in the figure as an example and is not intended to be limiting.

[0067] like Figure 3 As shown, the substrate 30 has an upper surface 31, a lower surface 32, a plurality of second through holes 33 and a plurality of second metal pillars 34. A plurality of positioning areas 351 are defined on the upper surface 31, and the ceramic substrates 10 are respectively located on the positioning areas 351. The second through holes 33 penetrate the upper surface 31 and the lower surface 32. The second metal pillars 34 are filled in the second through holes 33 and connected to the second circuit layers 16 of each ceramic substrate.

[0068] The resin layer 40 covers the upper surface 31 of the substrate 30 and the first surface 11 of the ceramic substrate 10, and the resin layer 40 includes a plurality of first openings 41. In this embodiment, the resin layer 40 directly covers the ceramic substrate 10 to achieve double-layer packaging.

[0069] The third circuit layer 50 is located on a portion of the surface of the resin layer 40 and in the first opening 41, and is connected to the first circuit layer 15. In some embodiments, the first opening 41 corresponds to the second metal column 34. The fourth circuit layer 60 is located on a portion of the lower surface 32 of the substrate 30 and is connected to the second metal column 34. Here, the second metal column 34 and the fourth circuit layer 60 can also be covered by dry film and then directly completed by electroplating.

[0070] Figure 4 FIG. 2 is a partial cross-sectional view of a second embodiment of a composite packaging substrate. Figure 4 As shown, refer to Figure 3Different from the first embodiment, the upper surface 31 of the substrate 30 is provided with a plurality of grooves 311, and the grooves 311 are used as the positioning areas 351. The ceramic substrates 10 are respectively clamped in the grooves 311 and then covered with the resin layer 40. This method can further reduce the thickness of the overall structure, and the ceramic substrate 10, the electronic component 20 and the substrate 30 can be coplanar. However, this is only an example and not intended to be limiting.

[0071] See again Figure 3 and Figure 4 The composite package substrate 1 further includes a first solder mask layer 71, a first pad layer 73, a second solder mask layer 75 and a second pad layer 77. The first solder mask layer 71 is located on the resin layer 40 and has a plurality of first pad openings 711. The first pad layer 73 is filled in the first pad openings 711 and is electrically connected to the third circuit layer 50. The second solder mask layer 75 is located on the lower surface 32 of the substrate 30 and has a plurality of second pad openings 751. The second pad layer 77 is filled in the second pad openings 751 and is electrically connected to the fourth circuit layer 60.

[0072] Furthermore, the first pad layer 73 includes a plurality of first pads 731, and the plurality of first pads 731 protrude from the first solder mask layer 71. The second pad layer 77 includes a plurality of second pads 771, and the second pads 771 protrude from the second solder mask layer 75, and a first spacing D1 between the first pads 731 is smaller than a second spacing D2 between the second pads 771. In other words, through the substrate 30 and the ceramic substrate 10, an interposer function can be provided for the subsequently installed chip.

[0073] See again Figure 3 and Figure 4 In some embodiments, the composite package substrate 1 further includes a first protective layer 81, a first redistribution layer 83, a second protective layer 85 and a second redistribution layer 87. The first protective layer 81 is located between the resin layer 40 and the first solder mask layer 71, covers the third circuit layer 50, and has a plurality of second openings 811. The first redistribution layer 83 is located on a portion of the first protective layer 81 and fills the second openings 811, connecting the third circuit layer 50 and the first pad layer 73. The second protective layer 85 is located between the lower surface 32 of the substrate 30 and the second solder mask layer 75, covers the fourth circuit layer 60, and has a plurality of third openings 851. The second redistribution layer 87 is located on a portion of the second protective layer 85 and fills the third openings 851, connecting the fourth circuit layer 60 and the second pad layer 77. In addition, the first protective layer 81, the first redistribution layer 83, the second protective layer 85 and the second redistribution layer 87 can be one layer or multiple layers. Two layers are used here only as an example, not for limitation.

[0074] Figure 5 and Figure 6 1 is a partial cross-sectional view of different embodiments of the ceramic substrate. Figure 5 and Figure 6 As shown, for different precisions, drilling and filling types, the first through hole 13 may be as follows Figure 5 As shown, only the first metal column 14 is filled. Alternatively, Figure 6 As shown, a coating 133 is further included between the sidewall surface 131 of the first through hole 13 and the first metal column 14. Preferably, the coating 133 can be a resin coating.

[0075] In summary, by providing a more stable core structure through the ceramic substrate 10, it can effectively maintain thermal stability when heated and increase mechanical strength, thereby providing high coplanarity and stability for small chips and large area packages. Furthermore, by embedding the electronic components 20 together in the ceramic substrate 10, it can be used as an embedded multi-die interconnect bridge (EMIB) packaging structure. It can further increase the density of product components and is more suitable for application in advanced chip packaging.

[0076] Although the technical contents of the present invention have been disclosed as above in the preferred embodiments, they are not used to limit the present invention. Any slight changes and modifications made by anyone familiar with this technology without departing from the spirit of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be based on the scope defined by the attached claims.

Claims

1. A composite packaging substrate, characterized in that: Include: A plurality of ceramic substrates, each of which comprises a first surface, a second surface, a plurality of first through holes, a plurality of first metal pillars, a first circuit layer, and a second circuit layer, wherein the first surface is provided with a groove, the plurality of first through holes penetrate the first surface and the second surface, the plurality of first metal pillars are filled in the plurality of first through holes, the first circuit layer is formed on a portion of the first surface and connected to the plurality of first metal pillars, and the second circuit layer is formed on a portion of the second surface and connected to the plurality of first metal pillars; A plurality of electronic components, each of which is installed in the groove and connected to the plurality of first metal pillars in the groove; A substrate having an upper surface, a lower surface, a plurality of second through holes and a plurality of second metal pillars, wherein a plurality of positioning areas are defined on the upper surface, the plurality of ceramic substrates are respectively located on the plurality of positioning areas, the plurality of second through holes penetrate the upper surface and the lower surface, the plurality of second metal pillars are filled in the plurality of second through holes and connected to the second circuit layer of each of the ceramic substrates; a resin layer covering the upper surface of the substrate and the first surfaces of the plurality of ceramic substrates, and the resin layer comprises a plurality of first openings; a third circuit layer, located on a portion of a surface of the resin layer and in the plurality of first openings, and connected to the first circuit layers of each of the ceramic substrates; as well as A fourth circuit layer is located on a portion of the lower surface of the substrate and is connected to the plurality of second metal pillars.

2. The composite packaging substrate according to claim 1, characterized in that: Each of the electronic components is a chip, an active component, or a passive component.

3. The composite packaging substrate according to claim 1, characterized in that: The plurality of first openings correspond to the plurality of second metal pillars.

4. The composite packaging substrate according to claim 1, characterized in that: The upper surface of the substrate is provided with a plurality of grooves, the plurality of grooves define the plurality of positioning areas, and the plurality of ceramic substrates are respectively clamped in the plurality of grooves.

5. The composite packaging substrate according to claim 1, wherein: It also includes a first solder mask layer, a first pad layer, a second solder mask layer and a second pad layer. The first solder mask layer is located on the resin layer and has a plurality of first pad openings. The first pad layer is filled in the plurality of first pad openings and is electrically connected to the third circuit layer. The second solder mask layer is located on the lower surface of the substrate and has a plurality of second pad openings. The second pad layer is filled in the plurality of second pad openings and is electrically connected to the fourth circuit layer.

6. The composite packaging substrate according to claim 5, characterized in that: The first pad layer includes a plurality of first pads, the plurality of first pads protrude from the first solder mask layer, the second pad layer includes a plurality of second pads, the plurality of second pads protrude from the second solder mask layer, and a first spacing between the plurality of first pads is smaller than a second spacing between the plurality of second pads.

7. The composite packaging substrate according to claim 6, characterized in that: It also includes a first protective layer, a first redistribution layer, a second protective layer and a second redistribution layer. The first protective layer is located between the resin layer and the first solder mask layer, covers the third circuit layer, and has a plurality of second openings. The first redistribution layer is located on a portion of the first protective layer and fills the plurality of second openings to connect the third circuit layer and the first pad layer. The second protective layer is located between the lower surface of the substrate and the second solder mask layer, covers the fourth circuit layer, and has a plurality of third openings. The second redistribution layer is located on a portion of the second protective layer and fills the plurality of third openings to connect the fourth circuit layer and the second pad layer.

8. The composite packaging substrate according to claim 1, characterized in that: A coating is also included between the sidewalls of the plurality of second through holes and the second metal pillars filled therein.

9. The composite packaging substrate according to claim 8, characterized in that: The coating is a resin coating.

10. The composite packaging substrate according to claim 1, wherein: The length and width of each ceramic substrate range from 3 to 100 cm, and the thickness ranges from 0.1 to 1 mm.

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