Scanning window signal generation circuit
By adjusting the oscillation period and circuit parameters of the oscillator, the length of the scanning window signal can be flexibly set, solving the problem of fixed scanning window signal length in the prior art, reducing circuit design complexity and cost, and reducing interference of digital signals on analog signals.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI ZGMICRO ELECTRONICS CO LTD
- Filing Date
- 2024-12-16
- Publication Date
- 2026-07-21
AI Technical Summary
In the prior art, the length of the scanning window signal is fixed as an integer multiple of the base clock, which increases the complexity of circuit design and production costs, and also requires preventing digital signals from interfering with analog signals.
By adjusting the oscillation period of the oscillator and flexibly setting the length of the scan window signal based on the charging current, charging capacitor, and reference voltage, the length of each scan window signal is equal to the corresponding predetermined duration, thus avoiding the overlap of scan window signals.
It enables flexible setting of the scanning window signal length, reducing circuit design complexity and production costs, while also reducing the risk of digital signals interfering with analog signals.
Smart Images
Figure CN119892016B_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to the field of circuit design, and in particular to a scanning window signal generation circuit. [Background Technology]
[0002] Battery protection chips need to have the lowest possible power consumption. One solution is to perform various protection detections through intermittent scanning to achieve low average power consumption. Currently, the control of intermittent scanning is achieved by using the base clock CLK output by the oscillator for combinational timing logic. The scan window length for different protection functions needs to be set to an integer multiple of 1 / 2 cycle of the base clock CLK.
[0003] Figure 1 This is a block diagram of an existing scan window signal generation circuit. (Example:) Figure 1 As shown, the scan window signal generation circuit includes an oscillator OSC and a scan logic module SCAN_LOGIC. The oscillator OSC outputs a base clock signal CLK, and the scan logic module SCAN_LOGIC generates various scan window signals SCAN_WINDOW1~n based on the base clock CLK.
[0004] Figure 2 This is a schematic diagram of the internal circuitry of an oscillator (OSC). The OSC includes a discharge switch SW, a comparator CMP, a current source ibias, and a charging capacitor C.
[0005] The current source ibias provides charging current, which is used to charge the first terminal RAMP of the charging capacitor C. The comparator CMP compares the voltage at the first terminal RAMP of the charging capacitor C with the reference voltage VREF, and outputs a comparison signal CMPO as the control signal for the discharge switch SW. The discharge switch SW is connected between the first terminal RAMP and the second voltage terminal VSS of the charging capacitor C. When the discharge switch SW is turned on, the capacitor C is discharged; when the discharge switch SW is turned off, the charging current charges the capacitor C. The voltage signal at the first terminal RAMP of the charging capacitor C is the oscillation signal, and one charging and discharging process constitutes one oscillation cycle.
[0006] Specifically, the charging capacitor C is charged through the current source ibias. When the voltage at the first connection terminal RAMP of the charging capacitor C exceeds the reference voltage VREF, the comparator CMP outputs a high-level comparison signal CMPO, the discharge switch SW turns on, discharging the charging capacitor C and pulling the voltage at the first connection terminal RAMP back to VSS. Since the voltage of RAMP is lower than VREF, CMPO becomes low, the discharge switch SW turns off, and the charging capacitor C continues to be charged, starting the next oscillation cycle. Because the comparison signal CMPO is a square wave signal with a very small duty cycle, the oscillator OSC uses a frequency divider circuit to divide the frequency of the comparison signal CMPO by half, thus generating a basic clock signal CLK with a 50% duty cycle. Figure 2 The frequency divider module is not shown.
[0007] Figure 3 for Figure 1 and Figure 2 The waveform diagrams for each signal are shown below. It can be seen that half the clock period of the base clock CLK is equal to one period of the oscillation signal RAMP. The scan window of the scan window signal SCAN_WINDOW is aligned with the rising edge of the base clock CLK. Therefore, the width of the scan window of the scan window signal SCAN_WINDOW is an integer multiple of the period of the oscillation signal RAMP. Different integer multiples are designed for the scan window of the scan window signal SCAN_WINDOW according to the requirements of different scan functions.
[0008] The above approach results in the scan window signal SCAN_WINDOW encompassing one or more toggling edges of the base clock. Since the scan window corresponds to the operating time of the analog circuit, special consideration must be given to preventing digital signals from interfering with analog signals during layout signal routing and power distribution. Furthermore, it necessitates a deliberate distinction between digital and analog circuit power supplies during circuit design. These measures simultaneously increase design complexity and production costs.
[0009] Therefore, it is necessary to propose an improved technical solution to overcome the above problems. [Summary of the Invention]
[0010] One of the objectives of this invention is to provide a scanning window signal generation circuit that can flexibly set the length of the scanning window for various scanning window signals, thereby reducing the complexity of circuit design.
[0011] According to one aspect of the present invention, a scan window signal generation circuit is provided, comprising: an oscillator that generates an oscillation signal; and a scan logic module that generates a plurality of scan window signals based on the oscillation signal and feeds the scan window signals back to the oscillator, such that the length of one oscillation period of the oscillation signal generated by the oscillator during the scan window of each scan window signal is a corresponding predetermined duration, thereby making the length of the scan window of each scan window signal equal to the corresponding predetermined duration, wherein the scan window of each scan window signal corresponds to one oscillation period of the oscillation signal.
[0012] In one embodiment, the scanning windows of different scanning window signals do not overlap, the scanning window of the scanning window signal is high level or low level, the non-scanning window portion of the scanning window signal is low level or high level, the length of the oscillation period corresponding to the scanning window of each scanning window signal is equal to the length of the scanning window of that scanning window signal, at least two scanning window signals have different lengths of their scanning windows, and at least two scanning window signals have different lengths of their corresponding oscillation periods.
[0013] In one embodiment, the oscillator determines the oscillation period of the oscillation signal based on the charging current, the charging capacitor, and the reference voltage. One or more of the charging current, the charging capacitor, and the reference voltage are adjustable. The oscillator adjusts the oscillation period of the oscillation signal by adjusting one or more of the charging current, the charging capacitor, and the reference voltage. At the beginning of the scanning window of each scanning window signal, the oscillator adjusts one or more of the charging current, the charging capacitor, and the reference voltage to a set of predetermined values corresponding to the scanning window of that scanning window signal, such that at the beginning of the scanning window of each scanning window signal, the length of the oscillation period of the oscillation signal is the corresponding predetermined duration. The lengths of the scanning windows of at least two scanning window signals are different, and the lengths of the oscillation periods corresponding to the scanning windows of at least two scanning window signals are different.
[0014] Compared with the prior art, the present invention changes the oscillation period of the oscillator and uses this oscillation period as the length of the scanning window of the corresponding scanning window signal. This allows for flexible setting of the scanning window length of various scanning window signals, reducing the complexity of circuit design. [Attached Image Description]
[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0016] Figure 1 A block diagram of an existing scan window signal generation circuit;
[0017] Figure 2 This is a schematic diagram of the internal circuitry of an oscillator (OSC).
[0018] Figure 3 for Figure 1 and Figure 2 A schematic diagram of the waveforms of each signal in the diagram;
[0019] Figure 4 This is a structural block diagram of the scanning window signal generation circuit in one embodiment of the present invention;
[0020] Figure 5 for Figure 4 A schematic diagram of the internal circuitry of the OSC oscillator in one embodiment; and
[0021] Figure 6 for Figure 4 and Figure 5 The waveform diagrams of each signal are shown.
Detailed Implementation Methods
[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0023] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.
[0024] This invention provides a scanning window signal generation circuit. By changing the oscillation period of the oscillator and using this oscillation period as the length of the scanning window of the corresponding scanning window signal, the length of the scanning window of various scanning window signals can be flexibly set, reducing the complexity of circuit design.
[0025] Figure 4 This is a block diagram of the scanning window signal generation circuit in one embodiment of the present invention. Figure 5 for Figure 4 A schematic diagram of the internal circuitry of the OSC oscillator in one embodiment. Figure 6 for Figure 4 and Figure 5 The waveform diagrams of each signal are shown.
[0026] like Figure 4As shown, the scan window signal generation circuit includes an oscillator OSC and a scan logic module SCAN_LOGIC. The oscillator generates an oscillation signal RAMP. The scan logic module generates multiple scan window signals SCAN_WINDOW1 to SCAN_WINDOWn based on the oscillation signal, where n is a natural number greater than or equal to 2. The scan logic module feeds back the scan window signals SCAN_WINDOW1 to SCAN_WINDOWn to the oscillator, so that the length of one oscillation cycle of the oscillation signal generated by the oscillator during the scan window of each scan window signal is equal to the corresponding predetermined duration, thereby making the length of the scan window of each scan window signal equal to the corresponding predetermined duration, wherein the scan window of each scan window signal corresponds to one oscillation cycle of the oscillation signal, that is, the length (or duration) of the scan window of each scan window signal is equal to the length (or duration) of the corresponding oscillation cycle. Figure 6 As shown, the scan window signal SCAN_WINDOW1 corresponds to one oscillation period T1 of the oscillation signal, the scan window signal SCAN_WINDOW2 corresponds to one oscillation period T2 of the oscillation signal, and the scan window signal SCAN_WINDOWn corresponds to one oscillation period Tn of the oscillation signal. The lengths of the oscillation periods corresponding to the various scan window signals SCAN_WINDOW1-n are different. Of course, in some embodiments, two or more scan window signals may correspond to the same length of the oscillation period as needed. In any case, the scan window lengths of at least two scan window signals are different, that is, the lengths of the oscillation periods corresponding to the scan windows of at least two scan window signals are different, and the predetermined durations of the oscillation periods corresponding to the scan windows of at least two scan window signals are different.
[0027] like Figure 6 As shown, the scanning windows of different scanning window signals do not overlap. The scanning window portion of the scanning window signal SCAN_WINDOW1-n is at a high level, while the non-scanning window portion of the scanning window signal is at a low level. In other embodiments, the scanning window portion of the scanning window signal SCAN_WINDOW1-n may also be at a low level, while the non-scanning window portion of the scanning window signal is at a high level.
[0028] The oscillator determines the oscillation period of the oscillation signal RAMP based on the charging current, the charging capacitor C, and the reference voltage VREF. One or more of the charging current, the charging capacitor, and the reference voltage are adjustable, and the oscillator adjusts the oscillation period of the oscillation signal by adjusting one or more of the charging current, the charging capacitor, and the reference voltage. Figure 5In the illustrated embodiment, the charging current is adjustable. In other embodiments, the charging capacitor or the reference voltage may also be adjustable, or two or three of the charging current, the charging capacitor, and the reference voltage may be adjustable.
[0029] At the start of the scan window of each scan window signal, i.e., at the rising edge of the scan window, the oscillator adjusts one or more of the charging current, charging capacitor, and reference voltage to a predetermined set of values corresponding to the scan window of that scan window signal (e.g., the charging current is a predetermined current value corresponding to the scan window, the charging capacitor is a predetermined capacitance value corresponding to the scan window, and the reference voltage is a predetermined reference voltage value corresponding to the scan window), so that during the scan window of each scan window signal, the length of the oscillation period of the oscillation signal is the corresponding predetermined duration. Figure 5 In the example shown, at the start of the scan window of each scan window signal, the oscillator adjusts the charging current to a predetermined current value corresponding to the scan window of that scan window signal, thereby making the length of the scan window of each scan window signal the corresponding predetermined duration. Different sets of predetermined values corresponding to the scan windows of different scan window signals can be different, which allows the length of their corresponding oscillation periods to be different, that is, the length of the oscillation period of the oscillation signal corresponding to the predetermined duration can be different.
[0030] like Figure 5 As shown, the oscillator includes a discharge switch SW, a comparator CMP, a current source ibias, and a charging capacitor C. The current source ibias provides the charging current, which charges the first terminal RAMP of the charging capacitor C. The comparator CMP compares the voltage RAMP at the first terminal of the charging capacitor C with the reference voltage VREF and outputs a comparison signal CMPO as a control signal for the discharge switch SW, which is connected to the first terminal of the charging capacitor C. When the discharge switch SW is on, the charging capacitor C is discharged; when the discharge switch SW is off, the charging current charges the charging capacitor C. The voltage signal RAMP at the first terminal of the charging capacitor C is the oscillation signal, and one charge-discharge process constitutes one oscillation cycle. The other end of the discharge switch SW is connected to a second voltage terminal VSS, and the first voltage terminal VCC supplies power to the current source.
[0031] Specifically, the charging capacitor C is charged through the current source ibias. When the voltage at the first connection terminal RAMP of the charging capacitor C exceeds the reference voltage VREF, the comparator CMP outputs a high-level comparison signal CMPO, the discharge switch SW turns on, and the charging capacitor C is discharged, pulling the voltage at the first connection terminal RAMP back to VSS. Since the voltage of RAMP is lower than VREF, CMPO becomes low, the discharge switch SW turns off, and the charging capacitor C continues to be charged, starting the next oscillation cycle.
[0032] It can be seen that the oscillation period of the oscillation signal can be adjusted by adjusting one or more of the charging current, the charging capacitor, and the reference voltage.
[0033] In one specific embodiment, the charging capacitor includes multiple charging capacitor unit groups connected in parallel. Each charging capacitor unit group includes a charging capacitor unit and a control switch. The capacitance value of the charging capacitor is reduced by turning off the control switch in one or more charging capacitor unit groups, and the capacitance value of the charging capacitor is increased by turning on the control switch in one or more charging capacitor unit groups.
[0034] like Figure 6 As shown, the oscillator OSC generates a clock signal CLK based on the comparison signal CMPO or the oscillation signal RAMP. Each clock cycle of the clock signal CLK includes two oscillation cycles. The oscillation period of the oscillation signal RAMP or the period of the comparison signal CMPO is variable, and the clock period of the clock signal CLK is also variable. The predetermined duration corresponding to the oscillation period of the oscillation signal RAMP is also variable.
[0035] The scanning logic module sets the timing of each scanning window signal and the scanning period of each scanning window signal based on the clock signal CLK. For example, the scanning window of scanning window signal SCAN_WINDOW1 appears first, followed by the scanning window of scanning window signal SCAN_WINDOW2, and finally the scanning window of scanning window signal SCAN_WINDOWn. The scanning period of the scanning window signal refers to how often a scanning window appears.
[0036] In this invention, the oscillation period of the oscillator can be changed according to the requirements of different detection functions, and this period can be used as the length of the scanning window signal for the corresponding detection function. This allows for flexible setting of the scanning window length for various scanning window signals, no longer limited to integer multiples of half a period of a constant base clock, and also reduces circuit design complexity, chip area, design risk, and production costs.
[0037] In this invention, terms such as "connection," "linked," "connected," "coupled," and "interconnected" that indicate electrical connection, unless otherwise specified, refer to direct or indirect electrical connections. A direct electrical connection refers to a direct connection between two or more objects without any intervening objects, while an indirect electrical connection refers to an electrical connection between two or more objects with one or more intervening objects (such as electrical components or units like resistors, capacitors, inductors, switches, and filters).
[0038] It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims. Accordingly, the scope of the claims is not limited to the foregoing specific embodiments.
Claims
1. A scanning window signal generation circuit, characterized in that, It includes: An oscillator that generates an oscillating signal; and The scanning logic module generates multiple scanning window signals based on the oscillation signal and feeds these scanning window signals back to the oscillator. This ensures that the length of one oscillation cycle of the oscillation signal generated by the oscillator during the scanning window of each scanning window signal is equal to a predetermined duration. Consequently, the length of the scanning window for each scanning window signal is equal to the predetermined duration, where each scanning window signal corresponds to one oscillation cycle of the oscillation signal. The oscillator determines the oscillation period of the oscillation signal based on the charging current, the charging capacitor, and the reference voltage. One or more of the charging current, the charging capacitor, and the reference voltage are adjustable. The oscillator adjusts the oscillation period of the oscillation signal by adjusting one or more of the charging current, the charging capacitor, and the reference voltage. At the start of each scan window of the scan window signal, the oscillator adjusts one or more of the charging current, charging capacitance, and reference voltage to a predetermined set of values corresponding to that scan window of the scan window signal, such that during each scan window of the scan window signal, the length of the oscillation period of the oscillation signal is the corresponding predetermined duration. The scan window lengths of at least two scan window signals are different, and the oscillation period lengths corresponding to the scan windows of at least two scan window signals are different.
2. The scanning window signal generation circuit according to claim 1, characterized in that, The scan windows of signals from different scan windows do not overlap. The length of the scan window for each scan window signal is equal to the length of the corresponding oscillation period. At least two scan window signals have different scan window lengths, at least two scan window signals have different oscillation period lengths corresponding to their scan windows, and at least two scan window signals have different predetermined durations corresponding to their oscillation periods. The scanning window portion of the scanning window signal is either high or low, while the non-scanning window portion of the scanning window signal is either low or high.
3. The scanning window signal generation circuit according to claim 1, characterized in that, The oscillator includes a discharge switch, a comparator, a current source, and a charging capacitor. The current source provides the charging current, which is used to charge the first connection terminal of the charging capacitor. The comparator compares the voltage at the first connection terminal of the charging capacitor with the reference voltage and outputs a comparison signal as a control signal for the discharge switch. The discharge switch is connected to the first connection terminal of the charging capacitor. When the discharge switch is on, the charging capacitor is discharged; when the discharge switch is off, the charging current charges the charging capacitor. The voltage signal at the first connection terminal of the charging capacitor is the oscillation signal, and one charge-discharge process constitutes one oscillation cycle. The oscillation period of the oscillation signal can be adjusted by adjusting one or more of the charging current, the charging capacitor, and the reference voltage.
4. The scanning window signal generation circuit according to claim 3, characterized in that, The other end of the discharge switch is connected to the second voltage terminal VSS, and the first voltage terminal VCC supplies power to the current source.
5. The scanning window signal generation circuit according to claim 3, characterized in that, The charging capacitor includes multiple charging capacitor unit groups connected in parallel. Each charging capacitor unit group includes one charging capacitor unit and a control switch. The capacitance value of the charging capacitor is reduced by turning off the control switch in one or more charging capacitor unit groups, and the capacitance value of the charging capacitor is increased by turning on the control switch in one or more charging capacitor unit groups.
6. The scanning window signal generation circuit according to claim 3, characterized in that, The oscillator generates a clock signal based on the comparison signal or the oscillation signal. Each clock cycle of the clock signal includes two oscillation cycles. The scanning logic module sets the timing of the scanning windows of each scanning window signal and sets the scanning cycle of each scanning window signal based on the clock signal.