A foreground calibration circuit for a time domain analog-to-digital converter

Abstract

The application provides a foreground calibration circuit of a time domain analog-digital converter, which comprises a calibration clock generation circuit, an oscillation period detection and processing circuit and a current adjustment circuit; the calibration clock generation circuit is connected with the oscillation period detection and processing circuit and is used for calibrating the clock of the circuit; the oscillation period detection and processing circuit is connected with a counter and the current adjustment circuit and is used for detecting the oscillation period and adjusting the oscillation period; and the current adjustment circuit is connected with an input current and is used for adjusting the size of the current. The application introduces a detection circuit at the counting result of the ring oscillator, and under the condition of full swing input, the result is fed back to the counter output control code word to adjust the discharge current in the voltage time conversion circuit by detecting whether the counted period reaches the preset value, so as to adjust the time range of the output, realize the automatic matching of the conversion range of the voltage time conversion circuit and the quantization range of the time digital conversion circuit.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a front-end calibration circuit for a time-domain analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs) are crucial bridges connecting analog and digital signals, essential components of computers for processing analog signals, and widely used in modern communications, smart healthcare, and other fields. With advancements in integrated circuit manufacturing processes, transistor feature sizes are continuously shrinking, and power supply voltages are gradually decreasing. For voltage-domain ADCs, this leads to smaller input swings and a lower achievable signal-to-noise ratio (SNR). In contrast, time-domain ADCs convert input voltage into time signals and quantize them. Quantization resolution increases with decreasing delay time, and as feature sizes shrink, the delay time of a single inverter decreases, resulting in a significant speed advantage. Figure 1 The traditional time-domain analog-to-digital converter circuit operates as follows: First, analog voltages V2 and V1 are acquired through a switch and fed to the capacitors at both ends. Then, the voltage on the capacitors is discharged. The charge conversion relationship can be expressed as I*(t2-t1)=C*((V2-VTH)-(V1-VTH)), where I is the discharge current, t1 and t2 are the times when the voltage across the two ends drops to the inverter's flip threshold VTH, and C is the value of the capacitor being discharged. When the discharge current and the capacitance value remain constant, the voltage difference and the discharge time difference are linearly related. The rising edge signal of the output clock is then converted into a pulse signal by a pulse generation circuit, enabling a multi-stage differential ring oscillator structure based on the inverter. By acquiring the number of oscillation cycles and phase information of the output clock at the falling edge of the enable signal, the digital codeword is obtained, completing the conversion from analog signal to digital signal.

[0003] However, the delay of the inverter is affected by process angle, temperature, and power supply voltage, which causes the time range of the time-to-digital converter to change. At the same time, the capacitance value in the voltage-to-time converter is affected by the process angle, which affects the output time range. This results in a mismatch between the output range of the voltage-to-time converter and the quantization range of the time-to-digital converter. Summary of the Invention

[0004] The purpose of this invention is to provide a front-end calibration circuit for a time-domain analog-to-digital converter (ADC). This circuit addresses the mismatch between the output range of the voltage-to-time conversion circuit and the quantization range of the time-to-digital conversion circuit in existing time-domain ADCs under variations in process angle, temperature, and power supply voltage. The invention introduces a detection circuit at the period counting result of a ring oscillator. Under full-swing input conditions, it detects whether the counting period has reached a preset value and feeds the result back to the counter output control codeword to adjust the discharge current in the voltage-to-time conversion circuit, thereby adjusting the output time range and achieving automatic matching between the conversion range of the voltage-to-time conversion circuit and the quantization range of the time-to-digital conversion circuit.

[0005] A front-end calibration circuit for a time-domain analog-to-digital converter includes: a calibration clock generation circuit, an oscillation period detection and processing circuit, and a current adjustment circuit; The calibration clock generation circuit is connected to the oscillation period detection and processing circuit and is used to calibrate the circuit clock. The oscillation period detection and processing circuit is connected to the counter and the current adjustment circuit, and is used to detect the oscillation period and adjust the oscillation period. The current adjustment circuit is connected to the input current and is used to adjust the magnitude of the current.

[0006] Preferably, the calibration clock generation circuit includes: an asynchronous low-level reset D flip-flop (DFF0) and an asynchronous low-level reset D flip-flop (DFF1). The reset terminals RST of the asynchronous low-level reset D flip-flops (DFF0) and (DFF1) are connected to the calibration enable signal EN_CAL. The input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF0) is connected to the data acquisition clock CLK of the ring oscillator. The data input terminal D and the inverting output terminal... It is connected to the input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF1); The data input D and the inverting output of an asynchronous low-level reset D flip-flop (DFF1) Connected, inverted output terminal Connect the sampling clock CLK_SIN to the positive output terminal Q, and connect the codeword output clock CLK_DOUT to the positive output terminal Q.

[0007] Preferably, the oscillation period detection and processing circuit includes: a D flip-flop (DFF2), an asynchronous low-level reset D flip-flop (DFF3), an asynchronous low-level reset D flip-flop (DFF4), an asynchronous low-level reset D flip-flop (DFF5), an asynchronous low-level reset D flip-flop (DFF6), an asynchronous low-level set D flip-flop (DFF7), a half adder (A1), a full adder (A2), a full adder (A3), a full adder (A4), and a full adder (A5); The input D of the D flip-flop (DFF2) is connected to the period counting signal CNT, the input clock Clk is connected to the sampling clock CLK_SIN, the positive output Q is connected to the detection signal CNT_IN, and the inverting output... Connect to the detection signal CNT_INB; The input terminal A of the half-adder (A1) is connected to the signal IN. <0> Input terminal B is connected to the power supply voltage VDD, and the summation result S at output terminal is connected to the signal OUT. <0> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A2); The input terminal A of the full adder (A2) is connected to the signal IN. <1> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <1> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A3); The input terminal A of the full adder (A3) is connected to the signal IN. <2> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <2> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A4); The input terminal A of the full adder (A4) is connected to the signal IN. <3> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <3> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A5); The input terminal A of the full adder (A5) is connected to the signal IN. <4> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <4> ; The input D of the asynchronous low-level reset D flip-flop (DFF3) is connected to the signal OUT. <0> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <0> Inverting output terminal Received signal INB <0> ; The input D of the asynchronous low-level reset D flip-flop (DFF4) is connected to the signal OUT. <1> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <1> Inverting output terminal Received signal INB <1> ; The input D of the asynchronous low-level reset D flip-flop (DFF5) is connected to the signal OUT. <2> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <2> Inverting output terminal Received signal INB <2> ; The input D of the asynchronous low-level reset D flip-flop (DFF6) is connected to the signal OUT. <3> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <3> Inverting output terminal Received signal INB <3> ; The input D of the asynchronous low-level set D flip-flop (DFF7) is connected to the signal OUT. <4> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input set terminal SET is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <4> Inverting output terminal Received signal INB <4> .

[0008] Preferably, the current adjustment circuit includes: a current source (I1), a PMOS transistor (PM1), a PMOS transistor (PM2), a PMOS transistor (PM3), a PMOS transistor (PM4), a PMOS transistor (PM5), an NMOS transistor (NM1), an NMOS transistor (NM2), an NMOS transistor (NM3), an NMOS transistor (NM4), an NMOS transistor (NM5), an NMOS transistor (NM6), an NMOS transistor (NM7), an NMOS transistor (NM8), an NMOS transistor (NM9), an NMOS transistor (NM10), an NMOS transistor (NM11), an NMOS transistor (NM12), an NMOS transistor (NM13), an NMOS transistor (NM14), an NMOS transistor (NM15), an NMOS transistor (NM16), an NMOS transistor (NM17), an NMOS transistor (NM18), an NMOS transistor (NM19), and a resistor (R1), and the size ratio of the five adjustable current mirror sections is 16:8:4:2:1; The input terminal of the current source (I1) is connected to the power supply VDD, and the output terminal is connected to VB1. The two ends of the resistor (R1) are connected to VB1 and VB2. The drain of the NMOS transistor (NM6) is connected to VB2, the gate is connected to VB1, and the source is connected to the drain of the NMOS transistor (NM13). The gate of the NMOS transistor (NM13) is connected to VB2, and the source is connected to VSS. The drain of NMOS transistor (NM7) is connected to the output terminal IBout, the gate is connected to VB1, and the source is connected to the drain of NMOS transistor (NM14). The gate of NMOS transistor (NM14) is connected to VB2, and the source is connected to VSS. The drain of the NMOS transistor (NM8) is connected to the output terminal IBout, and the gate is connected to D. <0> The source is connected to the drain of the NMOS transistor (NM15), the gate of the NMOS transistor (NM15) is connected to VB2, and the source is connected to VSS; The drain of the NMOS transistor (NM9) is connected to the output terminal IBout, and the gate is connected to D. <1> The source is connected to the drain of the NMOS transistor (NM16), the gate of the NMOS transistor (NM16) is connected to VB2, and the source is connected to VSS; The drain of the MOSFET (NM10) is connected to the output terminal IBout, and the gate is connected to D. <2> The source is connected to the drain of the NMOS transistor (NM17), the gate of the NMOS transistor (NM17) is connected to VB2, and the source is connected to VSS; The drain of the NMOS transistor (NM11) is connected to the output terminal IBout, and the gate is connected to D. <3> The source is connected to the drain of the NMOS transistor (NM18), the gate of the NMOS transistor (NM18) is connected to VB2, and the source is connected to VSS; The drain of the NMOS transistor (NM12) is connected to the output terminal IBout, and the gate is connected to D. <4> The source is connected to the drain of the NMOS transistor (NM19), the gate of the NMOS transistor (NM19) is connected to VB2, and the source is connected to VSS; The drain of the PMOS transistor (PM1) is connected to the bias voltage VB2, and the gate is connected to INB. <0> The source is connected to D <0> The drain of the NMOS transistor (NM1) is connected to VSS, and the gate is connected to INB. <0> The source is connected to D <0> ; The drain of the PMOS transistor (PM2) is connected to the bias voltage VB2, and the gate is connected to INB. <1> The source is connected to D <1> The drain of the NMOS transistor (NM2) is connected to VSS, and the gate is connected to INB. <1> The source is connected to D <1> ; The drain of the PMOS transistor (PM3) is connected to the bias voltage VB2, and the gate is connected to INB. <2> The source is connected to D <2> The drain of the NMOS transistor (NM3) is connected to VSS, and the gate is connected to INB. <2> The source is connected to D <2> ; The drain of the PMOS transistor (PM4) is connected to the bias voltage VB2, and the gate is connected to INB. <3> The source is connected to D <3> The drain of the NMOS transistor (NM4) is connected to VSS, and the gate is connected to INB. <3> The source is connected to D <3> ; The drain of the PMOS transistor (PM5) is connected to the bias voltage VB2, and the gate is connected to INB. <4> The source is connected to D <4> The drain of the NMOS transistor (NM5) is connected to VSS, and the gate is connected to INB. <4> The source is connected to D <4> .

[0009] A method for controlling the front-end calibration circuit of a time-domain analog-to-digital converter, applied to the front-end calibration circuit of a time-domain analog-to-digital converter, comprising: Reset the circuit; The circuit is calibrated after reset.

[0010] Preferably, the calibration of the reset circuit includes: Sample the signal; The sampled signal is adjusted.

[0011] Preferably, resetting the circuit includes: When RST_CAL and EN_CAL are low, the outputs of D flip-flops (DFF3, DFF4, DFF5, DFF6, and DFF7) are reset. The corresponding inverting output signals INB<4:0>=01111 turn on PMOS transistors (PM1, NMOS transistors (NM2, NMOS transistors (NM3, NMOS transistors (NM4), and NMOS transistors (NM5), enabling D... <4> =VB2,D <0> D <1> D <2> D <3> All are VSS, which turns on the NMOS transistor (NM12). The input current consists of two branches: NMOS transistor (NM7), NMOS transistor (NM14) and NMOS transistor (NM12), NMOS transistor (NM19).

[0012] Preferably, the sampling of the signal includes: When the rising edge of CLK_SIN arrives, the D flip-flop (DFF2) samples the period count result CNT. If CNT is 1, it latches CNT_IN=1 and CNT_INB=0, indicating that the oscillation period exceeds the preset value. If CNT is 0, it latches CNT_IN=0 and CNT_INB=1, indicating that the oscillation period is less than the preset value. Through the subsequent processing circuit composed of half adders and full adders, when CNT_IN=1 and CNT_INB=0, the output codeword OUT<4:0> is added by 1 compared to IN<4:0>. When CNT_IN=0 and CNT_INB=1, the input codeword IN<4:0> is equivalent to adding 11111. Since the output is only 5 bits, it is equivalent to the output codeword OUT<4:0> being subtracted by 1 compared to IN<4:0>, thus completing the codeword conversion.

[0013] Preferably, adjusting the sampled signal includes: When the rising edge of CLK_DOUT arrives, the output codeword OUT<4:0> is triggered and latched as IN<4:0>. The inverted signal INB<4:0> is selected by PMOS or NMOS, and the transmission level VB2 or VSS is set to set the value of D<4:0>. Then, the conducting part in the current mirror circuit is adjusted to realize the current adjustment. When the oscillation period exceeds the preset value, the input code word is incremented by 1, the PMOS is selected, and the control terminal output is VB2. The current transistor is turned on, and the current is increased to reduce the output time range of the voltage-time converter. When the oscillation period is less than the preset value, the input code word is decremented by 1, the NMOS is selected, and the control terminal output is VSS. The current transistor is turned off, and the current is reduced to increase the output time range of the voltage-time converter.

[0014] Preferably, the calibration of the reset circuit includes: When the RST_CAL signal is high, as the rising edge of the data acquisition clock CLK of the ring oscillator arrives, the asynchronous low-level reset D flip-flops (DFF0) and (DFF1) flip-flops (DFF1) toggle their output levels under the control of the clock CLK, realizing the function of frequency division by four. The output clock CLK_SIN and CLK_DOUT frequencies are 1 / 4 of the original frequencies.

[0015] The beneficial effects of this invention are as follows: 1. By introducing a detection circuit at the period counting result of the ring oscillator, under full-swing input conditions, this invention detects whether the counting period has reached a preset value and feeds the result back to the counter to adjust the magnitude of the current source in the voltage-time conversion circuit, thereby adjusting the output time range and achieving automatic matching of the quantization range of the voltage-time conversion circuit and the time-to-digital conversion circuit. 2. The circuit design of this invention also has good PVT (process, voltage, temperature) robustness. By enabling calibration, the circuit can maintain stable performance under different process angles, supply voltages, and ambient temperatures. By feeding the detection result back to the counter, the circuit can adapt to these changes and automatically adjust to maintain a suitable matching range, thereby improving the reliability and adaptability of the circuit. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the front-end calibration circuit structure of a time-domain analog-to-digital converter according to the present invention; Figure 2 This is a schematic diagram of the calibration clock generation circuit structure of the present invention; Figure 3 This is a schematic diagram of the oscillation period detection and processing circuit structure of the present invention; Figure 4 This is a schematic diagram of the current adjustment circuit structure of the present invention; Figure 5 This is a diagram showing the adjustment results when the VTC output time range of the present invention is too large; Figure 6 This is a waveform diagram showing the adjustment when the VTC output time range of the present invention is too small. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0022] The delay of the inverter is affected by process angle, temperature, and power supply voltage, which causes the time range of the time-to-digital converter to change. At the same time, the capacitance value in the voltage-to-time converter is affected by the process angle, which affects the output time range. This results in a mismatch between the output range of the voltage-to-time converter and the quantization range of the time-to-digital converter.

[0023] This invention introduces a detection circuit at the period counting result of a ring oscillator. Under full-swing input conditions, it detects whether the counting period reaches a preset value and feeds the result back to the counter to adjust the current source in the voltage-to-time conversion circuit, thereby adjusting the output time range. This achieves automatic matching of the quantization range between the voltage-to-time conversion circuit and the time-to-digital conversion circuit. The circuit design of this invention also exhibits good PVT (process, voltage, temperature) robustness. By enabling calibration, the circuit can maintain stable performance under different process angles, supply voltages, and ambient temperatures. By feeding the detection result back to the counter, the circuit can adapt to these changes and automatically adjust to maintain a suitable matching range, thus improving the reliability and adaptability of the circuit.

[0024] Example 1 A front-end calibration circuit for a time-domain analog-to-digital converter, reference Figure 1 It includes: a calibration clock generation circuit, an oscillation period detection and processing circuit, and a current adjustment circuit; The calibration clock generation circuit is connected to the oscillation period detection and processing circuit for calibrating the circuit clock. The oscillation period detection and processing circuit is connected to the counter and the current adjustment circuit to detect and adjust the oscillation period; The current adjustment circuit is connected to the input current and is used to adjust the magnitude of the current.

[0025] Preferably, refer to Figure 2 The calibration clock generation circuit includes: an asynchronous low-level reset D flip-flop (DFF0) and an asynchronous low-level reset D flip-flop (DFF1). The reset terminals RST of the asynchronous low-level reset D flip-flops (DFF0) and (DFF1) are connected to the calibration enable signal EN_CAL. The input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF0) is connected to the data acquisition clock CLK of the ring oscillator. The data input terminal D and the inverting output terminal... It is connected to the input clock terminal Clk of the asynchronous low-level reset D flip-flop (DFF1); The data input D and the inverting output of an asynchronous low-level reset D flip-flop (DFF1) Connected, inverted output terminal Connect the sampling clock CLK_SIN to the positive output terminal Q, and connect the codeword output clock CLK_DOUT to the positive output terminal Q.

[0026] Preferably, refer to Figure 3 The oscillation period detection and processing circuit includes: D flip-flop (DFF2), asynchronous low-level reset D flip-flop (DFF3), asynchronous low-level reset D flip-flop (DFF4), asynchronous low-level reset D flip-flop (DFF5), asynchronous low-level reset D flip-flop (DFF6), asynchronous low-level set D flip-flop (DFF7), half adder (A1), full adder (A2), full adder (A3), full adder (A4), and full adder (A5); The input D of the D flip-flop (DFF2) is connected to the period counting signal CNT, the input clock Clk is connected to the sampling clock CLK_SIN, the positive output Q is connected to the detection signal CNT_IN, and the inverting output... Connect to the detection signal CNT_INB; The input terminal A of the half-adder (A1) is connected to the signal IN. <0> Input terminal B is connected to the power supply voltage VDD, and the summation result S at output terminal is connected to the signal OUT. <0> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A2); The input terminal A of the full adder (A2) is connected to the signal IN. <1> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <1> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A3); The input terminal A of the full adder (A3) is connected to the signal IN. <2> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <2> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A4); The input terminal A of the full adder (A4) is connected to the signal IN. <3> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <3> The carry result CO at the output terminal is connected to the input terminal CI of the next stage full adder (A5); The input terminal A of the full adder (A5) is connected to the signal IN. <4> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <4> ; The input D of the asynchronous low-level reset D flip-flop (DFF3) is connected to the signal OUT. <0> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <0> Inverting output terminal Received signal INB <0> ; The input D of the asynchronous low-level reset D flip-flop (DFF4) is connected to the signal OUT. <1> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <1> Inverting output terminal Received signal INB <1> ; The input D of the asynchronous low-level reset D flip-flop (DFF5) is connected to the signal OUT. <2> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <2> Inverting output terminal Received signal INB <2> ; The input D of the asynchronous low-level reset D flip-flop (DFF6) is connected to the signal OUT. <3> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <3> Inverting output terminal Received signal INB <3> ; The input D of the asynchronous low-level set D flip-flop (DFF7) is connected to the signal OUT. <4> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input set terminal SET is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <4> Inverting output terminal Received signal INB <4> .

[0027] Preferably, refer to Figure 4The current adjustment circuit includes: a current source (I1), PMOS transistors (PM1), (PM2), (PM3), (PM4), (PM5), NMOS transistors (NM1), (NM2), (NM3), (NM4), (NM5), (NM6), (NM7), (NM8), (NM9), (NM10), (NM11), (NM12), (NM13), (NM14), (NM15), (NM16), (NM17), (NM18), (NM19), and a resistor (R1). The five adjustable current mirror sections have a size ratio of 16:8:4:2:1. The input terminal of the current source (I1) is connected to the power supply VDD, and the output terminal is connected to VB1. The two ends of the resistor (R1) are connected to VB1 and VB2. The drain of the NMOS transistor (NM6) is connected to VB2, the gate is connected to VB1, and the source is connected to the drain of the NMOS transistor (NM13). The gate of the NMOS transistor (NM13) is connected to VB2, and the source is connected to VSS. The drain of NMOS transistor (NM7) is connected to the output terminal IBout, the gate is connected to VB1, and the source is connected to the drain of NMOS transistor (NM14). The gate of NMOS transistor (NM14) is connected to VB2, and the source is connected to VSS. The drain of the NMOS transistor (NM8) is connected to the output terminal IBout, and the gate is connected to D. <0> The source is connected to the drain of the NMOS transistor (NM15), the gate of the NMOS transistor (NM15) is connected to VB2, and the source is connected to VSS; The drain of the NMOS transistor (NM9) is connected to the output terminal IBout, and the gate is connected to D. <1> The source is connected to the drain of the NMOS transistor (NM16), the gate of the NMOS transistor (NM16) is connected to VB2, and the source is connected to VSS; The drain of the MOSFET (NM10) is connected to the output terminal IBout, and the gate is connected to D. <2> The source is connected to the drain of the NMOS transistor (NM17), the gate of the NMOS transistor (NM17) is connected to VB2, and the source is connected to VSS; The drain of the NMOS transistor (NM11) is connected to the output terminal IBout, and the gate is connected to D. <3> The source is connected to the drain of the NMOS transistor (NM18), the gate of the NMOS transistor (NM18) is connected to VB2, and the source is connected to VSS; The drain of the NMOS transistor (NM12) is connected to the output terminal IBout, and the gate is connected to D. <4> The source is connected to the drain of the NMOS transistor (NM19), the gate of the NMOS transistor (NM19) is connected to VB2, and the source is connected to VSS; The drain of the PMOS transistor (PM1) is connected to the bias voltage VB2, and the gate is connected to INB. <0> The source is connected to D <0> The drain of the NMOS transistor (NM1) is connected to VSS, and the gate is connected to INB. <0> The source is connected to D <0> ; The drain of the PMOS transistor (PM2) is connected to the bias voltage VB2, and the gate is connected to INB. <1> The source is connected to D <1> The drain of the NMOS transistor (NM2) is connected to VSS, and the gate is connected to INB. <1> The source is connected to D <1> ; The drain of the PMOS transistor (PM3) is connected to the bias voltage VB2, and the gate is connected to INB. <2> The source is connected to D <2> The drain of the NMOS transistor (NM3) is connected to VSS, and the gate is connected to INB. <2> The source is connected to D <2> ; The drain of the PMOS transistor (PM4) is connected to the bias voltage VB2, and the gate is connected to INB. <3> The source is connected to D <3> The drain of the NMOS transistor (NM4) is connected to VSS, and the gate is connected to INB. <3> The source is connected to D <3> ; The drain of the PMOS transistor (PM5) is connected to the bias voltage VB2, and the gate is connected to INB. <4> The source is connected to D <4> The drain of the NMOS transistor (NM5) is connected to VSS, and the gate is connected to INB. <4> The source is connected to D <4> .

[0028] Example 2 A method for controlling the front-end calibration circuit of a time-domain analog-to-digital converter, referenced Figure 5 and Figure 6 A front-end calibration circuit for a time-domain analog-to-digital converter includes: S100, reset the circuit; S200 calibrates the circuit after reset.

[0029] To further verify the technical effect of the present invention, the inventors conducted the following experiment. Using a 65nm CMOS process, a simulation was performed on the time-domain analog-to-digital converter with a calibration circuit added. A full-swing voltage was input to the circuit. When the quantization range of the voltage-time conversion circuit was large, the output quantized codeword was too large. A period count value of 1 was detected, and the current control codeword was incremented by 1. This opened the corresponding control current branch, increasing the current, accelerating the discharge rate, and decreasing the conversion time range, until the detected period value was 0. The final output codeword then fluctuated within the set value range. The simulation waveform is shown below. Figure 5As shown in the diagram. When a full-swing voltage is input to the circuit, if the quantization range of the voltage-time conversion circuit is small, the output quantized codeword is too small. Upon detecting a period count value of 0, the current control codeword is decremented by 1, correspondingly disconnecting the current branch, thus reducing the current, slowing the discharge rate, and increasing the conversion time range. This continues until the detected period value is 1, at which point the final output codeword fluctuates within the set value range. The simulation waveform is shown below. Figure 6 As shown in the figure. Simulations in both cases demonstrate that the calibration technique proposed in this invention can achieve the calibration function.

[0030] Preferably, calibrating the reset circuit includes: Sample the signal; The sampled signal is adjusted.

[0031] Preferably, resetting the circuit includes: When RST_CAL and EN_CAL are low, the outputs of D flip-flops (DFF3, DFF4, DFF5, DFF6, and DFF7) are reset. The corresponding inverting output signals INB<4:0>=01111 turn on PMOS transistors (PM1, NMOS transistors (NM2, NMOS transistors (NM3, NMOS transistors (NM4), and NMOS transistors (NM5), enabling D... <4> =VB2,D <0> D <1> D <2> D <3> All are VSS, which turns on the NMOS transistor (NM12). The input current consists of two branches: NMOS transistor (NM7), NMOS transistor (NM14) and NMOS transistor (NM12), NMOS transistor (NM19).

[0032] Preferably, sampling the signal includes: When the rising edge of CLK_SIN arrives, the D flip-flop (DFF2) samples the period count result CNT. If CNT is 1, it latches CNT_IN=1 and CNT_INB=0, indicating that the oscillation period exceeds the preset value. If CNT is 0, it latches CNT_IN=0 and CNT_INB=1, indicating that the oscillation period is less than the preset value. Through the subsequent processing circuit composed of half adders and full adders, when CNT_IN=1 and CNT_INB=0, the output codeword OUT<4:0> is added by 1 compared to IN<4:0>. When CNT_IN=0 and CNT_INB=1, the input codeword IN<4:0> is equivalent to adding 11111. Since the output is only 5 bits, it is equivalent to the output codeword OUT<4:0> being subtracted by 1 compared to IN<4:0>, thus completing the codeword conversion.

[0033] Preferably, adjusting the sampled signal includes: When the rising edge of CLK_DOUT arrives, the output codeword OUT<4:0> is triggered and latched as IN<4:0>. The inverted signal INB<4:0> is selected by PMOS or NMOS, and the transmission level VB2 or VSS is set to set the value of D<4:0>. Then, the conducting part in the current mirror circuit is adjusted to realize the current adjustment. When the oscillation period exceeds the preset value, the input code word is incremented by 1, the PMOS is selected, and the control terminal output is VB2. The current transistor is turned on, and the current is increased to reduce the output time range of the voltage-time converter. When the oscillation period is less than the preset value, the input code word is decremented by 1, the NMOS is selected, and the control terminal output is VSS. The current transistor is turned off, and the current is reduced to increase the output time range of the voltage-time converter.

[0034] Preferably, calibrating the reset circuit includes: When the RST_CAL signal is high, as the rising edge of the data acquisition clock CLK of the ring oscillator arrives, the asynchronous low-level reset D flip-flops (DFF0) and (DFF1) flip-flops (DFF1) toggle their output levels under the control of the clock CLK, realizing the function of frequency division by four. The output clock CLK_SIN and CLK_DOUT frequencies are 1 / 4 of the original frequencies.

[0035] This invention introduces a detection circuit at the period counting result of a ring oscillator. Under full-swing input conditions, it detects whether the counting period reaches a preset value and feeds the result back to the counter to adjust the current source in the voltage-to-time conversion circuit, thereby adjusting the output time range. This achieves automatic matching of the quantization range between the voltage-to-time conversion circuit and the time-to-digital conversion circuit. The circuit design of this invention also exhibits good PVT (process, voltage, temperature) robustness. By enabling calibration, the circuit can maintain stable performance under different process angles, supply voltages, and ambient temperatures. By feeding the detection result back to the counter, the circuit can adapt to these changes and automatically adjust to maintain a suitable matching range, thus improving the reliability and adaptability of the circuit.

[0036] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A front-end calibration circuit for a time-domain analog-to-digital converter, characterized in that, It includes: a calibration clock generation circuit, an oscillation period detection and processing circuit, and a current adjustment circuit; the calibration clock generation circuit is connected to the oscillation period detection and processing circuit and is used to calibrate the circuit clock; the oscillation period detection and processing circuit is connected to a counter and the current adjustment circuit and is used to detect and adjust the oscillation period. The oscillation period detection and processing circuit includes: D flip-flop DFF2, asynchronous low-level reset D flip-flops DFF3-DFF6, asynchronous low-level set D flip-flop DFF7, half adder A1, and full adders A2-A5. The input D of the D flip-flop DFF2 is connected to the period counting signal CNT, the input clock Clk is connected to the sampling clock CLK_SIN, the positive output Q is connected to the detection signal CNT_IN, and the inverting output... Connect to the detection signal CNT_INB; The input terminal A of half-adder A1 is connected to the signal IN. <0> Input terminal B is connected to the power supply voltage VDD, and the summation result S at output terminal is connected to the signal OUT. <0> The carry result CO from the output terminal is connected to the input terminal CI of the next stage full adder A2; The input terminals A of the full adders A2-A4 are respectively connected to the signal IN. <1> -IN <3> The input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the corresponding signal OUT. <1> -OUT <3> The carry-out result CO at the output terminal is connected to the input terminal CI of the next stage full adder A3-A5 respectively; The input terminal A of the full adder A5 is connected to the signal IN. <4> Input terminal B is connected to the detection signal CNT_INB, and the summation result S at the output terminal is connected to the signal OUT. <4> ; The inputs D of the asynchronous low-level reset D flip-flops DFF3-DFF6 are respectively connected to the signal OUT. <0> -OUT <3> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input reset terminal RST is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the corresponding signal IN. <0> -IN <3> Inverting output terminal Each is connected to signal INB. <0> -INB <3> ; The input D of the asynchronous low-level set D flip-flop DFF7 is connected to the signal OUT. <4> The input clock terminal Clk is connected to the codeword output clock CLK_DOUT, the input set terminal SET is connected to the reset clock signal RST_CAL, and the positive output terminal Q is connected to the signal IN. <4> Inverting output terminal Received signal INB <4> ; The codeword output clock CLK_DOUT is out of phase with the sampling clock CLK_SIN; The current adjustment circuit is connected to the input current and is used to adjust the magnitude of the current; The calibration clock generation circuit is a frequency divider circuit composed of D flip-flops; The oscillation period detection and processing circuit is used to detect the oscillation period, adjust the codeword, and then output the codeword. The calibration clock generation circuit outputs a clock to control the D flip-flop to sample the period count value, and then the codeword is adjusted through an addition circuit composed of a half adder and a full adder. The calibration clock generation circuit outputs a clock to control the D flip-flop to output the adjusted codeword. The current adjustment circuit adjusts the output current value according to the codeword, including a current mirror circuit composed of MOSFETs and a multi-channel proportional current output circuit controlled by switches.

2. The front-end calibration circuit of a time-domain analog-to-digital converter according to claim 1, characterized in that, The calibration clock generation circuit includes: an asynchronous low-level reset D0 flip-flop DFF0 and an asynchronous low-level reset D1 flip-flop DFF1; the reset terminal RST of the asynchronous low-level reset D0 flip-flop DFF0 and the asynchronous low-level reset D1 flip-flop DFF1 is connected to the calibration enable signal EN_CAL; the input clock terminal Clk of the asynchronous low-level reset D0 flip-flop DFF0 is connected to the data acquisition clock CLK of the ring oscillator; and the data input terminal D and the inverting output terminal... It is connected to the input clock terminal Clk of the asynchronous low-level reset D1 flip-flop DFF1; Asynchronous low-level reset D1 flip-flop DFF1's data input D and inverting output terminal Connected, inverted output terminal Connect the codeword output clock CLK_DOUT, and connect the positive output terminal Q to the sampling clock CLK_SIN.

3. The front-end calibration circuit of a time-domain analog-to-digital converter according to claim 2, characterized in that, The current adjustment circuit includes: a current source I1, PMOS transistors PM1, PM2, PM3, PM4, PM5, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, NMOS transistors NM6, NMOS transistors NM7, NMOS transistors NM8, NMOS transistors NM9, NMOS transistors NM10, NMOS transistors NM11, NMOS transistors NM12, NMOS transistors NM13, NMOS transistors NM14, NMOS transistors NM15, NMOS transistors NM16, NMOS transistors NM17, NMOS transistors NM18, NMOS transistors NM19, and a resistor R1. The size ratio of the five adjustable current mirror sections is 16:8:4:2:

1. The input terminal of current source I1 is connected to power supply VDD, and the output terminal is connected to VB1. One end of resistor R1 is connected to VB1, and the other end is connected to VB2. The drain of NMOS transistor NM6 is connected to VB2, the gate is connected to VB1, and the source is connected to the drain of NMOS transistor NM13. The gate of NMOS transistor NM13 is connected to VB2, and the source is connected to VSS. The drain of NMOS transistor NM7 is connected to the output terminal IBout, the gate is connected to VB1, and the source is connected to the drain of NMOS transistor NM14. The gate of NMOS transistor NM14 is connected to VB2, and the source is connected to VSS. The drain of NMOS transistor NM8 is connected to the output terminal IBout, and the gate is connected to D. <0> The source is connected to the drain of the NMOS transistor NM15, the gate of the NMOS transistor NM15 is connected to VB2, and the source is connected to VSS. The drain of NMOS transistor NM9 is connected to the output terminal IBout, and the gate is connected to D. <1> The source is connected to the drain of the NMOS transistor NM16, the gate of the NMOS transistor NM16 is connected to VB2, and the source is connected to VSS. The drain of MOSFET NM10 is connected to the output terminal IBout, and the gate is connected to D. <2> The source is connected to the drain of NMOS transistor NM17, the gate of NMOS transistor NM17 is connected to VB2, and the source is connected to VSS. The drain of NMOS transistor NM11 is connected to the output terminal IBout, and the gate is connected to D. <3> The source is connected to the drain of the NMOS transistor NM18, the gate of the NMOS transistor NM18 is connected to VB2, and the source is connected to VSS. The drain of the NMOS transistor NM12 is connected to the output terminal IBout, and the gate is connected to D. <4> The source is connected to the drain of NMOS transistor NM19, the gate of NMOS transistor NM19 is connected to VB2, and the source is connected to VSS. The drain of PMOS transistor PM1 is connected to the bias voltage VB2, and the gate is connected to INB. <0> The source is connected to D <0> The drain of NMOS transistor NM1 is connected to VSS, and the gate is connected to INB. <0> The source is connected to D <0> ; The drain of PMOS transistor PM2 is connected to the bias voltage VB2, and the gate is connected to INB. <1> The source is connected to D <1> The drain of NMOS transistor NM2 is connected to VSS, and the gate is connected to INB. <1> The source is connected to D <1> ; The drain of PMOS transistor PM3 is connected to the bias voltage VB2, and the gate is connected to INB. <2> The source is connected to D <2> The drain of NMOS transistor NM3 is connected to VSS, and the gate is connected to INB. <2> The source is connected to D <2> ; The drain of PMOS transistor PM4 is connected to the bias voltage VB2, and the gate is connected to INB. <3> The source is connected to D <3> The drain of NMOS transistor NM4 is connected to VSS, and the gate is connected to INB. <3> The source is connected to D <3> ; The drain of PMOS transistor PM5 is connected to the bias voltage VB2, and the gate is connected to INB. <4> The source is connected to D <4> The drain of NMOS transistor NM5 is connected to VSS, and the gate is connected to INB. <4> The source is connected to D <4> .

4. A method for controlling the front-end calibration circuit of a time-domain analog-to-digital converter, applied to the front-end calibration circuit of a time-domain analog-to-digital converter as described in any one of claims 1-3, characterized in that, include: Reset the circuit; The circuit is calibrated after reset.

5. The front-end calibration circuit control method for a time-domain analog-to-digital converter according to claim 4, characterized in that, The calibration of the reset circuit includes: Sample the signal; The sampled signal is adjusted.

6. The front-end calibration circuit control method for a time-domain analog-to-digital converter according to claim 4, characterized in that, The circuit reset includes: When RST_CAL and EN_CAL are low, the outputs of D flip-flops DFF3, DFF4, DFF5, DFF6 (asynchronous low-level reset), and DFF7 (asynchronous low-level set) are reset. The corresponding inverting output signal INB<4:0>=01111 turns on PMOS transistors PM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, and NMOS transistors NM5, thus enabling D... <4> =VB2,D <0> D <1> D <2> D <3> All are VSS, which turns on NMOS transistor NM12. The input current consists of two branches: NMOS transistors NM7 and NM14, and NMOS transistors NM12 and NM19.

7. The front-end calibration circuit control method for a time-domain analog-to-digital converter according to claim 5, characterized in that, The sampling of the signal includes: When the rising edge of CLK_SIN arrives, the D flip-flop DFF2 samples the period count result CNT. If CNT is 1, it latches CNT_IN=1 and CNT_INB=0, indicating that the oscillation period exceeds the preset value. If CNT is 0, it latches CNT_IN=0 and CNT_INB=1, indicating that the oscillation period is less than the preset value. Through the subsequent processing circuit composed of half adders and full adders, when CNT_IN=1 and CNT_INB=0, the output codeword OUT<4:0> is added by 1 compared to IN<4:0>. When CNT_IN=0 and CNT_INB=1, the input codeword IN<4:0> is equivalent to adding 11111. Since the output is only 5 bits, it is equivalent to the output codeword OUT<4:0> being subtracted by 1 compared to IN<4:0>, thus completing the codeword conversion.

8. The front-end calibration circuit control method for a time-domain analog-to-digital converter according to claim 5, characterized in that, The adjustment of the sampled signal includes: When the rising edge of CLK_DOUT arrives, the output codeword OUT<4:0> is triggered and latched as IN<4:0>. The inverted signal INB<4:0> selects the PMOS and NMOS transmission levels VB2 or VSS to set the value of D<4:0>. Then, the conducting part in the current mirror circuit is adjusted to achieve current adjustment. When the oscillation period exceeds the preset value, the input code word is incremented by 1, the PMOS is selected, and the control terminal output is VB2. The current transistor is turned on, and the current is increased to reduce the output time range of the voltage-time converter. When the oscillation period is less than the preset value, the input code word is decremented by 1, the NMOS is selected, and the control terminal output is VSS. The current transistor is turned off, and the current is reduced to increase the output time range of the voltage-time converter.

9. The front-end calibration circuit control method for a time-domain analog-to-digital converter according to claim 4, characterized in that, The calibration of the reset circuit includes: When the RST_CAL signal is high, as the rising edge of the data acquisition clock CLK of the ring oscillator arrives, the asynchronous low-level reset D0 flip-flop DFF0 and the asynchronous low-level reset D1 flip-flop DFF1 flip-flop toggles their output levels under the control of the clock CLK, realizing the function of frequency division by four. The output clock CLK_SIN and CLK_DOUT frequencies are 1 / 4 of the original frequencies.

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