Image sensor and image sensing apparatus including the same

Abstract

An image sensor and an image sensing apparatus including the same are provided. The image sensor includes: a pixel array including a plurality of unit pixels; and a driving circuit disposed around the pixel array and driving the plurality of unit pixels. Each of the plurality of unit pixels includes a first region and a second region. The first region includes a first photodiode, a first pass transistor connected to the first photodiode, a first floating diffusion node connected to the first pass transistor, and a (1-1) th contact connected to a second floating diffusion node, and the second region includes a second photodiode, a second transfer transistor connected to the second photodiode, a (1-2) th contact electrically connected to the (1-1) th contact through a connection metal wiring, and a second contact provided to a third floating diffusion node connected to the second transfer transistor.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0142081 filed on October 23, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosure relates to an image sensing device including an image sensor. Background Art

[0003] An image sensing device is a type of semiconductor device that converts optical information (eg, incident light) into an electrical signal. Examples of image sensing devices include a charge coupled device (CCD) image sensing device and a complementary metal oxide semiconductor (CMOS) image sensing device.

[0004] A CMOS image sensor (CIS) includes a two-dimensional (2D) array of a plurality of pixels. Each of the pixels may include, for example, a photodiode (PD) that converts incident light into an electrical signal.

[0005] Recently, with the development of computer and telecommunication industries, the demand for image sensors with improved performance has been increasing in various fields including those of digital cameras, camcorders, smart phones, game devices, surveillance cameras, medical micro cameras, robots, vehicles, etc. Summary of the invention

[0006] The disclosed aspects provide an image sensor having improved dark signal non-uniformity (DSNU) in a high dynamic range (HDR) environment and an image sensing device having enhanced image quality.

[0007] The disclosed aspects also provide a vehicle or mobile device including an image sensor with improved DSNU in an HDR environment.

[0008] However, aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0009] According to one aspect of the disclosure, an image sensor is provided, comprising: a pixel array comprising a plurality of unit pixels; and a driving circuit configured to drive the plurality of unit pixels, wherein each of the plurality of unit pixels comprises a first region and a second region, the first region comprising a first photodiode, a first transfer transistor connected to the first photodiode, a first floating diffusion node connected to the first transfer transistor, and a first contact connected to the second floating diffusion node, and the second region comprising a second photodiode, a second transfer transistor connected to the second photodiode, a second contact electrically connected to the first contact via a metal wiring connection, and a third contact arranged to a third floating diffusion node connected to the second transfer transistor.

[0010] According to another aspect of the disclosure, an image sensor is provided, comprising: a pixel array comprising a plurality of unit pixels; and a driving circuit configured to drive the plurality of unit pixels, wherein each of the plurality of unit pixels comprises a first region and a second region, the first region comprising a first photodiode, a first transfer transistor connected to the first photodiode, a first floating diffusion node connected to the first transfer transistor, a first contact connected to the second floating diffusion node, and a second contact, and the second region comprising a second photodiode, a second transfer transistor connected to the second photodiode, and a third contact connected to a third floating diffusion node together with the second contact.

[0011] According to another aspect of the disclosure, an image sensing device is provided, which includes: a pixel array including a plurality of unit pixels; and a driving circuit configured to drive the plurality of unit pixels, wherein each of the plurality of unit pixels includes: a first transfer transistor connected between a first photodiode and a first floating diffusion node; a photodiode switching transistor connected between the first floating diffusion node and a second floating diffusion node, the photodiode switching transistor being configured to be turned on based on a photodiode switching control signal; a second transfer transistor connected between the second photodiode and a third floating diffusion node; a metal capacitor connected between the third floating diffusion node and a fourth floating diffusion node; and a first connection transistor connected between the fourth floating diffusion node and a first power line, the first connection transistor being configured to be turned on based on a capacitor connection control signal.

[0012] It should be noted that the effects of the disclosure are not limited to the effects described above, and other effects of the disclosure will be clear from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the disclosure will become more apparent by describing in detail exemplary embodiments of the disclosure with reference to the attached drawings.

[0014] Figure 1 is a block diagram of an image sensing device according to a disclosed embodiment.

[0015] Figure 2 is a top view of a pixel array according to a disclosed embodiment.

[0016] Figure 3 is a pixel map of a unit pixel according to a disclosed embodiment.

[0017] Figure 4 It is shown Figure 3 Signal diagram of the operation of a unit pixel.

[0018] Figure 5 is a circuit diagram of a unit pixel according to a disclosed embodiment.

[0019] Figure 6 It is shown Figure 5 Schematic diagram of the layout of unit pixels.

[0020] Figure 7 yes Figure 6 Layout diagram of unit pixels.

[0021] Figure 8 is a circuit diagram of a unit pixel according to an embodiment.

[0022] Fig. 9 It is shown Figure 8 Schematic diagram of the layout of unit pixels.

[0023] Fig.10 yes Fig. 9 Layout diagram of unit pixels.

[0024] Fig.11 is a schematic diagram of a vehicle including an image sensor according to a disclosed embodiment. DETAILED DESCRIPTION

[0025] The disclosed embodiments will be described with reference to the accompanying drawings.

[0026] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the method, device and / or system described herein will be clear. For example, the order of operations described herein is only an example, and the order of operations is not limited to the order of operations set forth herein, but can be changed as will be clear after understanding the disclosure of the present application, except for the operations that must occur in a specific order. In addition, for greater clarity and simplicity, the description of known features after understanding the disclosure of the present application can be omitted.

[0027] The features described herein may be implemented in different forms and are not to be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be clear after understanding the disclosure of this application.

[0028] Throughout the specification, when a component is described as being "connected to" or "coupled to" another component, the component may be directly "connected to" or "coupled to" the other component, or there may be one or more other components placed between them. Conversely, when an element is described as being "directly connected to" or "directly coupled to" another element, there may be no other elements placed between them. Similarly, similar expressions (such as "between" and "immediately between" and "adjacent to" and "directly adjacent to") are also interpreted in the same manner. As used herein, the term "and / or" includes any one of the relevant listed items and any combination of any two or more.

[0029] Although terms such as "first," "second," and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, a first member, component, region, layer, or portion referred to may also be referred to as a second member, component, region, layer, or portion.

[0030] The terms used herein are only used to describe various examples, and are not used to limit disclosure. Unless the context clearly indicates otherwise, the articles "one (kind / person)" and "the (said)" are intended to also include plural forms. The terms "include", "comprise" and "have" specify the existence of stated features, numbers, operations, components, elements and / or their combinations, but do not exclude the existence or addition of one or more other features, numbers, operations, components, elements and / or their combinations. As used herein, the expression "at least one of ..." after a column of elements modifies the entire column of elements, without modifying the individual elements in the column. For example, the expression "at least one of a, b and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b and c.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by ordinary technicians in the field to which the present disclosure belongs, and are based on the understanding of the disclosure of the present application. Unless explicitly defined as such herein, terms (such as terms defined in commonly used dictionaries) will be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the disclosure of the present application, and will not be interpreted in an idealized or overly formal sense. The use of the term "may" with respect to an example or embodiment herein (for example, with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature, and all example embodiments are not limited thereto.

[0032] The disclosed embodiments are example embodiments, and therefore, the disclosure is not limited thereto and may be implemented in various other forms. As is conventional in the art, the embodiments may be described and illustrated in terms of blocks that perform the described functions or multiple functions as shown in the accompanying drawings. These blocks (which may be referred to herein as units or modules, etc., or named as devices, logic, circuits, counters, comparators, generators, converters, etc.) may be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc., and may be implemented or driven by software and / or firmware (configured to perform the functions or operations described herein).

[0033] Figure 1 is a block diagram of an image sensing device according to a disclosed embodiment.

[0034] Reference Figure 1 , the image sensing device 1 may include an image sensor 100 and an image signal processor 200. However, the disclosure is not limited thereto, and thus, the image sensing device 1 may include one or more other components.

[0035] According to an embodiment, the image sensor 100 may include a controller 1110, a timing generator 1120, a row driver 1130, a readout circuit 1150, a ramp signal generator 1160, and a buffer 1170. However, the disclosure is not limited thereto, and therefore, according to another embodiment, Figure 1 One or more of the components shown in the figure may be combined or deleted. In addition, according to another embodiment, one or more components may be added to the Figure 1Components shown in . Image sensor 100 may generate pixel signal SIG_PX based on incident light on image sensor 100. For example, image sensor 100 may generate pixel signal SIG_PX by sensing an image of a target using light sensing. In one embodiment, pixel signal SIG_PX may be, for example, a digital signal, but the disclosure is not limited thereto. Pixel signal SIG_PX may also include a specific signal voltage or a reset voltage.

[0036] The pixel signal SIG_PX may be provided to the image signal processor 200. For example, the pixel signal SIG_PX may be provided to the image signal processor 200 to be processed by the image signal processor 200. The image signal processor 200 may receive the pixel signal SIG_PX output from the buffer 1170 of the image sensor 100 and process or manipulate the pixel signal SIG_PX for display purposes.

[0037] In one embodiment, the image signal processor 200 may perform digital binning on the pixel signal SIG_PX output from the image sensor 100. In this case, the pixel signal SIG_PX output from the image sensor 100 may be a raw image signal from the pixel array PA that has not undergone analog binning, or a pixel signal SIG_PX that has undergone analog binning.

[0038] In one embodiment, the image sensor 100 and the image signal processor 200 may be arranged separately from each other. For example, the image sensor 100 may be mounted on a first chip, and the image signal processor 200 may be mounted on a second chip and communicate with the image sensor 100 through a predetermined interface. However, the disclosure is not limited to this example. Alternatively, the image sensor 100 and the image signal processor 200 may be implemented as a single package (such as a multi-chip package (MCP)).

[0039] The image sensor 100 includes a pixel array PA and a driver circuit. The driver circuit is disposed adjacent to the pixel array PA. For example, the driver circuit may be disposed around the pixel array PA. The driver circuit may be configured to drive the pixel array PA in units of unit pixels. According to an embodiment, the driver circuit may include, for example, a controller 1110, a timing generator 1120, a row driver 1130, a readout circuit 1150, a ramp signal generator 1160, and a buffer 1170.

[0040] The controller 1110 may control the overall operation of the image sensor 100. For example, the controller 1110 may directly send an operation signal to the timing generator 1120, the ramp signal generator 1160, and the buffer 1170. According to an embodiment, the controller 1110 may be referred to as a control register block or a controller circuit.

[0041] The timing generator 1120 may generate a signal used as a reference for operation timing of various components of the image sensor 100. The signal generated by the timing generator 1120 may be transmitted to the row driver 1130, the readout circuit 1150, and the ramp signal generator 1160. According to an embodiment, the timing generator 1120 may be referred to as a timing generator circuit.

[0042] The ramp signal generator 1160 may generate and send a ramp signal for use in the readout circuit 1150. For example, the readout circuit 1150 may include a correlated double sampler (CDS) and a comparator, and the ramp signal generator 1160 may generate and send a ramp signal for use in the CDS and the comparator. According to an embodiment, the ramp signal generator 1160 may be referred to as a ramp signal circuit.

[0043] The buffer 1170 may include, for example, a latch. The buffer 1170 may temporarily store a pixel signal SIG_PX to be provided externally, and may transmit the pixel signal SIG_PX to an external memory or device. The buffer 1170 may include a memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0044] The pixel array PA may sense an external image. The pixel array PA may include a plurality of pixels (or a plurality of unit pixels). The row driver 1130 may selectively activate rows of the pixel array PA.

[0045] The readout circuit 1150 may sample a pixel signal provided from the pixel array PA, compare the sampled pixel signal with a ramp signal, and may convert an analog image signal (or analog image data) into a digital image signal (or digital image data) based on a result of the comparison.

[0046] Figure 2 is a top view of a pixel array according to a disclosed embodiment.

[0047] Reference Figure 2 , the pixel array PA may include a plurality of unit pixels UP. For example, the plurality of unit pixels UP may be arranged in a first direction X and a second direction Y. For example, the plurality of unit pixels UP may be regularly or repeatedly arranged in the first direction X and the second direction Y. Here, the plurality of unit pixels UP may be units that receive light and output an image corresponding to one pixel.

[0048] According to some example cases, a high dynamic range (HDR) of at least 120 dB to 140 dB may be necessary. For example, an image sensor for automotive use may require such HDR. In order to meet such HDR, the image sensor 100 may be implemented with unit pixels UP containing different types of photodiodes. For example, each unit pixel UP may include at least one large photodiode and at least one small photodiode. Each unit pixel UP may include a first region REG1 corresponding to the large photodiode and a second region REG2 corresponding to the small photodiode. The first region REG1 and the second region REG2 may be distinguished in a top view. The first region REG1 may be in the shape of a first polygon (such as, for example, an octagon), and the second region REG2 may be in the shape of a second polygon (such as, for example, a quadrilateral). However, the disclosure is not limited, and therefore, the first region REG1 and the second region REG2 may have other shapes. The first region REG1 and the second region REG2 may contact each other. The first region REG1 and the second region REG2 have different sensitivities. For example, the second region REG2 may have a relatively small sensitivity, and the first region REG1 may have a greater sensitivity than the second region REG2.

[0049] According to an embodiment, the first region REG1 and the second region REG2 may be of different sizes. For example, the first region REG1 may be larger than the second region REG2. That is, the amount of light incident on the first region REG1 may be greater than the amount of light incident on the second region REG2. Each of the plurality of unit pixels UP including the first region REG1 and the second region REG2 may convert light into an electrical signal.

[0050] In the example case of implementing HDR by adjusting the exposure time in the image sensor 100, problems such as light emitting diode (LED) flicker mitigation arise. Since the LED light source used in vehicles and road traffic operates at a frequency of more than 90 Hz and involves many flicker frequencies, the image sensor 100 prevents losses that may be caused by flicker components in the actual measurement signal by setting the effective integration time (EIT) to be longer than the flicker cycle of the LED light source. Therefore, because the image sensor 100 includes a large photodiode with higher sensitivity in the first region REG1 and a small photodiode with lower sensitivity in the second region REG2, the image sensor 100 can be less affected by flicker events while achieving HDR performance. In addition, since the image sensor 100 also includes a metal capacitor to store overflowing charges from the small photodiode, the HDR performance of the image sensor 100 can be enhanced. However, in the example case of reading a signal from a metal capacitor, charge domain sampling (CDS) is not feasible, which may cause leakage current in the switching transistor of the metal capacitor. As the EIT increases, the leakage current between the metal capacitor and the switching transistor may increase, which may lead to deterioration of dark signal non-uniformity (DSNU) and reduction of the signal-to-noise ratio (SNR).

[0051] Figure 3 is a pixel map of a unit pixel according to a disclosed embodiment.

[0052] Reference Figure 2 and Figure 3 , a pixel circuit of a unit pixel UP in the pixel array PA includes a first photodiode LPD, a second photodiode SPD, a plurality of transistors, and a metal capacitor C. The plurality of transistors may include a first transfer transistor TR1, a second transfer transistor TR7, a source follower transistor TR2, a selection transistor TR3, a reset transistor TR5, a connection transistor TR6, a photodiode switch transistor TR4, and a capacitor connection transistor TR8. According to an embodiment, a first transfer signal LTG may be applied to the first transfer transistor TR1, and a second transfer signal STG may be applied to the second transfer transistor TR7.

[0053] The first subpixel REG1 includes a first photodiode LPD and a first transfer transistor TR1, and the second subpixel REG2 may include a second photodiode SPD and a second transfer transistor TR7. The first subpixel REG1 corresponds to Figure 2 The first region REG1 and the second sub-pixel REG2 correspond to Figure 2 The second region REG2. Figure 2 The first photodiode LPD included in the relatively large first region REG1 in a plan view of FIG. Figure 2The second photodiode SPD included in the relatively small second region REG2 in the plan view of FIG. 1 may be referred to as a small photodiode. For example, the first photodiode LPD may be larger than the second photodiode SPD.

[0054] The first sub-pixel REG1 and the second sub-pixel REG2 may share a source follower transistor TR2 , a selection transistor TR3 , and a reset transistor TR5 .

[0055] For example, the first transfer transistor TR1 may be disposed between the first photodiode LPD and the first node FD1. The first node FD1 may be connected to the first floating diffusion region FD1, or the first node FD1 itself may be the first floating diffusion region FD1. The gate of the first transfer transistor TR1 is connected to the first transfer line to receive the first transfer signal LTG.

[0056] The source follower transistor TR2 may be connected between a first power line VDDA providing a first power voltage and an output signal line VOUT. A gate of the source follower transistor TR2 may be connected to a first node FD1.

[0057] The selection transistor TR3 may be disposed between the source follower transistor TR2 and the output signal line VOUT. A gate of the selection transistor TR3 may be connected to a selection line of a corresponding row to receive a selection signal SEL.

[0058] The photodiode switch transistor TR4 and the reset transistor TR5 may be arranged between the first node FD1 and the first power supply line VDDA providing the first power supply voltage. A common node between the photodiode switch transistor TR4 and the reset transistor TR5 is defined as a second node FD2. The photodiode switch transistor TR4 may be located between the first node FD1 and the second node FD2. The gate of the photodiode switch transistor TR4 may be connected to a connection signal line. The photodiode switch transistor TR4 may connect the first node FD1 to the second node FD2 according to a photodiode switch control signal DRG provided from the connection signal line. The reset transistor TR5 may be arranged between the first power supply line VDDA and the second node FD2. The gate of the reset transistor TR5 may be connected to a reset line to receive a reset signal RG.

[0059] The second transfer transistor TR7 and the connecting transistor TR6 may be disposed between the second photodiode SPD and the second node FD2. The common node between the second transfer transistor TR7 and the connecting transistor TR6 may be defined as the third node FD3. The second transfer transistor TR7 is connected between the second photodiode SPD and the third node FD3. The third node FD3 may be connected to the second node FD2. The gate of the second transfer transistor TR7 may be connected to the second transfer line. The second transfer line applies a second transfer signal STG as a scanning signal different from the first transfer signal LTG from the first transfer line, and therefore, the first transfer transistor TR1 and the second transfer transistor TR7 may be turned on and off at different times. For example, the first transfer transistor TR1 and the second transfer transistor TR7 may be turned on and off independently or separately from each other. However, the disclosure is not limited thereto, and therefore, the first transfer transistor TR1 and the second transfer transistor TR7 may be turned on and off at the same time.

[0060] The connection transistor TR6 may be disposed between the third node FD3 and the second node FD2. A gate of the connection transistor TR6 is connected to the switch control line. The connection transistor TR6 may connect the third node FD3 and the second node FD2 according to a connection control signal SW.

[0061] In one embodiment, the metal capacitor C may be provided between the third node FD3 and the fourth node (or fourth diffusion node) FD4. The capacitor connection transistor TR8 may be connected between the fourth node FD4 and the first power supply line VDDA. The capacitor connection transistor TR8 may store overflowing charges from the second photodiode SPD in the metal capacitor C according to the capacitor connection signal TSW. However, the disclosure is not limited thereto, and therefore, according to some circumstances, the capacitor connection transistor TR8 may not store overflowing charges from the second photodiode SPD in the metal capacitor C according to the capacitor connection signal TSW.

[0062] In one embodiment, a power connection transistor TR9 may be further included to connect a common node between the first power line VDDA and the capacitor connection transistor TR8 and a common node between the first power line VDDA and the reset transistor TR5 according to a power connection signal DSW.

[0063] Figure 4 It is shown Figure 3 Signal diagram of the operation of a unit pixel.

[0064] Figure 4 1 shows the timing of the signal applied to the unit pixel UP located in the row to be read out. However, the disclosure is not limited thereto, and therefore, Figure 4 A signal different from the signal shown in FIG. 1 may be applied to the unit pixels UP in the row not selected as the target to be read out. For example, Figure 4A signal waveform before or after the signal waveform shown in may be applied to the unit pixels UP from a row which is not selected as a target to be read out.

[0065] According to an embodiment, Figure 4 The waveforms of the selection signal SEL, the reset signal RG, the photodiode switch control signal DRG, the connection control signal SW, the capacitor connection signal TSW, the second transmission signal STG, and the first transmission signal LTG are shown. Each signal waveform can swing between a high level voltage and a low level voltage. Figure 4 In the embodiment shown in FIG. 1 , a high level voltage is used as a turn-on signal to activate each applied transistor, and a low level voltage is used as a turn-off signal to deactivate each applied transistor. However, the disclosure is not limited thereto, and therefore, according to another embodiment, each transistor may be turned off by a high level voltage and turned on by a low level voltage.

[0066] Before the readout period, the reset signal RG, the photodiode switch control signal DRG and the capacitor connection signal TSW maintain a high level, while the connection control signal SW, the second transfer signal STG and the first transfer signal LTG maintain a low level. For example, before the readout period, the selection signal SEL may be at a low level.

[0067] During the period from point R1 to point S1 corresponding to the first operation phase, as the selection signal SEL turns to a high level, the reset signal RG and the photodiode switch control signal DRG turn from a high level to a low level, a reset operation is performed, and the charge accumulated at the first node FD1 is converted to a first reset voltage by the source follower transistor TR2 and output to the output signal line VOUT. In the first operation phase, the first transfer signal LTG is switched from a low level to a high level and then to a low level. While the first transfer signal LTG maintains a high level, the first transfer transistor TR1 may be turned on for a predetermined amount of time and then may be turned off. While the first transfer transistor TR1 is turned on, the first node FD1 may be connected to the first photodiode LPD. As a result, the charge stored in the first photodiode LPD may be transferred to the first node (or the first floating diffusion area) FD1. The charge transferred to the first node (or the first floating diffusion area) FD1 may be converted into a first signal voltage VS1 by the source follower transistor TR2 and output to the output signal line VOUT.

[0068] In the second operation phase after the first operation phase, the second signal operation S2 may be performed first, and then the second reset operation R2 may be performed. The photodiode switch control signal DRG is switched from a low level to a high level at the S2 point, turning on the photodiode switch transistor TR4 to connect the first node FD1 to the second node FD2. After the point S2, the reset signal RG is switched from a low level to a high level and then to a low level, and the second reset operation is performed at the point R2. The second reset operation resets both the connected first node FD1 and the second node FD2, converts the charge into a second reset voltage VS2 through the source follower transistor TR2, and outputs the second reset voltage VS2 to the output signal line VOUT.

[0069] In the third operation phase after the second operation phase, the third reset operation R3 may be performed first, and then the third signal operation S3 may be performed. During the period between the points R2 and R3, the connection control signal SW changes from a low level to a high level, turning on the connection transistor TR6, and the capacitor connection signal TSW changes from a high level to a low level, turning off the capacitor switch transistor TR8. As a result, the second node FD2, the third node FD3, and the fourth node FD4 are connected together, and the fourth node FD4 is disconnected from the first power line VDDA.

[0070] During the period from point R3 to point S3, the second transfer signal STG switches from a low level to a high level and then to a low level. The connection control signal SW maintains a high level, and the capacitor connection signal TSW maintains a low level. While the second transfer signal STG switches from a low level to a high level and then to a low level, the second transfer transistor TR7 may be turned on for a predetermined amount of time and then may be turned off. While the second transfer transistor TR7 is turned on, the third node FD3 may be connected to the second photodiode SPD. As a result, the charge stored in the second photodiode SPD is transferred to the floating diffusion region of the third node FD3, the charge stored in the third node FD3 may be transferred to the second node FD2 connected to the third node FD3 through the turned-on connection transistor TR6, and the charge transferred to the second node FD2 may be transferred to the first node FD1 through the turned-on switch transistor TR4. The charge at the first node FD1 may be converted into a third signal voltage VS3 by the source follower transistor TR2 and then may be output. The third signal voltage VS3 does not include the output of the charge accumulated in the metal capacitor C when the capacitor connection transistor TR8 is turned off. In addition, since the capacitor connection transistor TR8 connected between the first power line VDDA and the fourth node FD4 is turned off by the capacitor connection signal TSW, there may be no leakage current from the charges accumulated in the metal capacitor C to the first power line VDDA or the power connection transistor TR9.

[0071] In the fourth operation phase after the third operation, the fourth signal operation S4 may be performed first, and then the fourth reset operation R4 may be performed. During the period from point S3 to point S4, the capacitor connection signal TSW may be switched from a low level to a high level. Therefore, the metal capacitor C is connected to the third node FD3, and the overflowing charge from the third node FD3 is accumulated in the metal capacitor C. As a result of the conduction of the connection transistor TR6 and the switching transistor TR4, the first node FD1, the second node FD2, and the third node FD3 may all be connected together, and the accumulated charge in the first node FD1, the second node FD2, the third node FD3, and the metal capacitor C may be converted into a fourth signal voltage VS4 through the source follower transistor TR2, and then may be output.

[0072] During the period from point S4 to point R4, the reset signal RG switches from a low level to a high level and then to a low level, while the connection control signal SW, the photodiode switch control signal DRG, and the capacitor connection signal TSW maintain a high level. As the connection transistor TR6, the capacitor connection transistor TR8, and the switch transistor TR4 are turned on by the connection control signal SW, the capacitor connection signal TSW, and the photodiode switch control signal DRG, respectively, the first node FD1, the second node FD2, the third node FD3, and the fourth node FD4 are connected together. While the reset transistor TR5 is turned on, the first node FD1, the second node FD2, the third node FD3, and the fourth node FD4 can be reset based on the first power line VDDA, and the charges accumulated in the first node FD1, the second node FD2, the third node FD3, and the fourth node FD4 can be converted and output as the fifth signal voltage VS5 through the source follower transistor TR2.

[0073] After the fourth operation stage or point R4 , the selection signal SEL switches from the high level to the low level to deactivate the unit pixel UP.

[0074] In short, the first operation stage may include outputting the charge generated by the first photodiode LPD as the first output signal VS1, the second operation stage may include turning on the reset transistor TR5 to reset the residual charge accumulated at the first node FD1 and the second node FD2 and outputting it as the second output signal VS2, and the third operation stage may include outputting the charge generated by the second photodiode SPD as the third output signal VS3. In addition, the fourth operation stage may include storing the charge generated by the second photodiode SPD but overflowing from the third node FD3 in the metal capacitor C and outputting the stored overflowing charge as the fourth output signal VS4, and the fifth operation stage may include resetting the residual charge in the first node FD1, the second node FD2, the third node FD3, the fourth node FD4 and the metal capacitor C when the first operation stage, the second operation stage, the third operation stage and the fourth operation stage are completed and outputting it as the fifth output signal VS5.

[0075] Figure 5 is a circuit diagram of a unit pixel according to a disclosed embodiment, Figure 6 It is shown Figure 5 A diagram of the layout of a unit pixel, and Figure 7 yes Figure 6 Layout diagram of unit pixels.

[0076] In one embodiment, the first photodiode LPD and the second photodiode SPD of the unit pixel UP may be connected to the second node FD2. As a result, the third node FD3 may be implemented with a single contact.

[0077] Reference Figure 5 and Figure 6 , a first photodiode LPD, a first transfer transistor TR1, a source follower transistor TR2, a selection transistor TR3, a reset transistor TR5, a photodiode switch transistor TR4, a capacitor connection transistor TR8, a power supply connection transistor TR9, a first node FD1, a second node FD2 and a fourth node FD4 are arranged in a first region ( Figure 2 The second photodiode SPD, the second transfer transistor TR7, the connection transistor TR6, the metal capacitor C and the third node FD3 are arranged in the second region ( Figure 2 The boundary between the first region REG1 and the second region REG2 may be defined by a front deep trench isolation (FDTI). The pixel circuit of the unit pixel UP is as follows: Figure 3 , therefore, its redundant description will be omitted.

[0078] Reference Figure 6 , the second node FD2 (see Figure 5) may be formed by a first contact FD2L formed on one side of the first photodiode LPD and a second contact FD2S formed on one side of the second photodiode SPD. The first contact FD2L and the second contact FD2S may be connected by a metal wiring connection.

[0079] The second region REG2 includes a second photodiode SPD, a second transfer transistor TR7 connected to the second photodiode SPD, a second contact FD2S connected to one end of the connection transistor TR6, and a third diffusion node FD3 corresponding to a third floating diffusion node connected to the other end of the connection transistor TR6. The fourth node FD4 is connected to the third node FD3 through a metal capacitor C. According to an embodiment, a third contact corresponding to the fourth node FD4 may be provided outside the second region REG2.

[0080] In an exemplary case where each of the first regions REG1 has a hexagonal planar shape and each of the second regions REG2 has a square planar shape, a unit pixel UP including one first region REG1 and one second region REG2 may be as follows: Figure 7 Each first region REG1 and each second region REG2 may be separated by a deep trench insulation portion PDI. For example, the deep trench insulation portion PDI may be filled with an insulating material.

[0081] As previously referred Figure 6 As mentioned, the first contact FD2L and the fourth node FD4 may be disposed in the first region REG1. The first contact FD2L may be disposed adjacent to the second region REG2 belonging to the same unit pixel UP as the first region REG1. For example, the first contact FD2L may be disposed adjacent to the second region REG2 belonging to the same unit pixel UP as the first region REG1. The first contact FD2L is electrically connected to the second contact FD2S through a metal wiring connection, thereby defining a single second node FD2. According to an embodiment, since the first contact FD2L and the second contact FD2S define a single second node FD2, the first contact may be referred to as a (1-1)th contact and the second contact may be referred to as a (1-2)th contact. According to an embodiment, the metal wiring connection may be a metal trace disposed in a wiring layer of the image sensor. For example, the metal trace may provide a connection between the first contact FD2L and the second contact FD2S. For example, the metal trace may electrically connect the first contact FD2L and the second contact FD2S. For example, the metal trace may physically contact both the first contact FD2L and the second contact FD2S.

[0082] In addition, as previously mentioned Figure 6As mentioned, the second transfer transistor TR7, the (1-2)th contact FD2S, the third diffusion node FD3, and the connection transistor TR6 are disposed in the second region REG2. The third diffusion node FD3 in the second region REG2 is connected to the fourth diffusion node FD4 through the metal capacitor C, and in the exemplary case where the second transfer transistor TR7 is turned off and the charge is accumulated in the second photodiode SPD, the charge accumulated in the metal capacitor C is discharged to the first power line VDDA during the EIT period.

[0083] Figure 8 is a circuit diagram of a unit pixel according to an embodiment, Fig. 9 It is shown Figure 8 A diagram of the layout of a unit pixel, and Fig.10 yes Fig. 9 Layout diagram of unit pixels.

[0084] In one embodiment, the first photodiode LPD and the second photodiode SPD of the unit pixel UP may be connected to the third node FD3. Therefore, the third node FD3 may be implemented with two contacts, ie, the (2-1)th contact FD3L and the (2-2)th contact FD3S.

[0085] Reference Figure 8 and Fig. 9 , a first photodiode LPD, a first transfer transistor TR1, a source follower transistor TR2, a selection transistor TR3, a reset transistor TR5, a photodiode switch transistor TR4, a connection transistor TR6, a capacitor connection transistor TR8, a power supply connection transistor TR9, a first node FD1, a second node FD2 and a fourth node FD4 are set in the first region ( Figure 2 The second photodiode SPD, the second transfer transistor TR7, the metal capacitor C and the third node FD3 are set Figure 2 A boundary between the first region REG1 and the second region REG2 may be defined by FDTI. Figure 8 The pixel circuit of the unit pixel UP is as follows Figure 3 , therefore, its redundant description will be omitted.

[0086] Reference Fig. 9 , the third node FD3 (see Figure 8 ) may be formed of a (2-1)th contact FD3L formed on one side of the first photodiode LPD and a (2-2)th contact FD3S formed on one side of the second photodiode SPD, and may be connected by a metal wiring connection.

[0087] A connection transistor TR6, a second node FD2 connected to one end of the connection transistor TR6, and a (2-1)th contact FD3L connected to the other end of the connection transistor TR6 are provided in the first region REG1. The (2-1)th contact FD3L is electrically connected to the (2-2)th contact FD3S through a metal wiring connection, thereby defining a single third node FD3. According to an embodiment, since the third contact FD3L and the fourth contact FD3S define a single third node FD3, the third contact may be referred to as a (2-1)th contact and the fourth contact may be referred to as a (2-2)th contact.

[0088] The second photodiode SPD, the second transfer transistor TR7 connected to the second photodiode SPD, and the (2-2)th contact FD3S corresponding to the third floating diffusion node are disposed in the second region REG2. The fourth node FD4 is connected to the (2-2)th contact FD3S through the metal capacitor C, but the third contact corresponding to the fourth node FD4 may be disposed outside the second region REG2.

[0089] In one embodiment, if the first region REG1 has a hexagonal planar shape and the second region REG2 has a square planar shape, the unit pixels UP each including one first region REG1 and one second region REG2 may be as follows: Fig.10 Each first region REG1 and each second region REG2 may be separated by a deep trench insulation PDI filled with an insulating material.

[0090] As previously referred Fig. 9 As mentioned, the connection transistor TR6, the capacitor connection transistor TR8, the (2-1)th contact FD3L, and the fourth diffusion node FD4 may be disposed in the first region REG1. The (2-1)th contact FD3L may be disposed near the second region REG2 of the unit pixel UP that is the same as the first region REG1. The (2-1)th contact FD3L may be disposed between the photodiode connection transistor TR6 and the capacitor connection transistor TR8.

[0091] In addition, as previously mentioned Fig. 9As mentioned, the second region REG2 includes a second transfer transistor TR7 and a (2-2)th contact FD3S. The (2-2)th contact FD3S in the second region REG2 is connected to the fourth diffusion node FD4 through the metal capacitor C, so that in the example case where the second transfer transistor TR7 is turned off and the charge is accumulated in the second photodiode SPD, the charge accumulated in the metal capacitor is discharged to the first power line VDDA during the EIT. Since the photodiode connection transistor TR6 is provided in the first region REG1 rather than in the second region REG2, a layout and routing (PnR) advantage can be provided in terms of the design area for the second region REG2. For example, the second transfer transistor TR7 can be implemented as a double transistor.

[0092] Fig.11 is a schematic diagram of a vehicle including an image sensor according to a disclosed embodiment.

[0093] Reference Fig.11 , the vehicle 300 may include a plurality of electronic control units (ECUs) 310 and a storage device (or storage apparatus) 320 .

[0094] Each of the ECUs 310 may be electrically, mechanically, or communicatively connected to at least one of a plurality of devices provided in the vehicle 300 , and may control the operation of the connected at least one device based on a function execution command.

[0095] Here, the plurality of devices may include an image sensor 330 that acquires an image for performing at least one function and a driving circuit (or driving unit) 340 that performs the at least one function.

[0096] The image sensor according to the aforementioned embodiment may be applicable to the image sensor 330. The image sensor 330 may correspond to an automotive image sensor. Since the image sensor 330 has no leakage current from a switching transistor for a metal capacitor, the image sensor 330 may operate more strongly against DSNU and may provide an improved SNR.

[0097] The drive circuit 340 may include a fan and compressor of an air conditioning system, a fan of a ventilation system, an engine and a motor of a power system, a motor of a steering system, a motor and a valve of a brake system, and an opening device and a closing device for a door or a trunk door.

[0098] The ECU 310 may communicate with the image sensor 330 and the driving circuit 340 using at least one of Ethernet communication, low voltage differential signaling (LVDS) communication, and local interconnect network (LIN) communication.

[0099] ECU 310 may determine the necessity of executing a specific function based on the information acquired through image sensor 330. In the example case where it is determined that the specific function needs to be executed, ECU 310 may perform the operation of drive circuit 340 that executes the specific function, thereby controlling the operation amount of drive circuit 340 based on the acquired information. Here, ECU 310 may store the acquired information in storage device 320, or read and use the information stored in storage device 320.

[0100] In addition, ECU 310 may control the operation of drive circuit 340 to perform a specific function based on a function execution command input through input circuit 350. ECU 310 may also control the operation of drive circuit 340 to perform a specific function based on a set amount corresponding to information input through input circuit 350.

[0101] Each of the ECUs 310 may control a function independently or in coordination with other ECUs 310 .

[0102] For example, the ECU 310 of the collision avoidance system may be configured to output a warning sound for a potential collision with an obstacle through a speaker if the distance to the obstacle detected by the distance detection unit is within a reference range.

[0103] For example, the ECU 310 of the autonomous driving control system may receive navigation information, road image information, and obstacle distance information in coordination with the ECU 310 of the vehicle terminal, the image acquisition unit, and the collision avoidance system, and perform autonomous driving by controlling the power system, the braking system, and the steering system using the received information.

[0104] A connection control unit (CCU) 360 may be electrically, mechanically, or communicatively connected to and communicate with each of the ECUs 310 .

[0105] That is, the ECU 360 may directly communicate with the ECU 310 provided in the vehicle, may communicate with an external server, and may communicate with an external device through an interface.

[0106] The CCU 360 may communicate with the ECU 310 , and may communicate with the server 400 using radio frequency (RF) communication using an antenna.

[0107] In addition, the CCU 360 may wirelessly communicate with the server 400. Specifically, the CCU 360 may wirelessly communicate with the server 400 using various wireless communication methods such as Wireless Fidelity (Wi-Fi), Wireless Broadband (WiBro), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Universal Mobile Telecommunications System (UMTS), Time Division Multiple Access (TDMA), Long Term Evolution (LTE), etc.

[0108] The image sensor 330 is a type of optical sensor, and the disclosed technical concept is also applicable to other types of sensors that use semiconductors to detect the amount of incident light, such as fingerprint sensors and distance measurement sensors.

[0109] Although the disclosed embodiments have been described with reference to the accompanying drawings, it should be understood that the invention can be implemented in other specific forms without changing the technical spirit or essential features of the invention. Therefore, the described embodiments are to be considered in all aspects as illustrative rather than restrictive.

Claims

1. An image sensor, comprising: A pixel array, comprising a plurality of unit pixels; as well as a driving circuit configured to drive the plurality of unit pixels, Wherein, each of the plurality of unit pixels comprises: a first region including: a first photodiode; a first transfer transistor connected to the first photodiode; a first floating diffusion node connected to the first transfer transistor; and a first contact connected to a second floating diffusion node, and The second region includes: a second photodiode; a second transfer transistor connected to the second photodiode; a second contact electrically connected to the first contact through a metal wiring connection; and a third contact provided to a third floating diffusion node connected to the second transfer transistor.

2. The image sensor according to claim 1, wherein: The second region further includes: a connection transistor disposed between the second contact and the third contact.

3. The image sensor according to claim 2, wherein: Each of the plurality of unit pixels further includes: a metal capacitor connected between the third contact and the fourth floating diffusion node; and The capacitor connection transistor is connected between the fourth floating diffusion node and the first power supply line.

4. The image sensor according to claim 3, wherein: The drive circuit is configured as: turning on the capacitor connection transistor during the effective integration time of the second photodiode; and The charges accumulated in the metal capacitor are discharged to the first power line according to the reset signal.

5. The image sensor according to any one of claims 1 to 4, wherein: The first area also includes: a photodiode switch transistor including a first terminal connected to the second floating diffusion node, the photodiode switch transistor being configured to be turned on based on a photodiode switch control signal; a reset transistor connected between the second floating diffusion node and the first power supply line, the reset transistor being configured to be turned on based on a reset signal; a source follower transistor including a gate connected to the first floating diffusion node and a first end connected to the first power line; and The selection transistor is connected between the second terminal of the source follower transistor and the output signal line, and is configured to be turned on based on the selection signal.

6. The image sensor according to claim 5, wherein: The first region further includes a fourth contact connected to the fourth floating diffusion node.

7. An image sensor, comprising: A pixel array, comprising a plurality of unit pixels; as well as a driving circuit configured to drive the plurality of unit pixels, Wherein, each of the plurality of unit pixels comprises: a first region including: a first photodiode; a first transfer transistor connected to the first photodiode; a first floating diffusion node connected to the first transfer transistor; a first contact connected to a second floating diffusion node; and a second contact, and The second region includes: a second photodiode; a second transfer transistor connected to the second photodiode; and a third contact connected to a third floating diffusion node together with the second contact.

8. The image sensor according to claim 7, wherein: The first region further includes a connection transistor disposed between the first contact and the second contact.

9. The image sensor according to claim 8, wherein: Each of the plurality of unit pixels further includes: a metal capacitor connected between the third contact and the fourth floating diffusion node, and The capacitor connection transistor is connected between the fourth floating diffusion node and the first power supply line.

10. The image sensor according to claim 9, wherein: The drive circuit is configured as: making the capacitor connection transistor conductive during the effective integration time of the second photodiode, and The charges accumulated in the third floating diffusion node and the metal capacitor are discharged to the first power line according to the reset signal.

11. The image sensor according to any one of claims 8 to 10, wherein: The first area also includes: a photodiode switch transistor including a first terminal connected to the second floating diffusion node, the photodiode switch transistor being configured to be turned on based on a photodiode switch control signal, a reset transistor connected between the second floating diffusion node and the first power supply line, the reset transistor being configured to be turned on based on a reset signal, a source follower transistor including a gate connected to the first floating diffusion node and a first terminal connected to the first power line, and The selection transistor is connected between the second terminal of the source follower transistor and the output signal line, and is configured to be turned on based on the selection signal.

12. The image sensor according to claim 11, wherein: The first region further includes a fourth contact connected to the fourth floating diffusion node.

13. The image sensor according to claim 7, wherein: The second pass transistor is implemented as a dual pass transistor.

14. An image sensing device, comprising: A pixel array, comprising a plurality of unit pixels; as well as a driving circuit configured to drive the plurality of unit pixels, Wherein, each of the plurality of unit pixels comprises: a first transfer transistor connected between the first photodiode and the first floating diffusion node; a photodiode switch transistor connected between the first floating diffusion node and the second floating diffusion node, the photodiode switch transistor being configured to be turned on based on a photodiode switch control signal; a second transfer transistor connected between the second photodiode and the third floating diffusion node; a metal capacitor connected between the third floating diffusion node and the fourth floating diffusion node; and The first connection transistor is connected between the fourth floating diffusion node and the first power supply line, and is configured to be turned on based on the capacitor connection control signal.

15. The image sensing device according to claim 14, wherein: Each of the plurality of unit pixels further includes: a source follower transistor including a gate connected to the first floating diffusion node and a first terminal connected to the first power line; a reset transistor connected between the second floating diffusion node and the first power supply line, the reset transistor being configured to be turned on based on a reset signal; and The selection transistor is configured to be turned on based on the selection signal and output an output signal corresponding to the signal at the second terminal of the source follower transistor to the output signal line.

16. The image sensing device according to claim 15, wherein: The drive circuit is configured as: accumulating charge in a third floating diffusion node by turning on the second connection transistor and turning off the first connection transistor during an effective integration time of the second photodiode; converting the charge accumulated in the third floating diffusion node and the metal capacitor through the source follower transistor by turning on the first connection transistor while keeping the second connection transistor turned on; as well as The converted charge is output to the output signal line.

17. The image sensing device according to claim 16, wherein: The driving circuit is configured to discharge the charges accumulated in the third floating diffusion node and the metal capacitor to the first power supply line by turning on each of the first connection transistor and the reset transistor.

18. The image sensing device according to claim 14, wherein: Each of the plurality of unit pixels further includes: a first region including a first photodiode and a first contact connected to a second floating diffusion node; and The second region includes a second photodiode, a second transfer transistor, a second contact electrically connected to the first contact through a first metal wiring connection, and a third contact connected to a third floating diffusion node.

19. The image sensing device according to claim 18, wherein: The second region further includes: a second connection transistor disposed between the second contact and the third contact.

20. The image sensing device according to claim 14, wherein: Each of the plurality of unit pixels further includes: a first region including a first photodiode, a first floating diffusion node connected to the first transfer transistor, a first contact connected to the second floating diffusion node, and a second contact connected to the third floating diffusion node; and The second region includes a second photodiode, a second transfer transistor connected to the second photodiode, and a third contact electrically connected to the second contact through a second metal wiring connection.

Images