Photon counting image sensor

Abstract

The invention relates to a photon counting image sensor. An image sensor pixel is provided that includes a single photon avalanche diode (SPAD), an analog counter coupled to a cathode terminal of the SPAD, and a comparator, the comparator has a first input coupled to a floating diffusion node in the analog counter, a second input configured to receive a reference voltage, and a clock input configured to receive a comparator clock signal from the analog counter. The image sensor pixel may also include an analog memory circuit selectively coupled to an output of the comparator. The analog memory circuit may include a read enable switch coupled between an output of a comparator and a storage node and a plurality of capacitors coupled to the storage node via respective switches.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 591,389, filed on October 18, 2023, which is hereby incorporated by reference in its entirety. Background Art

[0002] Image sensors are often used in electronic devices such as mobile phones, cameras, computers, automobiles, and other systems to capture images. In a typical arrangement, an image sensor includes an array of image pixels arranged into rows and columns of pixels. Each image pixel may include a photosensitive element coupled to an associated transistor.

[0003] It is against this background that the embodiments described herein arise. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a schematic diagram of an illustrative electronic device with an image sensor according to some embodiments.

[0005] Figure 2 is a schematic diagram of an illustrative pixel array and associated row and column control circuits for reading out image signals from an image sensor, according to some implementations.

[0006] Figure 3 is a block diagram of an illustrative single photon avalanche diode (SPAD) based image pixel, according to some implementations.

[0007] Figure 4 According to some embodiments Figure 3 Circuit diagram of one illustrative implementation of a SPAD-based image pixel of the type shown.

[0008] Figure 5 is a circuit diagram of an illustrative delay locked loop (DLL) circuit configured to generate a control voltage signal, according to some embodiments.

[0009] Figure 6 According to some embodiments, Figure 5 A circuit diagram of an exemplary voltage-controlled pulse generator that controls a control voltage signal generated by a DLL circuit.

[0010] Figure 7 is a timing diagram illustrating the behavior of related signals used to operate in conjunction with Figures 3 to 6 A SPAD-based image pixel of the type shown. DETAILED DESCRIPTION

[0011] Embodiments of the present invention technology relate to image sensors. It should be understood by those skilled in the art that exemplary embodiments of the present invention can be practiced without some or all of these specific details. In other cases, in order to avoid unnecessarily obscuring the embodiments of the present invention, well-known operations are not described in detail.

[0012] Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices may include an image sensor that collects incoming light to capture an image. The image sensor may include an array of pixels. The pixels in the image sensor may include a photosensitive element, such as a single photon avalanche diode (SPAD), which converts an impinging photon into an electron or a hole. Image sensor pixels including SPADs may be referred to herein as SPAD-based imaging pixels. Image sensors including SPAD-based imaging pixels may be referred to as SPAD-based image sensors. SPAD-based image sensors may have any number (e.g., hundreds, thousands, or millions) of pixels. The image sensor may include control circuits (such as circuits for operating pixels) and readout circuits for reading out image signals corresponding to the charge generated by the photosensitive element.

[0013] Figure 1 is a diagram of an exemplary imaging and response system including an imaging system that captures an image using an image sensor. Figure 1 The system 8 may be an electronic device such as a camera, a cellular phone, a video camera, or other electronic device that captures digital image data, may be a vehicle safety system (e.g., an active braking system or other vehicle safety system), or may be a surveillance system. Figure 1 As shown, system 8 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). Imaging system 10 may include camera module 12. Camera module 12 may include one or more image sensors 14 and one or more lenses, such as in an image sensor array integrated circuit. Image sensor 14 may be a SPAD-based image sensor. During an image capture operation, each lens may focus light onto an associated SPAD-based image sensor 14. Image sensor 14 may include a photosensitive element (i.e., a SPAD-based image sensor pixel) that converts light into corresponding data. The image sensor may have any number (e.g., hundreds, thousands, millions, or more) of pixels. A typical image sensor may, for example, have millions of pixels (e.g., several megapixels).

[0014] Each image sensor in camera module 12 may be identical, or different types of image sensors may be present in a given image sensor array integrated circuit. In some examples, image sensor 14 may also include bias circuitry (e.g., source follower load circuitry), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory (e.g., buffer circuitry), and / or addressing circuitry.

[0015] Still and video image data from image sensor 14 may be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 may be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization or face detection. Image processing and data formatting circuitry 16 may additionally or alternatively be used to compress raw camera image files (e.g., to Joint Photographic Experts Group or JPEG format) if desired.

[0016] In one exemplary arrangement, such as a system-on-chip (SoC) arrangement, the sensor 14 and the image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, the sensor 14 and the image processing circuitry 16 may be formed on separate semiconductor substrates. For example, the sensor 14 and the image processing circuitry 16 may be formed on separate substrates that have been stacked.

[0017] The imaging system 10 may transmit the acquired image data to a host subsystem 20 via a path 18. The host subsystem 20 may include input-output devices 22 and storage and processing circuitry 24. The host subsystem 20 may include processing software for detecting objects in an image, detecting motion of an object between image frames, determining distances to objects in an image, or filtering or otherwise processing images provided by the imaging system 10. For example, the image processing and data formatting circuitry 16 of the imaging system 10 may transmit the acquired image data to the storage and processing circuitry 24 of the host subsystem 20.

[0018] If desired, the system 8 can provide the user with many advanced functions. For example, in a computer or mobile phone, the user can be provided with the ability to run user applications. For these functions, the input-output device 22 of the host subsystem 20 can include a keyboard, input-output ports, buttons, and a display, as well as a storage and processing circuit 24. The storage and processing circuit 24 of the host subsystem 20 can include volatile memory and / or non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid state drive, etc.). The storage and processing circuit 24 can additionally or alternatively include a microprocessor, a microcontroller, a digital signal processor, and / or an application-specific integrated circuit.

[0019] Figure 2 It is shown in Figure 1 An example of an arrangement of a SPAD-based image sensor 14 is shown. Figure 2 As shown, image sensor 14 may include control and processing circuitry 44. Control and processing circuitry 44 (sometimes referred to as control and processing logic) may be Figure 1 1 and 2. The image sensor 14 may be a part of the image processing and data formatting circuitry 16 in the image sensor 14, or may be separate from the circuitry 16. The image sensor 14 may include an array of pixels, such as an array 32 of SPAD-based pixels 34 (sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels). The control and processing circuitry 44 may be coupled to the row control circuitry 40 via the control path 27, and may be coupled to the column control and readout circuitry 42 via the data path 26.

[0020] Row control circuitry 40 may receive row addresses from control and processing circuitry 44 and may provide corresponding row control signals to image pixels 34 via one or more control paths 36. The row control signals may include pixel reset control signals, charge transfer control signals, overflow control signals, row select control signals, dual conversion gain control signals, or any other desired pixel control signals.

[0021] Column control and readout circuitry 42 may be coupled to one or more columns of pixel array 32 via one or more conductors, such as column lines 38. A given column line 38 may be coupled to a column of image pixels 34 in image pixel array 32 and may be used to read out image signals from image pixels 34 and to provide bias signals (e.g., bias currents or bias voltages) to image pixels 34. In some examples, each column of pixels may be coupled to a corresponding column line 38. For image pixel readout operations, a row of pixels in image pixel array 32 may be selected using row driver circuitry 40, and image data associated with image pixels 34 of that pixel row may be read out on column lines 38 by column readout circuitry 42. Column readout circuitry 42 may include column circuitry, such as a column amplifier for amplifying a signal read out from array 32, a sample and hold circuit for sampling and storing a signal read out from array 32, an analog-to-digital converter circuit for converting a readout analog signal into a corresponding digital signal, or a column memory for storing the readout signal and any other desired data. Column control and readout circuitry 42 may output digital pixel readout values ​​via line 26 to control and processing logic 44 .

[0022] Array 32 may have any number of rows and columns. In general, the size of array 32 and the number of rows and columns in array 32 will depend on the specific implementation of image sensor 14. Although rows and columns are generally described herein as horizontal and vertical, respectively, rows and columns may refer to any grid-like structure. Features described herein as rows may be arranged vertically, and features described herein as columns may be arranged horizontally.

[0023] Pixel array 32 may optionally be provided with a color filter array having a plurality of color filter elements that allow a single image sensor to sample different colors of light. For example, an image sensor pixel, such as an image pixel in array 32, may be provided with a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels. The red, green, and blue image sensor pixels may be arranged in a Bayer mosaic pattern. The Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are diagonally opposite to each other and adjacent to a red image pixel diagonally opposite to a blue image pixel. In another example, a broadband image pixel having a broadband color filter element (e.g., a transparent color filter element) may be used in place of a green pixel in a Bayer pattern. These examples are merely illustrative, and in general, color filter elements of any desired color (e.g., cyan, yellow, red, green, blue, etc.) and any desired pattern may be formed on any desired number of image pixels 34.

[0024] Figure 3 is a block diagram of a SPAD-based image pixel, such as image pixel 34. A SPAD-based image sensor may be configured to count the number of impinging photons. This type of photon counting image sensor may provide an improved low light signal-to-noise ratio (SNR) while maintaining a high dynamic range. According to an embodiment, an image sensor is provided that includes an array of SPAD-based image pixels, the design of which is technically advantageous due to minimal area overhead and reduced power consumption compared to other prior art SPAD-based image sensors. Figure 3 As shown, image pixel 34 may include a single photon avalanche diode (such as SPAD 100), an associated quenching circuit (such as quenching circuit 102), a readout circuit (such as readout circuit 104), an analog counting circuit (such as analog counter 106), a comparison circuit (such as comparator 108), an analog storage circuit (such as analog memory 110), and optionally other circuit components. In contrast, conventional SPAD-based image pixels may include digital counters, which occupy considerable circuit area and therefore increase cost.

[0025] The SPAD 100 (sometimes referred to as a photodiode) can be biased above its breakdown point, and when incident photons from a light source generate electrons or holes, the carriers initiate an avalanche breakdown while generating additional carriers. Avalanche multiplication can produce a current signal that can be easily detected by a readout circuit 104 associated with the SPAD 100. It is desirable to stop (i.e., quench) the avalanche process by reducing the diode bias below its breakdown point. For example, a control circuit (such as Figure 2 Circuitry 40 and / or 44 in FIG. 1 may operate a quenching circuit 102 or other adjustable (transistor) circuit within each SPAD pixel to control one or more bias voltages provided to each SPAD pixel.

[0026] Figure 4 It is shown Figure 3 A circuit diagram of an exemplary implementation of a SPAD-based image pixel 34 of the type shown. Figure 4 As shown, the image pixel 34 may include: a photodiode or SPAD 100 having an anode (A) terminal coupled to a voltage line 199 (e.g., a voltage line on which an anode bias voltage Vanode may be provided); a quenching circuit 102 coupled to a cathode (C) terminal of the SPAD 100; an analog counter 106 coupled to the cathode terminal of the SPAD 100; a comparator 230 having an input coupled to a floating diffusion node FD as part of the analog counter 106; an analog memory circuit 110 coupled to an output of the comparator 230; and associated readout circuitry. As an example, Vanode may be different from a ground voltage and / or may be a negative voltage. In response to receiving a single photon 99, the SPAD 100 may generate carriers that cause a detectable change in a voltage Vspad at the cathode terminal. The voltage Vspad is sometimes referred to herein as the cathode terminal voltage. Generally speaking, an impinging photon may result in a corresponding detectable falling or rising edge of the cathode voltage Vspad.

[0027] The quenching circuit 102 may include a quenching transistor 204, a cascode transistor 206, and an associated quenching logic circuit 208. The quenching transistor 204 may be a p-type transistor, such as a p-channel metal oxide semiconductor (PMOS) transistor, having a source terminal coupled to the first positive supply line 202-1, a gate terminal coupled to the quenching logic 208, and a source terminal coupled to the cascode transistor 206. A positive supply voltage may be provided on the supply line 202-1. When referring to the conductive terminals of the metal oxide semiconductor transistor, the terms "source" and "drain" are sometimes used interchangeably. The source terminal and the drain terminal are therefore sometimes referred to as "source-drain" terminals. For example, the transistor 204 has at least a first source-drain terminal and a second source-drain terminal.

[0028] The term "activation" with respect to a switch (or transistor) may refer or be defined herein as the action of placing the switch in an "on" or low impedance state so that the two terminals of the switch are electrically connected to conduct current. Activating a switch may sometimes be referred to as turning the switch on or closing it. The term "deactivation" with respect to a switch (or transistor) may refer or be defined herein as the action of placing the switch in an "off" or high impedance state so that the two terminals of the switch / transistor are electrically disconnected with minimal leakage current. Deactivating a switch may sometimes be referred to as turning off or opening the switch.

[0029] The cascode transistor 206 may be a p-type (PMOS) transistor having a source terminal coupled to the quenching transistor 204, a drain terminal coupled to the cathode terminal of the SPAD 100, and a gate terminal configured to receive a cascode bias voltage Vbias_cas. The bias voltage Vbias_cas may be generated by an associated bias voltage generating circuit. The cascode transistor 206 is optional and may be omitted from the pixel 34. If the cascode transistor 206 is omitted from the pixel 34, the drain terminal of the quenching transistor 204 will be directly coupled to the cathode terminal of the SPAD 100. The quenching logic 208 may have an input terminal configured to receive a count completion signal (Count_done) output from the analog memory circuit 110 and a clock signal CLK, and may output a corresponding voltage for controlling the gate terminal of the quenching transistor 204. In other words, quenching logic 208 may generate a control signal for selectively activating quenching transistor 204 based on signal Count_done and clock signal CLK. Quenching logic circuit 208 may include one or more logic gates formed by a plurality of n-type and / or p-type transistors.

[0030] The analog counter 106 may include a logic gate such as a logic NAND gate 209, a pulse generator such as a voltage controlled pulse generator (VCPG) 210, a charge pump circuit such as a charge pump 212, a clock logic such as a comparator clock logic circuit 216, a capacitor such as an integrating capacitor Cint, and a precharge switch such as a precharge transistor 214. The logic NAND gate 209 may have a first input terminal coupled to the cathode terminal of the SPAD 100, a second input terminal configured to receive a clock signal CLK, and an output terminal generating a voltage Vvcpg. The voltage controlled pulse generator 210 may receive the voltage Vvcpg from the output of the logic gate 209 and the control voltage Vctrl, and may output a corresponding pulse signal 211. The pulse signal 211 may have a pulse width PW. The pulse 211 may be generated by the voltage controlled pulse generator 210 in response to the analog counter 106 detecting an edge such as a falling edge 213 of Vspad. Such a falling edge 213 will trigger the pulse generator 210 to output a corresponding pulse 211. The comparator clock logic 216 may receive the pulse signal 211 and generate a corresponding comparator clock signal CLK_comp for controlling the comparator 230. The logic circuit 216 may include one or more logic gates formed by a plurality of n-type and / or p-type transistors. The comparator 230 controlled by the comparator clock signal CLK_comp is sometimes referred to as a clock comparator. Configured in this manner, the comparator 230 may compare Vint with Vref and output a corresponding comparison result in response to detecting an edge (rising edge or falling edge) of the signal CLK_comp.

[0031] The charge pump 212 may receive the pulse signal 211 and discharge the integrated voltage Vint stored on the floating diffusion node FD. The charge pump 212 may have an output terminal coupled to the node FD. The integrating capacitor Cint has a first terminal coupled to the node FD and a second terminal coupled to the ground power supply line 200 (e.g., a power supply line on which a ground voltage is provided). Configured in this manner, the integrated voltage Vint is stored on the integrating capacitor Cint. The precharge transistor 214 may be a p-type (PMOS) transistor having a drain terminal coupled to the floating diffusion node FD, a source terminal coupled to the second positive power supply line 202-2, and a gate terminal configured to receive a precharge control signal PreC. The precharge transistor 214 is sometimes referred to as a reset transistor configured to selectively reset the floating diffusion node (region) FD. A positive supply voltage may be provided on the power supply line 202-2. The supply voltage on the line 202-2 may be the same as or different from the supply voltage on the line 202-1.

[0032] A source follower transistor (such as an n-type metal oxide semiconductor (NMOS) source follower (SF) transistor 220) may have a drain terminal coupled to a third positive supply line 202-3, a gate terminal coupled to a floating diffusion node FD, and a source terminal coupled to a row select transistor 222. A positive supply voltage may be provided on supply line 202-3. The supply voltage on line 202-3 may be the same as or different from the supply voltage on line 202-1 or 202-2. Row select transistor 222 may have a drain terminal coupled to source follower transistor 220, a gate terminal configured to receive a row select control signal RS, and a source terminal coupled to a pixel output column line 224. The control signal RS may be provided by row control circuit 40 ( Figure 2 ) is selectively asserted for reading out the pixel output voltage Pixout based on the current voltage level of the floating diffusion node FD. The pixel output column line 224 can be coupled to other pixels 34 arranged along the same column in the image pixel array. The source follower transistor 220 and the row select transistor 222 can be considered as Figure 3 Part of the readout circuit 104.

[0033] Comparator 230 (sometimes referred to as a voltage comparator) may have a first input terminal coupled to floating diffusion node FD, a second input terminal configured to receive reference voltage Vref, a clock input terminal configured to receive clock signal CLK_comp output from comparator clock logic 216 of analog counter 106, and an output terminal coupled to analog memory circuit 110. Arranged in this manner, comparator 230 may be considered to be coupled or inserted between analog counter 106 and analog memory circuit 110. This example of comparator 230 being a clock comparator is illustrative. In other embodiments, comparator 230 may be a non-clocked comparator (e.g., a comparator without a clock input).

[0034] The analog memory circuit 110 may have a read enable transistor 240, a plurality of analog memory capacitors (such as Cmem1, Cmem2, and Cmem3), a plurality of associated capacitor switches, and a logic gate (such as a logic NOR gate 244). The read enable transistor 240 (or switch) may be an n-type (NMOS) transistor having a first source-drain terminal coupled to the output of the comparator 230, a second source-drain terminal coupled to the analog storage node 248, and a gate terminal configured to receive an inverted read enable control signal Read_enb. The first analog memory capacitor Cmem1 may be coupled in series with a first capacitor switch controlled by a signal T1 between the storage node 248 and a voltage line 201 (e.g., a voltage line on which a memory bias voltage Vmem may be provided). The second analog memory capacitor Cmem2 may be coupled in series with a second capacitor switch controlled by a signal T2 between the storage node 248 and the voltage line 201. The third analog memory capacitor Cmem3 may be coupled in series with a third capacitor switch controlled by a signal T3 between a storage node 248 and a voltage line 201. A logic NOR gate 244 may have a first input coupled to a node disposed between Cmem1 and the first capacitor switch, a second input coupled to a node disposed between Cmem2 and the second capacitor switch, a third input coupled to a node disposed between Cmem3 and the third capacitor switch, and an output at which a count completion signal Count_done is generated. The signal Count_done may be transmitted to an input of the quenching logic 208 via a path 246.

[0035] Figure 4The example of is illustrative, where the analog memory 110 includes three capacitors Cmem. In general, the analog memory 110 may include one or more capacitors Cmem and associated switches, four or more capacitors Cmem and associated switches, four to eight capacitors Cmem and associated switches, 8 to 16 capacitors Cmem and associated switches, or more than 16 capacitors Cmem and associated switches. The memory capacitor Cmem may be significantly smaller than the integration capacitor Cint. For example, the integration capacitor Cint may be at least five times larger than one or more Cmem, at least 10 times larger than one or more Cmem, 10 to 50 times larger than one or more Cmem, 50 to 100 times larger than one or more Cmem, 100 to 1000 times larger than one or more Cmem, or more than 1000 times larger than one or more Cmem. The various analog memory capacitors Cmem1, Cmem2, and Cmem3 may have the same size or may have different sizes. Configured in this manner, any signal read from the larger integrating capacitor Cint can typically represent one or more least significant bits (LSBs) of the final read signal, while any signal read from the smaller analog memory capacitor can typically represent one or more most significant bits (MSBs) of the final read signal.

[0036] An additional source follower transistor, such as an n-type metal oxide semiconductor (NMOS) source follower (SF) transistor 250, may have a drain terminal coupled to a fourth positive supply line 202-4, a gate terminal coupled to storage node 248, and a source terminal coupled to an additional row select transistor 252. A positive supply voltage may be provided on supply line 202-4. The supply voltage on line 202-4 may be the same as or different from the supply voltage on lines 202-1, 202-2, or 202-3. Row select transistor 252 may have a drain terminal coupled to source follower transistor 250, a gate terminal configured to receive an additional row select control signal RS', and a source terminal coupled to memory readout line 254. Control signal RS' may be provided by row control circuit 40 ( Figure 2 ) is selectively asserted for reading out the memory output voltage Memout based on the current voltage level at the storage node 248. The source follower transistor 250 and the row select transistor 252 may also be viewed as Figure 3 Part of the readout circuit 104.

[0037] The control voltage Vctrl for tuning the voltage-controlled pulse generator 210 may be provided by a control voltage generator (such as Figure 5 The control voltage generator 300 shown in FIG. Figure 5As shown, the control voltage generator 300 may include a phase-locked loop (PLL) 302 coupled to a delay-locked loop (DLL) 304. The PLL 302 may have an input configured to receive a reference clock signal CLK_ref and an output coupled to the DLL 304. The delay-locked loop 304 may include a series of N inverting circuits, such as inverters 306-1, 306-2, ..., 306-N, sometimes referred to as an inverter chain. In general, N may represent an integer greater than five, greater than ten, 10-20, 20-50, 50-100, or more than 100.

[0038] The output of the last inverter 306-N may be coupled to an input of a charge pump and phase detector circuit 308. The charge pump and phase detector circuit 308 may have another input that is coupled to an input of the first inverter 306-1 via a path 309. The charge pump and phase detector 308 may output a control voltage Vctrl for tuning the delay of the N series-connected inverters. N series-connected inverters configured in this manner are sometimes referred to as a voltage-controlled delay line 310. Each inverter 306 having a drive strength modulated by Vctrl is sometimes referred to as a current-starved inverter. The control voltage generator 300 may be disposed along a peripheral edge of the image pixel array, where the control voltage Vctrl is transmitted to each SPAD-based pixel 34 via a control line 312.

[0039] Figure 6 is a circuit diagram of an exemplary voltage-controlled pulse generator 210 disposed within each SPAD-based image pixel 34. Figure 6 As shown, the voltage-controlled pulse generator 210 may include an input inverter 320 and a series of M inverting circuits, such as inverters 326-1, 326-2, ..., and 326-M, sometimes referred to as a hungry inverter chain. Inverter 320 has an output terminal coupled to the input terminal of the first inverter 326-1. In general, M may represent an odd integer less than N, less than ten, less than 20, less than five, less than three, or other suitable odd integer values. M inverters connected in series configured in this manner are sometimes referred to as a voltage-controlled delay line 330.

[0040] Each inverter 326 in delay line 330 may be a copy or replica of inverter 306 in delay line 310. In other words, inverters 306 and 326 may exhibit the same drive strength and transistor size. If desired, delay line 310 and / or delay line 330 may optionally include an always-active logic AND gate coupled in series with the inverter for improved matching. Each inverter 326 may have a drive strength modulated by Vctrl provided via signal line 312. Voltage-controlled pulse generator 210 may also include a logic gate (such as logic AND gate 322) having a first input coupled to the output of the last inverter 326-M, a second input coupled to the input of the first inverter 326-1 in delay line 330 via connection 324, and an output at which pulse signal 211 may be generated (see also Figure 4 ). Configured in this manner, the pulse signal 211 can exhibit a pulse width that is locked with minimal sensitivity to process, voltage, and temperature (PVT) variations.

[0041] Combination Figure 7 The timing diagram is best understood in conjunction with Figures 1 to 6 Operation of a SPAD-based image pixel 34 of the type described. Figure 7 The behavior of the relevant signals within image pixel 34 during the integration time from time t0 to time t4 is shown. The duration of the integration time is indicated by time period T. Prior to time t0, voltage Vspad may be low, signal Read_enb may be low, and signal PreC may be low, which activates transistor 214 and drives voltage Vint at the floating diffusion node to a high voltage level. Pixel 34 may have an initial photon count of "0". The output terminal (Comp_out) of comparator 230 may also have an initial low value.

[0042] At the beginning of the integration time at t0, the signal Read_enb and the precharge signal PreC may be driven high. Driving the signal PreC high turns off the transistor 214, which allows the voltage Vint to change. Driving the signal Read_enb high activates the transistor 240, so that the output of the comparator 230 is coupled to the analog memory circuit 110. After this point, the clock signals controlling the analog counter 106 and the quenching logic 208 may begin to switch. Figure 7 An inverted version of the clock signal CLKb is shown. The clock signal may be configured to pulse Nc times during an integration period. Nc may be an integer representing the total counter capacity of the pixel 34.

[0043] During the integration period, multiple photons may strike the SPAD 100. Each time a photon strikes the SPAD 100, a corresponding falling edge of the voltage Vspad is caused. This can be detected by the analog counter 106 by generating a corresponding pulse of the voltage Vvcpg at the input of the voltage-controlled pulse generator 210. This causes the pulse generator 210 to output a pulse signal that causes the charge pump 212 to pull down the voltage Vint by a determined voltage step size. Each time Vint decreases by a certain voltage step size, the effective photon count of the pixel 34 is incremented by one.

[0044] According to an embodiment, pixel 34 is configured to capture the state of comparator 230 at a plurality of different time stamps. Figure 7 As shown in the example of , the pixel 34 can be configured to capture the state of the comparator 230 at time t1, time t2, and time t3. Time t1 occurs at T / m^3 after time t0. Time t2 occurs at T / m^2 after time t0. Time t3 occurs at T / m after time t0. The integer m may refer to and is defined as a counter scale ratio in this article. The counter scale ratio m may be equal to 2, 3, 4, 5, 6, 7, 8, 9, 10 or other integer values. In an example where m is equal to 2, times t1, t2, and t3 may occur at T / 8, T / 4, and T / 2, respectively. In another example where m is equal to 8, times t1, t2, and t3 may occur at T / 512, T / 64, and T / 8, respectively. Operating in this manner, the comparator sampling times at t1, t2, and t3 are unevenly spaced during the integration period. For example, the time period from t0 to t1 may have a first value, the time period from t1 to t2 may have a second value equal to or greater than the first value, and the time period from t2 to t3 may have a third value greater than the second value. Arranged in this manner, signal CLKb may be pulse modulated Nc / m^3 times from time t0 to t1, may be pulse modulated Nc / m^2 times from time t0 to t2, and may be pulse modulated Nc / m times from time t0 to t3.

[0045] At time t1, the pulse of signal T1 is high to temporarily activate the first capacitor switch coupled in series with capacitor Cmem1. At this time, the comparator 230 can compare the current Vint value with Vref. The reference voltage Vref may have a voltage level set to be equal to a desired voltage level below the saturation level (for example, equal to the voltage step per count described in conjunction with Vint multiplied by Nsat and divided by the counter scale ratio m). Nsat can be an integer representing the full range or depth of the analog counter. In some embodiments, Nsat can be set to be equal to any value less than Nc. Based on the counter value, the pixel 34 can determine at time t1 whether the current count N1 at time t1 is greater than Nref, where Nref represents the effective analog count when Vint is equal to Vref. Figure 7 In the example of , the current analog counter value N1 is still less than Nref, so comparator 230 will output a low voltage which can then be stored on Cmem1, as indicated by the low amem1 value at time t1.

[0046] At time t2, the pulse of signal T2 is high to temporarily activate the second capacitor switch coupled in series with capacitor Cmem2. At this time, comparator 230 can compare the current Vint value with Vref. Figure 7 In the example of , the effective analog count does reach and exceed Nref at some time between t1 and t2. At this time, the comparator output Comp_out can be driven high. Here, the pixel 34 can then determine at time t2 whether the current count N2 at time t2 is greater than Nref. Figure 7 In the example of , the current analog counter value N2 is greater than Nref, so the comparator 230 will now output a high voltage that can then be stored on Cmem2, as indicated by the high amem2 value at time t2. At this point, the logic NOR gate 244 will assert or drive the signal Count_done high, as indicated by arrow 400. The time period from time t0 until Count_done is driven high can be referred to as the effective integration time Teff. After the signal Count_done is driven high, the count value of the analog counter 106 will remain fixed at N2, while Vint remains fixed at its current voltage level.

[0047] At time t3, the pulse of signal T3 is high to temporarily activate the third capacitor switch coupled in series with capacitor Cmem3. At this time, comparator 230 can compare the current Vint value with Vref. As described above, the current analog counter value is fixed at N2, which is greater than Nref, so comparator 230 outputs a high voltage, which can then be stored on Cmem3, as indicated by the high amem3 value at time t3. Logic NOR gate 244 will maintain its assertion of signal Count_done. At time t4, signals Read_enb and PreC can be driven to low. Driving signal Read_enb to low will decouple the analog memory circuit 110 from the output of comparator 230. Driving signal PreC to low will precharge Vint to a high voltage.

[0048] Figure 7The example is illustrative, in which the state of the comparator 230 is checked or sampled at three changing time points during the integration period. As another example, the state of the comparator 230 may be checked only twice (e.g., at time points 1 / m^2 and 1 / m during the integration period T), and the corresponding sampling results may be stored on two corresponding analog memory capacitors. As another example, the state of the comparator 230 may be checked four times (e.g., at various time points 1 / m^4, 1 / m^3, 1 / m^2, and 1 / m throughout the integration period T), and the corresponding results may be stored on four corresponding analog memory capacitors. In general, the state of the comparator 230 may be checked two or more times, and the corresponding results may be stored on two or more analog memory capacitors. Operating SPAD-based image pixels in this manner may be technically advantageous and beneficial to provide high-precision photon counting capabilities with excellent low light sensitivity and high dynamic range, which may be applicable to night vision imaging and a variety of imaging applications.

[0049] Figure 7 The timing of the described operations is exemplary. In some embodiments, one or more of the described operations may be modified, replaced, or omitted. In some embodiments, one or more of the described operations may be performed in parallel. In some embodiments, additional processing may be added or inserted between the described operations. If desired, the order of certain operations may be reversed or changed, and / or the timing of the described operations may be adjusted so that they occur at slightly different times. In some embodiments, the described operations may be distributed in a larger system.

[0050] The above contents are merely exemplary, and various modifications may be made to the described embodiments. The above embodiments may be implemented individually or in any combination.

Claims

1. An image sensor pixel, the image sensor pixel comprising: Single photon avalanche diode SPAD; an analog counter coupled to a cathode terminal of the SPAD; and A comparator has a first input coupled to a floating diffusion node in the analog counter, a second input configured to receive a reference voltage, and a clock input configured to receive a comparator clock signal from the analog counter.

2. The image sensor pixel of claim 1 , further comprising: An analog memory circuit is selectively coupled to the output terminal of the comparator.

3. The image sensor pixel of claim 2 , wherein the analog memory circuit comprises: a read enable switch coupled between the output of the comparator and a storage node; and A plurality of capacitors are coupled to the storage node via corresponding switches.

4. The image sensor pixel of claim 3 , further comprising: a quenching transistor coupled to the cathode terminal of the SPAD; and A quenching logic circuit is configured to output a voltage to a gate terminal of the quenching transistor, wherein the analog memory circuit further comprises a logic gate having an input coupled to the plurality of capacitors and having an output coupled to the quenching logic circuit.

5. The image sensor pixel of claim 4, wherein the logic gate comprises a logical NOR gate.

6. The image sensor pixel of claim 1 , wherein the analog counter comprises: a voltage-controlled pulse generator having an input coupled to the cathode terminal of the SPAD; a charge pump having an input coupled to the voltage-controlled pulse generator and having an output coupled to the floating diffusion node; and An integrating capacitor is coupled between the floating diffusion node and a power supply line.

7. The image sensor pixel of claim 6, wherein the analog counter further comprises: a logic gate having a first input coupled to the cathode terminal of the SPAD, a second input configured to receive a clock signal, and an output coupled to the input of the voltage-controlled pulse generator; and A clock logic circuit has an input coupled to the input of the charge pump and is configured to generate the comparator clock signal.

8. The image sensor pixel of claim 6, wherein: The voltage-controlled pulse generator is configured to receive a control voltage generated from a delay-locked loop (DLL) circuit; The DLL circuit includes a first number of inverter circuits; and The voltage-controlled pulse generator includes a second number of inverter circuits that is smaller than the first number, the second number of inverter circuits being replicas of the inverter circuits of the DLL circuit.

9. The image sensor pixel of claim 6, wherein the analog counter further comprises: A precharge transistor has a first source-drain terminal coupled to the floating diffusion node, a second source-drain terminal coupled to an additional supply line different from the supply line, and a gate terminal configured to receive a precharge control signal.

10. The image sensor pixel of claim 1 , further comprising: an analog memory circuit selectively coupled to an output of the comparator; a first source follower transistor having a gate terminal coupled to the floating diffusion node; a first row select transistor coupled between the first source follower transistor and a pixel output line; a second source follower transistor having a gate terminal coupled to a storage node in the analog memory circuit; and A second row select transistor is coupled between the second source follower transistor and a memory output line.

11. A method of operating an image sensor pixel, the method comprising: Detect photons using single photon avalanche diodes (SPADs); adjusting an integrated voltage at an integrating capacitor in steps using an analog counter and pulsing a comparator clock signal in response to detecting the photon; as well as The comparator is utilized to receive the comparator clock signal from the analog counter and to compare the integrated voltage to a reference voltage in response to detecting an edge in the comparator clock signal.

12. The method according to claim 11, further comprising: The comparison result output from the comparator is selectively sampled using an analog memory circuit having a plurality of memory capacitors.

13. The method of claim 12, wherein the integration capacitor is at least five times larger than each memory capacitor of the plurality of memory capacitors.

14. The method according to claim 12, further comprising: utilizing a read enable transistor in the analog memory circuit to transmit the comparison result output by the comparator to a storage node in the analog memory circuit during an integration period of duration T; selectively activating a first switch coupled between the storage node and a first memory capacitor of the plurality of memory capacitors; as well as A second switch coupled between the storage node and a second memory capacitor of the plurality of memory capacitors is selectively activated.

15. The method according to claim 14, further comprising: A third switch coupled between the storage node and a third memory capacitor of the plurality of memory capacitors is selectively activated.

16. The method of claim 14, wherein: Selectively activating the first switch occurs at T / m from the beginning of the integration period. 2 Afterwards, wherein m is an integer greater than or equal to two; and Selectively activating the second switch occurs after T / m from the beginning of the integration period.

17. An image sensor pixel, the image sensor pixel comprising: Photodiode; an analog counter coupled to a cathode terminal of the photodiode and having an integrating capacitor; a comparator having an input coupled to the analog counter; and An analog memory circuit is coupled to the output of the comparator and has a plurality of memory capacitors that are smaller than the integrating capacitor.

18. The image sensor pixel of claim 17, wherein the photosensitive diode comprises a single photon avalanche diode (SPAD).

19. The image sensor pixel of claim 17, wherein the analog counter comprises: Voltage controlled pulse generator; a logic gate coupled between the cathode terminal of the photodiode and an input terminal of the voltage-controlled pulse generator; a charge pump coupled between an output terminal of the voltage-controlled pulse generator and the integrating capacitor; and A precharge transistor is configured to precharge the integration capacitor.

20. The image sensor pixel of claim 17, wherein the analog memory circuit further comprises: a read enable switch coupled between the output of the comparator and a storage node of the analog memory circuit; a first switch coupled between the storage node and a first memory capacitor of the plurality of memory capacitors; a second switch coupled between the storage node and a second memory capacitor of the plurality of memory capacitors; a third switch coupled between the storage node and a third memory capacitor of the plurality of memory capacitors; and A logic gate having a first input terminal coupled to a first node disposed between the first switch and the first storage capacitor, a second input terminal coupled to a second node disposed between the second switch and the second storage capacitor, a third input terminal coupled to a third node disposed between the third switch and the third storage capacitor, and an output terminal coupled to a quenching transistor coupled to the cathode terminal of the photodiode.

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