Low-noise high-precision image sensor reading circuit and reading method

Abstract

The invention discloses a low-noise high-precision image sensor reading circuit and a reading method, and relates to the field of analog integrated circuits. The first chopping switch circuit receives a low-frequency analog output signal from an image sensor and modulates the low-frequency analog output signal into a high-frequency analog output signal in a chopping mode, the high-frequency analog output signal is converted into a current signal through a transconductance operational amplifier Gm1, and meanwhile the signal amplitude is preliminarily enhanced; the amplified high-frequency analog output signal is further amplified by a second-stage transconductance operational amplifier Gm2, then is subjected to filtering and error correction by a feedback network, and is adjusted by transconductance operational amplifiers Gm3 and Gm4 of a closed-loop feedback loop, and then a low-frequency component analog output signal, namely a high-precision image signal, is output; the high-precision image signal is transmitted to a high-precision ADC to wait for further digital processing. The image sensor reading circuit solves the problems of low-frequency noise, input offset voltage interference and balance between energy consumption and linearity in an existing image sensor reading circuit.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, and in particular to a low-noise and high-precision image sensor readout circuit and a readout method. Background Art

[0002] With the widespread application of image sensors in consumer electronics, industrial detection, and medical imaging, the performance of their readout circuits has become an important factor limiting the overall performance of the sensor. In the prior art, in order to reduce signal noise and improve readout accuracy, an operational amplifier and a low-frequency noise compensation circuit are usually combined. However, the traditional design has the following main problems:

[0003] 1. Interference of low-frequency noise and offset voltage: In the high-precision image signal processing, the low-frequency noise and input offset voltage of the existing amplifier circuit are difficult to completely eliminate, resulting in a decrease in image quality.

[0004] 2. Trade-off between energy consumption and linearity: In miniaturization and low-power applications, the power consumption optimization of existing bias circuits often sacrifices linearity and dynamic range, and cannot take into account both high performance and low power requirements.

[0005] Publication No. CN201710750060.9 discloses an image sensor readout circuit, in which a pixel unit includes a source follower, and the substrate of the source follower is grounded; the readout circuit includes an operational amplifier, but this technical solution has problems in processing image signals, such as large noise (low-frequency noise) and high offset, which leads to reduced image quality, and the resulting problem of nonlinearity in system energy consumption and signal processing. Summary of the invention

[0006] The present invention aims to solve the problems of large noise (low-frequency noise) and high offset in the existing image sensor readout circuit, which leads to degraded image quality, and the resulting nonlinearity in system energy consumption and signal processing, and provides a low-noise and high-precision image sensor readout circuit.

[0007] The technical solution adopted by the present invention is:

[0008] A low-noise, high-precision image sensor readout circuit, the circuit is used to read an image output signal of an image sensor (1); the output end of the circuit is connected to a high-precision ADC, and the high-precision ADC is used to perform image decoding and display on the image output signal sent by the circuit;

[0009] The circuit comprises a chopper amplifier (2) and a closed feedback loop (3);

[0010] The chopper amplifier (2) comprises a first chopper switch circuit (4), a second chopper switch circuit (5), a third chopper switch circuit (6), resistors R1, R2, R3, and transconductance amplifiers Gm1 and Gm2;

[0011] The closed feedback loop (3) includes transconductance amplifiers Gm3 and Gm4, a fourth chopper switch circuit (7), a capacitor Cint1, a capacitor Cint2, a capacitor C3 and a capacitor C4;

[0012] The transconductance amplifiers Gm1, Gm2, Gm3, and Gm4 have the same structure, and all include input end interfaces Vin+, Vin-, and output end interfaces Vout+, Vout-;

[0013] The first chopper switch circuit (4), the second chopper switch circuit (5), the third chopper switch circuit (6), and the fourth chopper switch circuit (7) have the same structure, that is, they include input terminals Vin+, Vin-, output terminals Vout+, Vout-, normally open switches sw1, sw4, and normally closed switches sw2, sw3;

[0014] The input terminal Vin+ is connected to one end of the normally open switch sw1 and one end of the normally closed switch sw2 at the same time, and the other end of the normally open switch sw1 is connected to the output terminal Vout+ and the other end of the normally closed switch sw3 at the same time;

[0015] The input terminal Vin- is connected to one end of the normally open switch sw4 and one end of the normally closed switch sw3 at the same time, and the other end of the normally open switch sw4 is connected to the output terminal Vout- and the other end of the normally closed switch sw1 at the same time;

[0016] The output terminal Vout+ of the first chopper switch circuit (4) is connected to the input terminal interface Vin+ of the transconductance amplifier Gm1, and the output terminal Vout- of the first chopper switch circuit (4) is connected to the input terminal interface Vin- of the transconductance amplifier Gm1;

[0017] The output terminal interface Vout+ of the transconductance amplifier Gm1 is simultaneously connected to the input terminal interface Vin+ of the second chopper switch circuit (5), the output terminal interface Vout+ of the transconductance amplifier Gm2, and the output terminal interface Vout+ of the transconductance amplifier Gm4; the output terminal interface Vout- of the transconductance amplifier Gm1 is simultaneously connected to the input terminal interface Vin+ of the second chopper switch circuit (5), the output terminal interface Vout- of the transconductance amplifier Gm2, and the output terminal interface Vout- of the transconductance amplifier Gm4;

[0018] The output end interfaces Vout+ and Vout- of the second chopper switch circuit (5) are respectively connected to the two ends of the resistor R1; one end of the resistor R1 is also simultaneously connected to the high-precision ADC and one end of the capacitor C3; the other end of the resistor R1 is simultaneously connected to one end of the resistor R2 and the input end Vin+ of the third chopper switch circuit (6); the other end of the resistor R2 is simultaneously connected to one end of the resistor R3 and the input end Vin- of the third chopper switch circuit (6); the output end Vout+ of the third chopper switch circuit (6) is connected to the input end interface Vin+ of the transconductance amplifier Gm2; the output end Vout- of the third chopper switch circuit (6) is connected to the input end interface Vin- of the transconductance amplifier Gm2; the output end interface Vout+ of the transconductance amplifier Gm2 is connected; the other end of the resistor R3 is simultaneously connected to the high-precision ADC and one end of the capacitor C3;

[0019] The input terminal interface Vin+ of the transconductance amplifier Gm4 is simultaneously connected to one end of the capacitor Cint1 and the output terminal interface Vout+ of the transconductance amplifier Gm3; the other end of the capacitor Cint1 is simultaneously connected to the input terminal interface Vin+ of the transconductance amplifier Gm3 and the output terminal Vout+ of the fourth chopper switch circuit (7); the input terminal Vin+ of the fourth chopper switch circuit (7) is connected to the other end of the capacitor C3;

[0020] The input terminal interface Vin- of the transconductance amplifier Gm4 is simultaneously connected to one end of the capacitor Cint2 and the output terminal interface Vout- of the transconductance amplifier Gm3; the other end of the capacitor Cint2 is simultaneously connected to the input terminal interface Vin- of the transconductance amplifier Gm3 and the output terminal Vout- of the fourth chopper switch circuit (7); the input terminal Vin- of the fourth chopper switch circuit (7) is connected to the other end of the capacitor C4; one end of the capacitor C4 is connected to a high-precision ADC.

[0021] Preferably, the transconductance operational amplifiers Gm1, Gm2, Gm3, and Gm4 also include a bias circuit (4) and a main operational amplifier circuit (4);

[0022] The bias circuit (4) comprises transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, nodes Vb1, Vb2, Vb3, power supplies VDD and VSS; the emitters of the transistors Q1, Q4 and Q7 are simultaneously connected to the power supply VDD; the bases of the transistors Q1, Q4 and Q7 are connected to the node Vb1; the collector of the transistor Q1 is connected to the emitter of the transistor Q2, and the collector of the transistor Q2 is simultaneously connected to the collector of the transistor Q3, the base of the transistor Q2, the transistor VSS and the collector of the transistor Q4. The base of transistor Q3; the collector of transistor Q4 is connected to the emitter of transistor Q5, and the collector of transistor Q5, the collector of transistor Q6, the base of transistor Q5, and the base of transistor Q6 are simultaneously connected to node Vb3; the collector of transistor Q7 and the emitter of transistor Q8 are simultaneously connected to node Vb2, and the collector of transistor Q8, the collector of transistor Q9, and the base of transistor Q8 are simultaneously connected to the base of transistor Q9; the emitters of transistors Q3, Q6, and Q9 are simultaneously connected to the power supply VSS.

[0023] The main operational amplifier circuit (4) comprises transistors Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, capacitor C1, capacitor C2, input end interfaces Vin+, Vin-, output ends Vout+, Vout-, nodes Vn, Vp, Vcmfb; one end of the node Vn is connected to the collector of the transistor Q12, the input end interface Vin+ is connected to the base of the transistor Q12, one end of the node Vp is connected to the collector of the transistor Q13, the input end interface Vin- is connected to the base of the transistor Q13, and the emitter of the transistor Q13 is connected to the collector of the transistor Q13. The emitter of transistor Q12 and the collector of transistor Q11 are connected; node Vb3 is connected to the base of transistor Q11, node Vb1 is connected to the base of transistor Q10, the emitter of transistor Q11 is connected to the collector of transistor Q10, and the emitters of transistors Q10, Q14, Q22, Q23, and Q27 are simultaneously connected to the power supply VDD; the base of transistor Q14 is simultaneously connected to the collector of transistor Q22 and the emitter of transistor Q19; the collector of transistor Q14 is simultaneously connected to the base of transistor Q19 and the collector of transistor Q15; the base of transistor Q15 is connected to node Vb2, the emitter of transistor Q15 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the emitter of transistor Q16. The base of transistor Q16 is connected to node Vb1, the collector of transistor Q16 is connected to the base of transistor Q20 and the collector of transistor Q17 at the same time, the base of transistor Q17 is connected to node Vn, the collector of transistor Q18, the collector of transistor Q21 and the emitter of transistor Q20 at the same time; the emitters of transistors Q17, Q18, Q21, Q26, Q31 and Q30 are connected to power supply VSS at the same time; the base of transistor Q22 and the base of transistor Q23 are connected to node Vb1 at the same time, the collector of transistor Q19 and the collector of transistor Q20 are connected to output terminal Vout+ at the same time, the base of transistor Q21 and the base of transistor Q26 are connected to node Vcmfb at the same time, the collector of transistor Q23 is connected to node Vcmfb at the same time. The emitter of transistor Q24 and the base of transistor Q27 are connected, the base of transistor Q24 is simultaneously connected to the collector of transistor Q27 and the collector of transistor Q28, the collector of transistor Q24 is simultaneously connected to the collector of transistor Q25 and the output terminal Vout-, the collector of transistor Q24 and the base of transistor Q25 are simultaneously connected to the collector of transistor Q29 and the collector of transistor Q30, the emitter of transistor Q25 is simultaneously connected to the collector of transistor Q26, the base of transistor Q30, the collector of transistor Q31 and the node Vp; the base of transistor Q28 is connected to the node Vb2, the emitter of transistor Q28 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the emitter of transistor Q29.

[0024] A readout method based on a low-noise and high-precision image sensor readout circuit, the method specifically includes:

[0025] Step 1: The image sensor (1) sends an image output signal;

[0026] Step 2: The first chopper switch circuit (4) in the chopper amplifier (2) receives the image output signal, and outputs a high-precision image output signal to a high-precision ADC after filtering and amplification by transconductance amplifiers Gm1, Gm2, Gm3, and Gm4;

[0027] Step 3: The high-precision ADC receives the high-precision image output signal.

[0028] Preferably, the specific method in which the first chopper switch circuit (4) in the chopper amplifier (2) in step 2 receives the image output signal and outputs the high-precision image output signal to the high-precision ADC after filtering and amplification by transconductance amplifiers Gm1, Gm2, Gm3, and Gm4 is:

[0029] Step 1: Chopping process: The first chopping switch circuit (4) receives the low-frequency analog output signal from the image sensor (1), and modulates the low-frequency analog output signal into a high-frequency analog output signal by chopping. The high-frequency analog output signal is modulated by the chopping frequency f chop Decide;

[0030] Step 2: Transconductance amplification process: The high-frequency analog output signal is converted into a current signal by the transconductance amplifier Gm1, and the signal amplitude is initially enhanced, that is, the high-frequency analog output signal is amplified. The amplified high-frequency analog output signal is further amplified by the second-stage transconductance amplifier Gm2;

[0031] Step 3: Feedback filtering process: The high-frequency analog output signal amplified by the transconductance amplifier Gm2 is filtered and error corrected through the feedback network. At the same time, the high-frequency analog output signal amplified by the transconductance amplifier Gm2 is adjusted by the transconductance amplifiers Gm3 and Gm4 of the closed-loop feedback loop (3) to output a low-frequency component analog output signal;

[0032] Step 4: High-precision output process: The low-frequency component analog output signal is the high-precision image signal, which is transmitted to the high-precision ADC for further digital processing.

[0033] Preferably, the feedback network in step three is a circuit composed of resistors R1, R2, R3 and capacitors Cint1, Cint2.

[0034] Preferably, the transconductance amplifiers Gm3 and Gm4 of the closed-loop feedback loop (3) are adjusted to output a low-frequency component analog output signal, wherein the transconductance amplifiers Gm3 and Gm4 are used to stabilize the loop gain and dynamically adjust the system bias error.

[0035] Preferably, the noise component of the low-frequency component analog output signal in step 4 is significantly reduced.

[0036] Preferably, the chopping process, transconductance amplification process, feedback filtering process and high-precision output process are all controlled by a synchronous clock.

[0037] Beneficial effects:

[0038] Low noise performance: The present invention effectively suppresses low-frequency noise and input offset voltage by using a chopper amplifier, thereby improving the processing accuracy of image signals. Compared with the prior art, the noise suppression effect is improved by about 30%, greatly reducing the background noise in the signal, thereby improving image quality.

[0039] High precision: The use of precise bias circuits and feedback mechanisms ensures the linearity and stability of the signal, solving the problem of signal distortion caused by bias current fluctuations in traditional circuits. Through this solution, the accuracy of the readout circuit is improved by about 25%, and the dynamic range is significantly improved.

[0040] Low power consumption: Through optimized power management design and bias circuit, the circuit significantly reduces power consumption while ensuring high accuracy. Compared with existing technologies, power consumption is reduced by about 40%, which is particularly suitable for low-power and portable devices.

[0041] The circuit design of the present invention has a simplified structure, reduces complex external components, reduces system complexity and failure rate. The user only needs to provide a stable power supply and input signal to easily achieve efficient image sensor readout, simplifying the operation process.

[0042] The present invention solves the problems of low-frequency noise, input offset voltage interference and the trade-off between energy consumption and linearity existing in the existing image sensor readout circuit. By designing a readout circuit based on chopping amplification and an optimized bias circuit, low-noise and high-precision image signal reading is achieved while taking into account the low power consumption requirement. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the overall structure of a low-noise and high-precision image sensor readout circuit;

[0044] Figure 2 It is a schematic diagram of the connection relationship of the main operational amplifier circuit in the present invention;

[0045] Figure 3is a schematic diagram of the connection relationship of the bias circuit in the present invention;

[0046] Figure 4 It is a schematic diagram of the connection relationship of the chopper switch circuit in the present invention;

[0047] Figure 5 It is a waveform diagram of a low-noise, high-precision image sensor readout circuit;

[0048] Component numbers: Image sensor input (Input Sensor); Chopper Amplifier; Bias Circuit; Closed-loop feedback circuit (Feedback Network); Output (Output); Switching Element; High-precision ADC is a high-precision analog-to-digital converter. DETAILED DESCRIPTION

[0049] Specific implementation method 1. Reference Figures 1 to 5 Specifically describing this embodiment, a low-noise high-precision image sensor readout circuit described in this embodiment is used to read an image output signal of an image sensor (1); the output end of the circuit is connected to a high-precision ADC, and the high-precision ADC is used to decode and display the image output signal sent by the circuit;

[0050] The circuit comprises a chopper amplifier (2) and a closed feedback loop (3);

[0051] The chopper amplifier (2) comprises a first chopper switch circuit (4), a second chopper switch circuit (5), a third chopper switch circuit (6), resistors R1, R2, R3, and transconductance amplifiers Gm1 and Gm2;

[0052] The closed feedback loop (3) includes transconductance amplifiers Gm3 and Gm4, a fourth chopper switch circuit (7), a capacitor Cint1, a capacitor Cint2, a capacitor C3 and a capacitor C4;

[0053] The transconductance amplifiers Gm1, Gm2, Gm3, and Gm4 have the same structure, and all include input end interfaces Vin+, Vin-, and output end interfaces Vout+, Vout-;

[0054] The first chopper switch circuit (4), the second chopper switch circuit (5), the third chopper switch circuit (6), and the fourth chopper switch circuit (7) have the same structure, that is, they include input terminals Vin+, Vin-, output terminals Vout+, Vout-, normally open switches sw1, sw4, and normally closed switches sw2, sw3;

[0055] The input terminal Vin+ is connected to one end of the normally open switch sw1 and one end of the normally closed switch sw2 at the same time, and the other end of the normally open switch sw1 is connected to the output terminal Vout+ and the other end of the normally closed switch sw3 at the same time;

[0056] The input terminal Vin- is connected to one end of the normally open switch sw4 and one end of the normally closed switch sw3 at the same time, and the other end of the normally open switch sw4 is connected to the output terminal Vout- and the other end of the normally closed switch sw1 at the same time;

[0057] The output terminal Vout+ of the first chopper switch circuit (4) is connected to the input terminal interface Vin+ of the transconductance amplifier Gm1, and the output terminal Vout- of the first chopper switch circuit (4) is connected to the input terminal interface Vin- of the transconductance amplifier Gm1;

[0058] The output terminal interface Vout+ of the transconductance amplifier Gm1 is simultaneously connected to the input terminal interface Vin+ of the second chopper switch circuit (5), the output terminal interface Vout+ of the transconductance amplifier Gm2, and the output terminal interface Vout+ of the transconductance amplifier Gm4; the output terminal interface Vout- of the transconductance amplifier Gm1 is simultaneously connected to the input terminal interface Vin+ of the second chopper switch circuit (5), the output terminal interface Vout- of the transconductance amplifier Gm2, and the output terminal interface Vout- of the transconductance amplifier Gm4;

[0059] The output end interfaces Vout+ and Vout- of the second chopper switch circuit (5) are respectively connected to the two ends of the resistor R1; one end of the resistor R1 is also simultaneously connected to the high-precision ADC and one end of the capacitor C3; the other end of the resistor R1 is simultaneously connected to one end of the resistor R2 and the input end Vin+ of the third chopper switch circuit (6); the other end of the resistor R2 is simultaneously connected to one end of the resistor R3 and the input end Vin- of the third chopper switch circuit (6); the output end Vout+ of the third chopper switch circuit (6) is connected to the input end interface Vin+ of the transconductance amplifier Gm2; the output end Vout- of the third chopper switch circuit (6) is connected to the input end interface Vin- of the transconductance amplifier Gm2; the output end interface Vout+ of the transconductance amplifier Gm2 is connected; the other end of the resistor R3 is simultaneously connected to the high-precision ADC and one end of the capacitor C3;

[0060] The input terminal interface Vin+ of the transconductance amplifier Gm4 is simultaneously connected to one end of the capacitor Cint1 and the output terminal interface Vout+ of the transconductance amplifier Gm3; the other end of the capacitor Cint1 is simultaneously connected to the input terminal interface Vin+ of the transconductance amplifier Gm3 and the output terminal Vout+ of the fourth chopper switch circuit (7); the input terminal Vin+ of the fourth chopper switch circuit (7) is connected to the other end of the capacitor C3;

[0061] The input terminal interface Vin- of the transconductance amplifier Gm4 is simultaneously connected to one end of the capacitor Cint2 and the output terminal interface Vout- of the transconductance amplifier Gm3; the other end of the capacitor Cint2 is simultaneously connected to the input terminal interface Vin- of the transconductance amplifier Gm3 and the output terminal Vout- of the fourth chopper switch circuit (7); the input terminal Vin- of the fourth chopper switch circuit (7) is connected to the other end of the capacitor C4; one end of the capacitor C4 is connected to a high-precision ADC.

[0062] Working principle: The first chopping switch circuit (4) receives the low-frequency analog output signal from the image sensor (1), and modulates the low-frequency analog output signal into a high-frequency analog output signal by chopping. The high-frequency analog output signal is modulated by the chopping frequency f chop The high-frequency analog output signal is converted into a current signal by the transconductance amplifier Gm1, and the signal amplitude is initially enhanced, that is, the high-frequency analog output signal is amplified. The amplified high-frequency analog output signal is further amplified by the second-stage transconductance amplifier Gm2. The high-frequency analog output signal amplified by the transconductance amplifier Gm2 is filtered and error corrected by the feedback network. At the same time, the high-frequency analog output signal amplified by the transconductance amplifier Gm2 is also adjusted by the transconductance amplifiers Gm3 and Gm4 of the closed-loop feedback loop (3) to output a low-frequency component analog output signal. High-precision output process: the low-frequency component analog output signal is a high-precision image signal, and the high-precision image signal is transmitted to the high-precision ADC to wait for further digital processing.

[0063] The circuit design of the present invention has a simplified structure, reduces complex external components, reduces system complexity and failure rate. The user only needs to provide a stable power supply and input signal to easily achieve efficient image sensor readout, simplifying the operation process.

[0064] The present invention solves the problems of low-frequency noise, input offset voltage interference and the trade-off between energy consumption and linearity existing in the existing image sensor readout circuit. By designing a readout circuit based on chopping amplification and an optimized bias circuit, low-noise and high-precision image signal reading is achieved while taking into account the low power consumption requirement.

[0065] Specific implementation method 2. This implementation method is a further description of a low-noise and high-precision image sensor readout circuit described in implementation method 1. In this implementation method, the transconductance amplifiers Gm1, Gm2, Gm3, and Gm4 all further include a bias circuit (4) and a main amplifier circuit (4);

[0066] The bias circuit (4) comprises transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, nodes Vb1, Vb2, Vb3, power supplies VDD and VSS; the emitters of the transistors Q1, Q4 and Q7 are simultaneously connected to the power supply VDD; the bases of the transistors Q1, Q4 and Q7 are connected to the node Vb1; the collector of the transistor Q1 is connected to the emitter of the transistor Q2, and the collector of the transistor Q2 is simultaneously connected to the collector of the transistor Q3, the base of the transistor Q2, the transistor VSS and the collector of the transistor Q4. The base of transistor Q3; the collector of transistor Q4 is connected to the emitter of transistor Q5, and the collector of transistor Q5, the collector of transistor Q6, the base of transistor Q5, and the base of transistor Q6 are simultaneously connected to node Vb3; the collector of transistor Q7 and the emitter of transistor Q8 are simultaneously connected to node Vb2, and the collector of transistor Q8, the collector of transistor Q9, and the base of transistor Q8 are simultaneously connected to the base of transistor Q9; the emitters of transistors Q3, Q6, and Q9 are simultaneously connected to the power supply VSS.

[0067] The main operational amplifier circuit (4) comprises transistors Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, capacitor C1, capacitor C2, input end interfaces Vin+, Vin-, output ends Vout+, Vout-, nodes Vn, Vp, Vcmfb; one end of the node Vn is connected to the collector of the transistor Q12, the input end interface Vin+ is connected to the base of the transistor Q12, one end of the node Vp is connected to the collector of the transistor Q13, the input end interface Vin- is connected to the base of the transistor Q13, and the emitter of the transistor Q13 is connected to the collector of the transistor Q13. The emitter of transistor Q12 and the collector of transistor Q11 are connected; node Vb3 is connected to the base of transistor Q11, node Vb1 is connected to the base of transistor Q10, the emitter of transistor Q11 is connected to the collector of transistor Q10, and the emitters of transistors Q10, Q14, Q22, Q23, and Q27 are simultaneously connected to the power supply VDD; the base of transistor Q14 is simultaneously connected to the collector of transistor Q22 and the emitter of transistor Q19; the collector of transistor Q14 is simultaneously connected to the base of transistor Q19 and the collector of transistor Q15; the base of transistor Q15 is connected to node Vb2, the emitter of transistor Q15 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the emitter of transistor Q16. The base of transistor Q16 is connected to node Vb1, the collector of transistor Q16 is connected to the base of transistor Q20 and the collector of transistor Q17 at the same time, the base of transistor Q17 is connected to node Vn, the collector of transistor Q18, the collector of transistor Q21 and the emitter of transistor Q20 at the same time; the emitters of transistors Q17, Q18, Q21, Q26, Q31 and Q30 are connected to power supply VSS at the same time; the base of transistor Q22 and the base of transistor Q23 are connected to node Vb1 at the same time, the collector of transistor Q19 and the collector of transistor Q20 are connected to output terminal Vout+ at the same time, the base of transistor Q21 and the base of transistor Q26 are connected to node Vcmfb at the same time, the collector of transistor Q23 is connected to node Vcmfb at the same time. The emitter of transistor Q24 and the base of transistor Q27 are connected, the base of transistor Q24 is simultaneously connected to the collector of transistor Q27 and the collector of transistor Q28, the collector of transistor Q24 is simultaneously connected to the collector of transistor Q25 and the output terminal Vout-, the collector of transistor Q24 and the base of transistor Q25 are simultaneously connected to the collector of transistor Q29 and the collector of transistor Q30, the emitter of transistor Q25 is simultaneously connected to the collector of transistor Q26, the base of transistor Q30, the collector of transistor Q31 and the node Vp; the base of transistor Q28 is connected to the node Vb2, the emitter of transistor Q28 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the emitter of transistor Q29.

[0068] Specific implementation method 3: Based on the readout method of a low-noise and high-precision image sensor readout circuit described in implementation method 2, the method specifically includes:

[0069] Step 1: The image sensor (1) sends an image output signal;

[0070] Step 2: The first chopper switch circuit (4) in the chopper amplifier (2) receives the image output signal, and outputs a high-precision image output signal to a high-precision ADC after filtering and amplification by transconductance amplifiers Gm1, Gm2, Gm3, and Gm4;

[0071] Step 3: The high-precision ADC receives the high-precision image output signal.

[0072] Specific implementation method 4: According to the readout method of a low-noise high-precision image sensor readout circuit described in implementation method 3, the specific method of the first chopper switch circuit (4) in the chopper amplifier (2) in step 2 receiving the image output signal and outputting the high-precision image output signal to the high-precision ADC after filtering and amplification by transconductance amplifiers Gm1, Gm2, Gm3, and Gm4 is as follows:

[0073] Step 1: Chopping process: The first chopping switch circuit (4) receives the low-frequency analog output signal from the image sensor (1), and modulates the low-frequency analog output signal into a high-frequency analog output signal by chopping. The high-frequency analog output signal is modulated by the chopping frequency f chop Decide;

[0074] Step 2: Transconductance amplification process: The high-frequency analog output signal is converted into a current signal by the transconductance amplifier Gm1, and the signal amplitude is initially enhanced, that is, the high-frequency analog output signal is amplified. The amplified high-frequency analog output signal is further amplified by the second-stage transconductance amplifier Gm2;

[0075] Step 3: Feedback filtering process: The high-frequency analog output signal amplified by the transconductance amplifier Gm2 is filtered and error corrected through the feedback network. At the same time, the high-frequency analog output signal amplified by the transconductance amplifier Gm2 is adjusted by the transconductance amplifiers Gm3 and Gm4 of the closed-loop feedback loop (3) to output a low-frequency component analog output signal;

[0076] Step 4: High-precision output process: The low-frequency component analog output signal is the high-precision image signal, which is transmitted to the high-precision ADC for further digital processing.

[0077] In this embodiment, the low-frequency component analog output signal obtained after the processing in steps one to three is the original low-frequency component with significantly reduced noise components.

[0078] Through the above steps, the circuit can achieve high-precision, low-noise image signal readout and provide high-quality raw data for subsequent image processing.

[0079] Specific implementation method 5: According to the readout method of a low-noise and high-precision image sensor readout circuit described in implementation method 4, the feedback network in step 3 is a circuit composed of resistors R1, R2, R3 and capacitors Cint1, Cint2.

[0080] Specific implementation method six: According to a readout method of a low-noise and high-precision image sensor readout circuit described in implementation method five, the transconductance amplifiers Gm3 and Gm4 of the closed-loop feedback loop (3) are adjusted to output a low-frequency component analog output signal, wherein the transconductance amplifiers Gm3 and Gm4 are used to stabilize the loop gain and dynamically adjust the system bias error.

[0081] Specific implementation method 7: According to the readout method of a low-noise and high-precision image sensor readout circuit described in implementation method 5, the noise component of the low-frequency component analog output signal in step 4 is significantly reduced.

[0082] Specific implementation example eight, according to a readout method of a low-noise and high-precision image sensor readout circuit as described in implementation example four, the chopping processing process, transconductance amplification process, feedback filtering process and high-precision output process are all controlled by a synchronous clock to ensure that the modulation and demodulation of the signal are fully aligned to avoid signal distortion caused by phase error.

[0083] The present invention solves the influence of low-frequency noise and input offset voltage on signal processing by designing a low-noise, high-precision image sensor readout circuit, combining a chopper amplifier with an optimized bias circuit. The specific solutions include:

[0084] Chopper amplifier design: Chopper technology is used to effectively suppress low-frequency noise and input offset voltage, thereby improving the signal processing accuracy of the circuit. Through the periodic switching of the chopper switch, the DC component of the input signal is dynamically balanced to reduce the interference of low-frequency noise on the signal.

[0085] Bias circuit optimization: Use precise current source and feedback network to ensure the circuit's operating point is stable and provide highly linear bias current, avoiding the contradiction between energy consumption and linearity that is common in existing circuits.

[0086] Component connection relationship description:

[0087] According to the two circuit diagrams provided, the basic connection relationship of the circuit is as follows:

[0088] Input end: The output signal of the image sensor is connected to the input end of the chopper amplifier through the input end, and the chopper realizes signal filtering processing through periodic switching.

[0089] Chopper amplifier: A chopper amplifier passes the processed signal to the output through a feedback loop, ensuring signal gain while suppressing low-frequency noise.

[0090] Bias circuit: The bias circuit provides a stable power supply and bias current, which is connected to the chopper amplifier and the input signal terminal to ensure the stability and accuracy of signal processing.

[0091] Output end: The optimized signal is transmitted through the output end for use by the subsequent image signal processing module.

[0092] The main performance indicators of the present invention are:

[0093] Noise Level:

[0094] The test results show that the low-frequency noise at 100Hz is reduced from 4μV to 30nV, which significantly improves the quality of image signals. Compared with traditional designs, the noise level is reduced by two orders of magnitude.

[0095] Accuracy:

[0096] The signal gain accuracy of the circuit reaches ±0.1%, which is 25% higher than the existing technology.

[0097] Power consumption:

[0098] The power consumption of the entire circuit is reduced by 40% compared with the traditional design.

[0099] Dynamic Range:

[0100] The dynamic range is increased to 90dB, which significantly improves the signal processing capability of the image sensor and adapts to a wider range of application scenarios.

[0101] Service life:

[0102] Due to the use of high-quality components and optimized power management design, the stability and service life of the circuit are improved.

[0103] Comparison with existing technologies:

[0104] In the prior art, image sensor readout circuits often face problems such as low-frequency noise interference, excessive power consumption, and insufficient signal processing accuracy. These problems are successfully solved through the chopper amplifier and optimized bias circuit design of the present invention. Specifically:

[0105] Noise problem: The existing circuit has obvious deficiencies in suppressing low-frequency noise. The design of the present invention can effectively suppress low-frequency noise and improve signal quality.

[0106] Power consumption: Existing designs often have high power consumption while improving accuracy, but the present invention significantly reduces power consumption by optimizing power management and bias circuit design.

[0107] Accuracy issue: Traditional circuits have fluctuations in signal gain accuracy, but the present invention adopts a precise feedback mechanism and bias current design to significantly improve the accuracy and stability of the signal.

[0108] Example 1: Application of image sensor readout circuit

[0109] Applications:

[0110] This embodiment is suitable for image sensor readout systems in portable intelligent camera devices, especially in low-light environments and high-precision imaging scenarios, such as smart phones, security monitoring equipment, drone cameras, etc.

[0111] Structure Description:

[0112] Input terminal: The output signal of the image sensor is connected to the input terminal of the image sensor readout circuit designed by the present invention. The input terminal signal comes from the output terminal of the image sensor, which is usually a voltage signal. The signal contains image information, but may contain certain low-frequency noise and offset voltage.

[0113] Chopper amplifier: The input signal is processed by a chopper amplifier. The chopper amplifier dynamically suppresses low-frequency noise in the input signal through periodic switching, reduces the interference of the DC component on the signal, and thus improves the quality and accuracy of the signal. The switching frequency of the chopper is set to 1kHz to effectively filter out low-frequency noise.

[0114] Bias circuit: The bias circuit provides accurate bias current through a stable current source to ensure that the amplifier and other circuit components operate at a stable operating point. In order to reduce power consumption, this embodiment uses low-power CMOS technology to implement the bias current source, ensuring that the power consumption of the entire circuit remains at around 15mW.

[0115] Feedback circuit: The feedback circuit is responsible for transmitting the amplified signal to the output end and maintaining the linearity of the circuit through a negative feedback mechanism to ensure the gain accuracy of the signal. This feedback circuit helps to improve the dynamic range of the signal and avoid signal distortion caused by nonlinear effects.

[0116] Output end: The processed signal is transmitted to the back-end image processing module through the output end for further image decoding and display.

[0117] Working principle:

[0118] The image sensor converts the light signal into an electrical signal through its photosensitive element and outputs it to the image readout circuit of the present invention. The circuit eliminates low-frequency noise through the filtering effect of the chopper amplifier, and provides stable working conditions through the optimized bias circuit to ensure high precision and high stability of signal processing. The processed signal is transmitted to the output end through the feedback circuit and finally provided to the high-precision ADC.

[0119] Effect:

[0120] Noise suppression: Compared with traditional image sensor readout circuits, the present invention shows significant advantages in low-frequency noise suppression, with improved image quality and a noise level reduced by about 30%.

[0121] Improved accuracy: Due to the use of precise feedback circuit and optimized bias current design, the accuracy of signal gain is improved to ±0.1%, ensuring high accuracy of image signal reading.

[0122] Reduced power consumption: The power consumption of the entire circuit is reduced by 40% compared with the existing technology, which is suitable for the application of low-power devices.

[0123] Dynamic range expansion: Through optimized signal processing circuits, the dynamic range is increased to 90dB, providing clear image output in a wider range of environments.

[0124] The present invention is described by several specific embodiments, and it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. In addition, various modifications may be made to the present invention for specific situations or specific circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all implementation methods falling within the scope of the claims of the present invention.

Claims

1. A low-noise, high-precision image sensor readout circuit, the circuit being used to read an image output signal of an image sensor (1); the output end of the circuit being connected to a high-precision ADC, the high-precision ADC being used to decode and display the image output signal sent by the circuit; It is characterized in that The circuit comprises a chopper amplifier (2) and a closed feedback loop (3); The chopper amplifier (2) comprises a first chopper switch circuit (4), a second chopper switch circuit (5), a third chopper switch circuit (6), resistors R1, R2, R3, and transconductance amplifiers Gm1 and Gm2; The closed feedback loop (3) includes transconductance amplifiers Gm3 and Gm4, a fourth chopper switch circuit (7), a capacitor Cint1, a capacitor Cint2, a capacitor C3 and a capacitor C4; The transconductance amplifiers Gm1, Gm2, Gm3, and Gm4 have the same structure, and all include input end interfaces Vin+, Vin-, and output end interfaces Vout+, Vout-; The first chopper switch circuit (4), the second chopper switch circuit (5), the third chopper switch circuit (6), and the fourth chopper switch circuit (7) have the same structure, that is, they include input terminals Vin+, Vin-, output terminals Vout+, Vout-, normally open switches sw1, sw4, and normally closed switches sw2, sw3; The input terminal Vin+ is connected to one end of the normally open switch sw1 and one end of the normally closed switch sw2 at the same time, and the other end of the normally open switch sw1 is connected to the output terminal Vout+ and the other end of the normally closed switch sw3 at the same time; The input terminal Vin- is connected to one end of the normally open switch sw4 and one end of the normally closed switch sw3 at the same time, and the other end of the normally open switch sw4 is connected to the output terminal Vout- and the other end of the normally closed switch sw1 at the same time; The output terminal Vout+ of the first chopper switch circuit (4) is connected to the input terminal interface Vin+ of the transconductance amplifier Gm1, and the output terminal Vout- of the first chopper switch circuit (4) is connected to the input terminal interface Vin- of the transconductance amplifier Gm1; The output terminal interface Vout+ of the transconductance amplifier Gm1 is simultaneously connected to the input terminal interface Vin+ of the second chopper switch circuit (5), the output terminal interface Vout+ of the transconductance amplifier Gm2, and the output terminal interface Vout+ of the transconductance amplifier Gm4; the output terminal interface Vout- of the transconductance amplifier Gm1 is simultaneously connected to the input terminal interface Vin+ of the second chopper switch circuit (5), the output terminal interface Vout- of the transconductance amplifier Gm2, and the output terminal interface Vout- of the transconductance amplifier Gm4; The output end interfaces Vout+ and Vout- of the second chopper switch circuit (5) are respectively connected to the two ends of the resistor R1; one end of the resistor R1 is also simultaneously connected to the high-precision ADC and one end of the capacitor C3; the other end of the resistor R1 is simultaneously connected to one end of the resistor R2 and the input end Vin+ of the third chopper switch circuit (6); the other end of the resistor R2 is simultaneously connected to one end of the resistor R3 and the input end Vin- of the third chopper switch circuit (6); the output end Vout+ of the third chopper switch circuit (6) is connected to the input end interface Vin+ of the transconductance amplifier Gm2; the output end Vout- of the third chopper switch circuit (6) is connected to the input end interface Vin- of the transconductance amplifier Gm2; the output end interface Vout+ of the transconductance amplifier Gm2 is connected; the other end of the resistor R3 is simultaneously connected to the high-precision ADC and one end of the capacitor C3; The input terminal interface Vin+ of the transconductance amplifier Gm4 is simultaneously connected to one end of the capacitor Cint1 and the output terminal interface Vout+ of the transconductance amplifier Gm3; the other end of the capacitor Cint1 is simultaneously connected to the input terminal interface Vin+ of the transconductance amplifier Gm3 and the output terminal Vout+ of the fourth chopper switch circuit (7); the input terminal Vin+ of the fourth chopper switch circuit (7) is connected to the other end of the capacitor C3; The input terminal interface Vin- of the transconductance amplifier Gm4 is simultaneously connected to one end of the capacitor Cint2 and the output terminal interface Vout- of the transconductance amplifier Gm3; the other end of the capacitor Cint2 is simultaneously connected to the input terminal interface Vin- of the transconductance amplifier Gm3 and the output terminal Vout- of the fourth chopper switch circuit (7); the input terminal Vin- of the fourth chopper switch circuit (7) is connected to the other end of the capacitor C4; one end of the capacitor C4 is connected to a high-precision ADC.

2. A low-noise and high-precision image sensor readout circuit according to claim 1, characterized in that: The transconductance operational amplifiers Gm1, Gm2, Gm3, and Gm4 also include a bias circuit (4) and a main operational amplifier circuit (4); The bias circuit (4) comprises transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, nodes Vb1, Vb2, Vb3, power supplies VDD and VSS; the emitters of transistors Q1, Q4 and Q7 are simultaneously connected to the power supply VDD; the bases of transistors Q1, Q4 and Q7 are connected to the node Vb1; the collector of transistor Q1 is connected to the emitter of transistor Q2, the collector of transistor Q2 is simultaneously connected to the collector of transistor Q3, the base of transistor Q2 and the base of transistor Q3; the collector of transistor Q4 is connected to the emitter of transistor Q5, the collector of transistor Q5, the collector of transistor Q6, the base of transistor Q5 and the base of transistor Q6 are simultaneously connected to the node Vb3; The collector of transistor Q7 and the emitter of transistor Q8 are connected to node Vb2 at the same time, the collector of transistor Q8, the collector of transistor Q9 and the base of transistor Q8 are connected to the base of transistor Q9 at the same time; the emitters of transistors Q3, Q6 and Q9 are connected to power supply VSS at the same time; The main operational amplifier circuit (4) comprises transistors Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, capacitor C1, capacitor C2, input end interfaces Vin+, Vin-, output ends Vout+, Vout-, nodes Vn, Vp, Vcmfb; one end of the node Vn is connected to the collector of the transistor Q12, the input end interface Vin+ is connected to the base of the transistor Q12, one end of the node Vp is connected to the collector of the transistor Q13, the input end interface Vin- is connected to the base of the transistor Q13, and the emitter of the transistor Q13 is connected to the collector of the transistor Q13. The emitter of transistor Q12 and the collector of transistor Q11 are connected; node Vb3 is connected to the base of transistor Q11, node Vb1 is connected to the base of transistor Q10, the emitter of transistor Q11 is connected to the collector of transistor Q10, and the emitters of transistors Q10, Q14, Q22, Q23, and Q27 are simultaneously connected to the power supply VDD; the base of transistor Q14 is simultaneously connected to the collector of transistor Q22 and the emitter of transistor Q19; the collector of transistor Q14 is simultaneously connected to the base of transistor Q19 and the collector of transistor Q15; the base of transistor Q15 is connected to node Vb2, the emitter of transistor Q15 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the emitter of transistor Q16. The base of transistor Q16 is connected to node Vb1, the collector of transistor Q16 is connected to the base of transistor Q20 and the collector of transistor Q17 at the same time, the base of transistor Q17 is connected to node Vn, the collector of transistor Q18, the collector of transistor Q21 and the emitter of transistor Q20 at the same time; the emitters of transistors Q17, Q18, Q21, Q26, Q31 and Q30 are connected to power supply VSS at the same time; the base of transistor Q22 and the base of transistor Q23 are connected to node Vb1 at the same time, the collector of transistor Q19 and the collector of transistor Q20 are connected to output terminal Vout+ at the same time, the base of transistor Q21 and the base of transistor Q26 are connected to node Vcmfb at the same time, the collector of transistor Q23 is connected to node Vcmfb at the same time. The emitter of transistor Q24 and the base of transistor Q27 are connected, the base of transistor Q24 is simultaneously connected to the collector of transistor Q27 and the collector of transistor Q28, the collector of transistor Q24 is simultaneously connected to the collector of transistor Q25 and the output terminal Vout-, the collector of transistor Q24 and the base of transistor Q25 are simultaneously connected to the collector of transistor Q29 and the collector of transistor Q30, the emitter of transistor Q25 is simultaneously connected to the collector of transistor Q26, the base of transistor Q30, the collector of transistor Q31 and the node Vp; the base of transistor Q28 is connected to the node Vb2, the emitter of transistor Q28 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the emitter of transistor Q29.

3. A readout method for a low-noise and high-precision image sensor readout circuit according to claim 2, characterized in that: The method specifically includes: Step 1: The image sensor (1) sends an image output signal; Step 2: The first chopper switch circuit (4) in the chopper amplifier (2) receives the image output signal, and outputs a high-precision image output signal to a high-precision ADC after filtering and amplification by transconductance amplifiers Gm1, Gm2, Gm3, and Gm4; Step 3: The high-precision ADC receives the high-precision image output signal.

4. The readout method of a low-noise and high-precision image sensor readout circuit according to claim 3, characterized in that: The specific method of receiving the image output signal by the first chopper switch circuit (4) in the chopper amplifier (2) in step 2, filtering and amplifying the image output signal through the transconductance amplifiers Gm1, Gm2, Gm3, and Gm4 to output the high-precision image output signal to the high-precision ADC is as follows: Step 1: Chopping process: The first chopping switch circuit (4) receives the low-frequency analog output signal from the image sensor (1), and modulates the low-frequency analog output signal into a high-frequency analog output signal by chopping. The high-frequency analog output signal is modulated by the chopping frequency f chop Decide; Step 2: Transconductance amplification process: The high-frequency analog output signal is converted into a current signal by the transconductance amplifier Gm1, and the signal amplitude is initially enhanced, that is, the high-frequency analog output signal is amplified. The amplified high-frequency analog output signal is further amplified by the second-stage transconductance amplifier Gm2; Step 3: Feedback filtering process: The high-frequency analog output signal amplified by the transconductance amplifier Gm2 is filtered and error corrected through the feedback network. At the same time, the high-frequency analog output signal amplified by the transconductance amplifier Gm2 is adjusted by the transconductance amplifiers Gm3 and Gm4 of the closed-loop feedback loop (3) to output a low-frequency component analog output signal; Step 4: High-precision output process: The low-frequency component analog output signal is the high-precision image signal, which is transmitted to the high-precision ADC for further digital processing.

5. The readout method of a low-noise and high-precision image sensor readout circuit according to claim 4, characterized in that: The feedback network in step three is a circuit composed of resistors R1, R2, R3 and capacitors Cint1, Cint2.

6. The readout method of a low-noise and high-precision image sensor readout circuit according to claim 5, characterized in that: The transconductance amplifiers Gm3 and Gm4 of the closed-loop feedback loop (3) are adjusted to output a low-frequency component analog output signal, wherein the transconductance amplifiers Gm3 and Gm4 are used to stabilize the loop gain and dynamically adjust the system bias error.

7. The readout method of a low-noise and high-precision image sensor readout circuit according to claim 5, characterized in that: The noise component of the low-frequency analog output signal in step 4 is significantly reduced.

8. The readout method of a low-noise and high-precision image sensor readout circuit according to claim 4, characterized in that: The chopping process, transconductance amplification process, feedback filtering process and high-precision output process are all controlled by a synchronous clock.

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