Memory and access method thereof, electronic device

Abstract

A memory and an access method thereof, and an electronic device, the memory comprising: a plurality of layers of memory arrays stacked along a third direction perpendicular to a substrate, the memory array comprising a plurality of memory cells distributed in an array, the memory further comprising: a plurality of second word lines corresponding to rows of the plurality of layers of memory arrays; and a plurality of first word lines corresponding to columns of the plurality of layers of memory arrays; the memory cell comprising a transistor, the transistor comprising a first gate electrode and a second gate electrode, the first gate electrode being connected to the first word line corresponding to the column in which the memory cell is located, and the second gate electrode being connected to the second word line corresponding to the row in which the memory cell is located. The scheme provided by the embodiment can select the memory cells at the same position of different layers through the first word line and the second word line, can reduce the number of word line drivers, can not need to set a gating transistor for word line gating, can not need to increase a process step of manufacturing the gating transistor, can simplify the process, can reduce the cost, and the control logic is simple.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design in the field of semiconductor technology, and particularly to a memory and its access method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs while still achieving the required functionality, it is desirable to reduce the number of devices used. In a conventional 1T1C memory, each memory cell includes an access transistor and a capacitor. The access transistor connects to a word line and a bit line. The word line connects to a word line driver, and the bit line connects to a sense amplifier. The access transistor is selected via the word line, and data is read and written via the bit line. If each word line is connected to an independent word line driver, the number of word line drivers becomes enormous when the memory contains a large number of memory cells, leading to complex manufacturing processes, high costs, and excessively large device sizes. Therefore, considering device size, cost, and manufacturing complexity, it is necessary to reduce the number of word line drivers. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This application provides a memory and its access method, as well as an electronic device, which simplifies the manufacturing process and reduces costs.

[0005] This disclosure provides a memory, including:

[0006] A multilayer memory array stacked along a third direction perpendicular to the substrate, the memory array comprising a plurality of memory cells arrayed along a first direction parallel to the substrate and a second direction parallel to the substrate, the memory further comprising a plurality of second word lines corresponding to rows of the multilayer memory array, and a plurality of first word lines corresponding to columns of the multilayer memory array, each second word line corresponding to the same row of the multilayer memory array, and each first word line corresponding to the same column of the multilayer memory array;

[0007] The memory cell includes a transistor, the transistor including a first gate electrode and a second gate electrode, the first gate electrode being connected to the first word line corresponding to the column where the memory cell is located, and the second gate electrode being connected to the second word line corresponding to the row where the memory cell is located.

[0008] In some embodiments, each layer of the memory array further includes multiple first sub-word lines extending along the third direction. The first gate electrodes of memory cells in the same row and column of different layers are connected to one first sub-word line, the first gate electrodes of different memory cells in the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same column are connected to form one first word line.

[0009] In some embodiments, each layer of the memory array further includes multiple second sub-word lines extending along the third direction. The second gate electrodes of memory cells in the same row and column of different layers are connected to one second sub-word line, and the second gate electrodes of different memory cells in the same layer are connected to different second sub-word lines. Multiple second sub-word lines in the same row are connected to form one second sub-word line.

[0010] In some embodiments, each layer of the memory array further includes: a plurality of bit lines extending along the second direction; the memory further includes: a plurality of common bit lines; a bit line connects memory cells in the same column of the layer where the bit line is located, bit lines in the same layer are connected to the same common bit line, and bit lines in different layers are connected to different common bit lines.

[0011] In some embodiments, each bit line is connected to the common bit line via a gating subcircuit, the gating subcircuit also being connected to a gating control line. Multiple gating subcircuits that are respectively connected to multiple bit lines in the same column of different layers are connected to the same gating control line. The gating subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

[0012] In some embodiments, the gating sub-circuit includes a first transistor, the first transistor including a first gate electrode, a second gate electrode, a first electrode and a second electrode, the first gate electrode and the second gate electrode of the first transistor being connected to the gating control line, the first electrode of the first transistor being connected to the bit line, and the second electrode of the first transistor being connected to the common bit line.

[0013] In some embodiments, the gating control line, which is connected to the multiple gating sub-circuits that are respectively connected to the multiple bit lines of the j-th column, is connected to the first word line corresponding to the memory cell of the j-th column.

[0014] This disclosure provides a method for accessing the memory described above, including:

[0015] During the data read / write phase, based on the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second word line corresponding to the target row, and an inactivation signal is loaded on the second word line not corresponding to the target row; an activation signal is loaded on the first word line corresponding to the target column, and an inactivation signal is loaded on the first word line not corresponding to the target column.

[0016] In some embodiments, the method further includes, during the data read / write phase, loading an enable level signal on a gating control line connected to the bit line of the target column and loading an disable level signal on a gating control line connected to the bit line of a non-target column.

[0017] In some embodiments, the activation signal loaded on the first word line corresponding to the target column and the enable level signal loaded on the gating control line connected to the bit line of the target column are the same signal, and the deactivation signal loaded on the first word line not corresponding to the target column and the disable level signal loaded on the gating control line not connected to the bit line of the target column are the same signal.

[0018] In some embodiments, the method further includes, during a pre-charge phase, loading an inactive signal on at least one of the first word line and the second word line to which the memory cell is connected, and loading an enable level signal on all the gating control lines for each memory cell.

[0019] This disclosure provides an electronic device including the memory described in any of the above embodiments.

[0020] In some embodiments, the electronic device further includes a control circuit configured to access the memory according to the memory access method described in any of the above embodiments.

[0021] This disclosure provides a memory and its access method, as well as an electronic device. The memory includes a multilayer memory array stacked along a third direction perpendicular to a substrate. The memory array includes a plurality of memory cells arranged in an array along a first direction parallel to the substrate and a second direction parallel to the substrate. The memory also includes a plurality of second word lines corresponding to rows of the multilayer memory array and a plurality of first word lines corresponding to columns of the multilayer memory array. Each second word line corresponds to the same row of the multilayer memory array, and each first word line corresponds to the same column of the multilayer memory array. Each memory cell includes a transistor, and each transistor includes a first gate electrode and a second gate electrode. The first gate electrode is connected to the first word line corresponding to the column where the memory cell is located, and the second gate electrode is connected to the second word line corresponding to the row where the memory cell is located. The solution provided by this embodiment can select memory cells at the same position in different layers using the first word lines and the second word lines. This reduces the number of word line drivers and eliminates the need for selection transistors for word line selection, thus simplifying the process, reducing costs, and simplifying the control logic.

[0022] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0025] Figure 1A A schematic diagram of the equivalent circuit of a storage unit provided by a technical solution;

[0026] Figure 1B A schematic diagram of the equivalent circuit of a memory provided as a technical solution;

[0027] Figure 2 A schematic diagram of the equivalent circuit of a memory cell provided for an exemplary embodiment;

[0028] Figure 3 A schematic diagram of the equivalent circuit of a memory provided for an exemplary embodiment;

[0029] Figure 4 A schematic diagram of the equivalent circuit of a memory provided for another exemplary embodiment. Detailed Implementation

[0030] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0032] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0033] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0034] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0035] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0036] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0037] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0038] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0039] Figure 1A This is a schematic diagram of the equivalent circuit of a memory cell provided by a technical solution. For example... Figure 1AAs shown, a memory cell may include an access transistor and a capacitor. The gate electrode of the access transistor is connected to the word line WL, the first electrode is connected to the bit line BL, the second electrode is connected to the first end of the capacitor, the second end of the capacitor is connected to the voltage terminal Vcom, and the first end of the capacitor serves as the memory node SN. Figure 1B This is a schematic diagram of a 1T1C memory. Figure 1B As shown, the memory includes a multi-layer memory array (memory arrays L1 to Lk), each layer comprising multiple memory cells (not shown) arranged in a first direction X and a second direction Y. Each memory cell is connected to a word line WL and a bit line BL. The bit line BL extends parallel to the substrate, and the word lines WL extend perpendicular to the substrate and are arranged in an array. In one approach, word lines WL in the same row along the first direction X can be connected together. In this approach, a large number of SAs (Short Arrays) are required, n*k, where n is the number of columns in the memory array and k is the number of stacked memory array layers. The number of SAs increases dramatically with the number of stacked layers. In another approach, a gating array composed of gating transistors can be arranged around the memory array to select word lines, thereby reducing word line drivers. While this approach reduces the number of word line drivers, it adds multiple gating transistors, requiring additional process steps for these transistors and increasing costs.

[0040] In this embodiment of the present disclosure, a dual-gate transistor is used in the memory cell, and the two gate electrodes of the transistor are respectively connected to different word lines. The first gate electrode of the memory cells in the same column of different layers is connected to the same first word line, and the second gate electrode of the memory cells in the same row of different layers is connected to the same second word line. The memory cells in the same position of different layers are selected through the first word line and the second word line, so that a group of memory cells can be selected without the need for a selection transistor and the number of word line drivers can be reduced.

[0041] Figure 2 This is a schematic diagram of the equivalent circuit of a memory cell provided for an exemplary embodiment. Figure 2As shown, the memory cell provided in this embodiment includes a transistor (also called an access transistor) and a capacitor Cs. The transistor includes a first gate electrode G1, a second gate electrode G2, a first electrode E1, and a second electrode E2. The first gate electrode G1 is connected to a first word line WL1, the second gate electrode G2 is connected to a second word line WL2, the first electrode E1 is connected to a bit line BL, and the second electrode E2 is connected to a first terminal of the capacitor Cs. The second terminal of the capacitor Cs is connected to a preset voltage terminal Vs, and the first terminal of the capacitor Cs serves as a memory node SN. The first word line WL1 and the second word line WL2 are connected to different signal terminals, meaning that the first word line WL1 and the second word line WL2 are independently controlled. This memory cell can be applied to a 3D stacked 1T1C memory to enable the selection of a vertical column of memory cells (including memory cells at the same position in each layer) through the first word line WL1 and the second word line WL2 without the need for a selection transistor. Compared with a single-gate 1T1C memory cell, the solution provided in this embodiment supports the realization of a 3D stacked 1T1C memory with simpler process and lower cost.

[0042] In some embodiments, the transistor may be an N-type transistor or a P-type transistor.

[0043] In some embodiments, the transistor is turned on when both the first word line WL1 and the second word line WL2 are loaded with an activation signal; the transistor is turned off when at least one of the first word line WL1 and the second word line WL2 is loaded with a deactivation signal. The activation signal and the deactivation signal vary depending on the transistor type. When the transistor is an N-type transistor, the transistor is turned on when both the first word line WL1 and the second word line WL2 are loaded with a high-level signal, and the transistor is turned off when at least one of the first word line WL1 and the second word line WL2 is loaded with a low-level signal; or, when the transistor is a P-type transistor, the transistor is turned on when both the first word line WL1 and the second word line WL2 are loaded with a low-level signal, and the transistor is turned off when at least one of the first word line WL1 and the second word line WL2 is loaded with a high-level signal.

[0044] Figure 3 A schematic diagram of a memory equivalent circuit provided for an exemplary embodiment. (e.g.) Figure 3As shown, the memory may include: a multi-layer stacked memory array (k layers), the multi-layer memory array being stacked along a third direction z. The memory may also include: multiple first sub-word lines Sub_WL1 extending along the third direction z, and multiple second sub-word lines Sub_WL2 extending along the third direction z. The multiple first sub-word lines Sub_WL1 are arrayed along a first direction x and a second direction y. The multiple second sub-word lines Sub_WL2 are arrayed along the first direction x and the second direction y. Each layer of the memory array may include multiple memory cells 100 arrayed along the first direction x and the second direction y, respectively, and multiple bit lines BL extending along the second direction y. The multiple bit lines BL of each layer are spaced apart along the first direction x. The structure of the memory cell 100 is shown in the reference diagram. Figure 2 I will not go into details.

[0045] Each layer of the storage array includes n rows and m columns of storage cells 100, and includes m bit lines BL, wherein the bit line BL of the r-th layer and j-th column is BL_j_r, where j is 1 to m and r is 1 to k.

[0046] The memory includes an n-row, m-column first sub-word line Sub_WL1, where the first sub-word line in the i-th row and j-th column is Sub_WL1_i_j, i is 1 to n, and j is 1 to m. The memory also includes an n-row, m-column second sub-word line Sub_WL2, where the second sub-word line in the i-th row and j-th column is Sub_WL2_i_j, i is 1 to n, and j is 1 to m. Specifically, the first gate electrode G1 of the memory cell C_i_j_r in the i-th row and j-th column of the r-th layer is connected to the first sub-word line Sub_WL1_i_j, the second gate electrode G2 is connected to the second sub-word line Sub_WL2_i_j, and the first electrode E1 is connected to the bit line BL_j_r.

[0047] The first direction x and the second direction y are parallel to the substrate. Figure 3 (Substrate not shown), the third direction z is perpendicular to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular. The first direction x is also called the row direction, and the second direction y is also called the column direction. The preset voltage terminal Vs may be, for example, a ground terminal.

[0048] In some embodiments, multiple first sub-word lines Sub_WL1 in the same column (i.e., multiple first sub-word lines Sub_WL1 distributed along the second direction Y) are connected to form a first word line WL1. Storage cells in the same column of different layers correspond to one first word line WL1. That is, n first sub-word lines Sub_WL1_1_j to Sub_WL1_n_j in the j-th column are connected to form the j-th first word line WL1_j, where j is 1 to m. For example, n first sub-word lines Sub_WL1_1_1 to Sub_WL1_n_1 in the 1st column are connected to form the 1st first word line WL1_1, and n first sub-word lines Sub_WL1_1_m to Sub_WL1_n_m in the m-th column are connected to form the m-th first word line WL1_m. Each first word line WL1_j is connected to a first word line driver. Different first word lines WL1_j are connected to different first word line drivers. Multiple first word line drivers connected to multiple first word lines WL1_j can be located on the same side of the memory array, but this embodiment is not limited to this, and multiple first word line drivers can be located on different sides of the memory array.

[0049] In some embodiments, multiple first sub-word lines Sub_WL1 in the same column can be connected by a connecting line extending along a second direction Y on the side of the memory array away from the substrate. However, the embodiments disclosed herein are not limited to this, and multiple first sub-word lines Sub_WL1 in the same column can be connected in other ways.

[0050] In some embodiments, multiple second sub-word lines Sub_WL2 in the same row are connected to form a single second word line WL2. Storage cells in the same row of different layers correspond to a single second word line WL2. That is, m second sub-word lines Sub_WL2_i_1 to Sub_WL2_i_m in the i-th row are connected to form the i-th second word line WL2_i, where i is 1 to n. The m second sub-word lines Sub_WL2_1_1 to Sub_WL2_1_m in the first row are connected to form the first second word line WL2_1, and the m second sub-word lines Sub_WL2_n_1 to Sub_WL2_n_m in the n-th row are connected to form the n-th second word line WL2_n. Each second word line WL2_i is connected to a second word line driver. Multiple second word line drivers connected to multiple second word lines WL2_i can be located on the same side of the storage array, but this embodiment is not limited to this; multiple second word line drivers can be located on different sides of the storage array.

[0051] In some embodiments, multiple second sub-word lines Sub_WL2 in a row can be connected by a connection line extending along a first direction X on the side of the memory array away from the substrate. However, the embodiments disclosed herein are not limited to this, and multiple second sub-word lines Sub_WL2 in a row can be connected in other ways.

[0052] The memory provided in this embodiment can select a vertical column of memory cells by activating a first word line and a second word line. For example, if the target row is row p and the target column is column q, an activation signal can be applied to the second word line WL2_p and the first word line WL1_q to select k memory cells in row p and column q from layer 1 to layer k. The solution provided in this embodiment can select a vertical column of memory cells without setting up selection transistors for the word lines. Compared to solutions that set up selection transistors for word lines, this eliminates the need for additional manufacturing steps for the selection transistors, and the number of word line drivers is small: m first word line drivers and n second word line drivers. Furthermore, the number of word line drivers remains constant as the number of stacked layers increases. Additionally, the circuit control logic is simple.

[0053] In some embodiments, the memory may further include multiple common bit lines (CBLs). Multiple bit lines (BLs) on the same layer can be connected to the same common bit line (CBL), while bit lines (BLs) on different layers are connected to different common bit lines (CBLs). For example, multiple bit lines (BLs) on the first layer are connected to the first common bit line (CBL1), multiple bit lines (BLs) on the second layer are connected to the second common bit line (CBL2), and multiple bit lines (BLs) on the k-th layer are connected to the k-th common bit line (CBLk). Each common bit line (CBL) is connected to a sense amplifier (SA). Compared to a scheme where each bit line (BL) is connected to a sense amplifier (SA), the solution provided in this embodiment can significantly reduce the number of sense amplifiers (SAs) by using common bit lines (CBLs). Adjacent memory arrays can share the same SA. However, this disclosure is not limited to this; each bit line (BL) can be connected to a sense amplifier (SA).

[0054] In some embodiments, each bit line BL can be connected to the common bit line CBL via a gating sub-circuit 10. The gating sub-circuit 10 can also be connected to a gating control line, and is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the gating control line (i.e., to make the bit line BL and the common bit line CBL electrically connected, or disconnected). That is, under the control of the gating control line, the signal of the common bit line CBL is loaded or not loaded onto the bit line BL. The solution provided in this embodiment, by setting the gating sub-circuit, can reduce the capacitive reactance of CBL, reduce power consumption, and improve read speed. However, this embodiment is not limited to this; in another exemplary embodiment, the gating sub-circuit 10 may not be provided.

[0055] In some embodiments, the gating sub-circuits 10 connected to the bit lines BL of the same column in different layers can be connected to the same gating control line, and the gating sub-circuits connected to the bit lines BL of different columns in different layers are connected to different gating control lines, with m columns of bit lines BL respectively connected to m different gating control lines. For example, Figure 3As shown, the gating sub-circuits 10 connected to the bit lines BL in the first column are all connected to the first gating control line S_1, the gating sub-circuits 10 connected to the bit lines BL in the second column are all connected to the second gating control line S_2, and so on, with the gating sub-circuits 10 connected to the bit lines BL in the m-th column being connected to the m-th gating control line S_m. Therefore, a bit line BL can be selected using the common bit line CBL and the gating control lines. For example, if the r-th common bit line CBLr is loaded with an activation signal (the remaining common bit lines are loaded with inactive signals), and the j-th gating control line S_j selects the corresponding gating sub-circuit 10 (the remaining gating control lines do not select the corresponding gating sub-circuit 10), then the bit line BL_j_r in the r-th layer and j-th column is loaded with an activation signal. Alternatively, bit lines BL in the same column of different layers can be selected using the gating control lines.

[0056] In some embodiments, only the same column bit line BL of different layers can be selected at the same time, which can reduce the capacitive load of SA and reduce the capacitance of memory cells.

[0057] In some embodiments, the gating sub-circuit 10 may include a first transistor T1, which may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 is connected to the gating control line, the first electrode is connected to the bit line BL, and the second electrode is connected to the common bit line CBL. The structure of the gating sub-circuit 10 described in this embodiment is merely an example and may be other circuits capable of implementing gating.

[0058] In another embodiment, such as Figure 4 As shown, the first transistor T1 can be a dual-gate transistor, meaning that the first transistor T1 may include a first gate electrode, a second gate electrode, a first electrode, and a second electrode. The first and second gate electrodes of the first transistor T1 are connected to the gating control line. The first electrode of the first transistor T1 is connected to the bit line BL, and the second electrode is connected to the common bit line CBL. In this embodiment, the first transistor T1 and the access transistor can be manufactured in a single process, i.e., the first transistor T1 is manufactured simultaneously with the access transistor, thereby simplifying the process and reducing costs.

[0059] In some embodiments, the first transistor T1 is, for example, an N-type transistor, but this disclosure is not limited thereto; the first transistor T1 may be a P-type transistor.

[0060] In some embodiments, when the first word line WL1_j corresponding to the memory cell in the j-th column of different layers is activated, the selection control line S_j connected to the selection sub-circuit 10 connected to the bit line BL of the j-th column is activated to connect the selection sub-circuit 10 connected to the bit line BL of the j-th column. When the second word line WL2_i corresponding to the i-th row is activated, the memory cell in the i-th row and j-th column of different layers is activated, and the memory cell in the i-th row and j-th column can be accessed (read or write) through the bit line BL of the j-th column.

[0061] In some embodiments, the first word line WL1_j can be connected to the gating control line S_j connected to the gating sub-circuit 10 connected to the bit line BL of the j-th column, where j is 1 to m. This means that the same signal driver can be used to load the same signal to both the first word line WL1_j and the gating control line S_j; that is, the activation signal and the turn-on level signal of the gating sub-circuit use the same signal. The solution provided in this embodiment can reduce the number of control lines, reduce the control circuitry that generates control signals, reduce the device footprint, and simplify the control logic.

[0062] This disclosure provides a memory access method, applied to the memory described in any of the above embodiments, the access method may include:

[0063] During the data read / write phase, based on the target row and target column where the storage cell to be operated is located, an activation signal is loaded on the second word line corresponding to the target row, and an inactivation signal is loaded on the second word line corresponding to a non-target row; an activation signal is loaded on the first word line corresponding to the target column, and an inactivation signal is loaded on the first word line corresponding to a non-target column (at this time, only the first gate electrode and the second gate electrode of the transistor of the storage cell of the target row and target column of each layer are loaded with activation signals, so that the transistor of the storage cell of the target row and target column of each layer can be turned on).

[0064] In some embodiments, the access method may further include: loading an enable level signal on a gating control line connected to the bit line of the target column (so that the gating sub-circuit connected to the bit line of the target column is in an on state), and loading an disable level signal on a gating control line connected to a bit line of a non-target column (so that the gating sub-circuit connected to the bit line of the non-target column is in a disable state).

[0065] This embodiment provides a memory access method that can access a vertical column of memory cells through a first word line, a second word line, and a strobe control line, with simple control logic.

[0066] The turn-on level signal is the signal that enables the corresponding gating sub-circuit to be in the connected state, and the turn-off level signal is the signal that enables the corresponding gating sub-circuit to be in the off state.

[0067] In some embodiments, it may further include:

[0068] During the pre-charging phase, inactive signals are applied to all second word lines, while active or inactive signals are applied to all first word lines. Enable level signals are applied to all the gating control lines. The solution provided in this embodiment can turn off all access transistors, enable all gating sub-circuits, and pre-charge the bit lines.

[0069] In some embodiments, the activation signal loaded on the first word line corresponding to the target column and the enable level signal loaded on the gating control line connected to the bit line of the target column are the same signal, and the deactivation signal loaded on the first word line not corresponding to the target column and the disable level signal loaded on the gating control line not connected to the bit line of the target column are the same signal.

[0070] That is, the gating control line connected to the bit line of the target column and the first word line corresponding to the target column can be controlled by the same signal, which reduces the number of control signals, simplifies control, and reduces signal drivers, thus reducing costs and device area. At this time, the gating control line S_j connected to the gating sub-circuit 10 connected to the first word line WL1_j and the bit line BL of the j-th column can be connected together, where j is from 1 to m, and m is the number of columns of memory cells contained in each layer of the memory array.

[0071] The working process of the memory is illustrated below through an embodiment. Figure 2 Taking the illustrated memory as an example, in this embodiment, the memory cell 100 has a 1T1C structure, the access transistor is an N-type MOS transistor, the first transistor T1 is an N-type MOS transistor, the selection control line S_j is connected to the first word line WL1_j, where j is 1 to m, and the common bit line CBL can also be connected to a precharge circuit. The memory's operating stages can include a precharge stage, a data read stage, and a data write-back stage, wherein:

[0072] During the precharge phase, low-level signals are applied to the second word lines WL2_1 to WL2_n, and these low-level signals are applied to the second sub-word line Sub_WL2. High-level signals are applied to the first word lines WL1_1 to WL1_m (i.e., high-level signals are applied to the gating control line S_j). At this time, the gating sub-circuit is turned on, all memory cell access transistors are turned off, the precharge sub-circuit is turned on, and a precharge voltage of 1 / 2VDD is applied to each common bit line CBL. Each common bit line CBL applies the precharge voltage to the bit line BL connected to the same layer.

[0073] During the data reading phase, the pre-charge electronic circuit is turned off. Taking the reading of data from storage cell 100 in row p and column q as an example, among the first word lines WL1_1 to WL1_m, the first word line WL1_q corresponding to column q is loaded with a high-level signal, and the remaining first word lines WL1_j (where j is 1 to m and j ≠ q) are loaded with a low-level signal. Among the second word lines WL2_1 to WL2_n, the second word line WL2_p corresponding to row p is loaded with a high-level signal, and the remaining WL2_i (where i is 1 to n and i ≠ p) are loaded with a low-level signal, thus the p-th row... The access transistor of the memory cell 100 in the qth column is turned on, the access transistors of the other memory cells 100 are turned off, the gating sub-circuit 10 connected to the bit line of the qth column is turned on, the common bit lines CBL1 to CBLk are respectively connected to the k bit lines of the qth column, and the charge is shared with the storage nodes of the k memory cells 100 in the pth row and qth column of the 1st to kth layers, respectively. The sensing amplifiers connected to CBL1 to CBLk respectively sense the voltage of CBL1 to CBLk and determine the data stored in the memory cell 100 in the pth row and qth column.

[0074] During the data write-back stage, in the first word lines WL1_1 to WL1_m, WL1_q is loaded with a high-level signal, and the remaining WL1_j (where j is from 1 to m and j≠q) are loaded with a low-level signal. In the second word lines WL2_1 to WL2_n, WL2_p is loaded with a high-level signal, and the remaining WL2_i (where i is from 1 to n and i≠p) are loaded with a low-level signal. The common bit lines CBL1 to CBLk are connected to the k bit lines of the qth column, respectively, and share charge with the storage nodes of the k storage cells 100 in the pth row and qth column of the 1st to kth layers, thereby realizing the data write-back.

[0075] The solution provided in this embodiment does not require the use of a gating transistor to select memory cells. A vertical column of memory cells can be selected using only the first word line and the second word line. The structure is simple, the control logic is simple, and the same control signal is used to control the gating control line and the second word line of the same column, which reduces the number of control signal lines, reduces the required control circuit, and makes the control logic simpler.

[0076] This disclosure also provides an electronic device, including the memory of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0077] In some embodiments, the electronic device may further include a control circuit configured to access the memory according to any of the access methods described above. The control circuit may include drivers that generate control signals to a first word line, a second word line, a gating control line, etc. The control circuit, together with the SA (Search Engine Controller), implements access to the memory.

[0078] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A memory, characterized in that, include: A multilayer memory array stacked along a third direction perpendicular to the substrate, the memory array comprising a plurality of memory cells arrayed along a first direction parallel to the substrate and a second direction parallel to the substrate, the memory further comprising a plurality of second word lines corresponding to rows of the multilayer memory array, and a plurality of first word lines corresponding to columns of the multilayer memory array, each second word line corresponding to the same row of the multilayer memory array, and each first word line corresponding to the same column of the multilayer memory array; The memory cell includes a transistor, the transistor including a first gate electrode and a second gate electrode, the first gate electrode being directly connected to the first word line corresponding to the column where the memory cell is located, and the second gate electrode being directly connected to the second word line corresponding to the row where the memory cell is located.

2. The memory according to claim 1, characterized in that, Each layer of the memory array also includes multiple first sub-word lines extending along the third direction. The first gate electrodes of memory cells in the same row and column of different layers are connected to one first sub-word line. The first gate electrodes of different memory cells in the same layer are connected to different first sub-word lines. Multiple first sub-word lines in the same column are connected to form one first word line.

3. The memory according to claim 1, characterized in that, Each layer of the memory array also includes multiple second sub-word lines extending along the third direction. The second gate electrodes of memory cells in the same row and column of different layers are connected to one second sub-word line, and the second gate electrodes of different memory cells in the same layer are connected to different second sub-word lines. Multiple second sub-word lines in the same row are connected to form one second sub-word line.

4. The memory according to claim 2, characterized in that, Each layer of the memory array further includes: multiple bit lines extending along the second direction; the memory further includes: multiple common bit lines; a bit line connects the memory cells in the same column of the layer where the bit line is located, bit lines in the same layer are connected to the same common bit line, and bit lines in different layers are connected to different common bit lines.

5. The memory according to claim 4, characterized in that, Each bit line is connected to the common bit line via a gating subcircuit, which is also connected to a gating control line. Multiple gating subcircuits that are connected to multiple bit lines in the same column of different layers are connected to the same gating control line. The gating subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

6. The memory according to claim 5, characterized in that, The gating sub-circuit includes a first transistor, which includes a first gate electrode, a second gate electrode, a first electrode, and a second electrode. The first gate electrode and the second gate electrode of the first transistor are connected to the gating control line. The first electrode of the first transistor is connected to the bit line, and the second electrode of the first transistor is connected to the common bit line.

7. The memory according to claim 5, characterized in that, The gating control line, which is connected to multiple gating sub-circuits that are respectively connected to multiple bit lines of column j, is connected to the first word line corresponding to the memory cell of column j.

8. A method for accessing a memory as described in any one of claims 1 to 7, characterized in that, include: During the data read / write phase, based on the target row and target column where the storage unit to be operated is located, an activation signal is loaded on the second word line corresponding to the target row, and an inactivation signal is loaded on the second word line not corresponding to the target row. An activation signal is applied to the first character line corresponding to the target column, and an inactivation signal is applied to the first character line not corresponding to the target column.

9. The memory access method according to claim 8, characterized in that, The memory is the memory as described in any one of claims 5 to 7, and the method further includes, during the data read / write phase, loading an enable level signal on the gating control line connected to the bit line of the target column, and loading an disable level signal on the gating control line connected to the bit line of a non-target column.

10. The memory access method according to claim 9, characterized in that, The activation signal loaded on the first word line corresponding to the target column and the turn-on level signal loaded on the gating control line connected to the bit line of the target column are the same signal. The deactivation signal loaded on the first word line not corresponding to the target column and the turn-off level signal loaded on the gating control line not connected to the bit line of the target column are the same signal.

11. The memory access method according to claim 9, characterized in that, The method further includes, during the pre-charging phase, loading an inactive signal on at least one of the first word line and the second word line connected to each memory cell, and loading an enable level signal on all the gating control lines.

12. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 7.

13. The electronic device according to claim 12, characterized in that, The electronic device further includes a control circuit configured to access the memory according to the memory access method according to any one of claims 8 to 11.

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