Semiconductor memory device

Abstract

There is provided a semiconductor memory device including: a substrate including a cell region and a peripheral region; a peripheral gate structure disposed on the substrate and in the peripheral region of the substrate; a peripheral wiring line disposed on the peripheral gate structure and connected to the substrate; a peripheral etch stop film disposed on the peripheral wiring line; an element isolation film defining an active region in the cell region in the substrate; a memory pad connected to an active region defined in the cell region; a cell etch stop film disposed on the memory pad; and a capacitor structure extending through the cell etch stop film to contact the memory pad, in which the peripheral etch stop film and the cell etch stop film respectively include materials different from each other.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device. Background Art

[0002] Semiconductor memory devices have an increasingly higher degree of integration. Therefore, in order to implement more semiconductor elements in the same area, each circuit pattern is becoming smaller and smaller. In other words, as the degree of integration of semiconductor memory devices increases, the design rules of the components of semiconductor memory devices decrease.

[0003] In highly scaled semiconductor memory devices, the process of forming a plurality of wiring lines and a plurality of buried contacts (BCs) interposed between the lines is becoming increasingly complex and difficult. Summary of the invention

[0004] A technical object of the present disclosure is to provide a semiconductor memory device with improved reliability and performance.

[0005] The purpose according to the present disclosure is not limited to the above-mentioned purpose. In addition to those mentioned above, other purposes and advantages according to the present disclosure can be understood from the following description and more clearly understood from the embodiments according to the present disclosure. In addition, it will be easily understood that the purposes and advantages according to the present disclosure can be achieved by the features disclosed in the claims and their combinations.

[0006] According to some example embodiments of the present invention, there is provided a semiconductor memory device, comprising: a substrate including a cell region and a peripheral region; a peripheral gate structure on the substrate and in the peripheral region; a peripheral wiring line on the peripheral gate structure and connected to the substrate; a peripheral etch stop film disposed on the peripheral wiring line; an element isolation film defining an active region in the cell region; a storage pad connected to the active region defined in the cell region; a cell etch stop film disposed on the storage pad; and a capacitor structure extending through the cell etch stop film to contact the storage pad, wherein the peripheral etch stop film and the cell etch stop film comprise different materials from each other.

[0007] According to some example embodiments of the present invention, there is provided a semiconductor memory device, comprising: a substrate including a cell region, a peripheral region, and an interface region between the cell region and the peripheral region; a peripheral gate structure disposed on the substrate and in the peripheral region; a peripheral wiring line disposed on the peripheral gate structure; an element isolation film defining an active region in the cell region in the substrate; a storage pad disposed on the active region defined in the cell region; a peripheral etch stop film disposed on the peripheral wiring line and not on the storage pad; a cell etch stop film disposed on the storage pad and not on the peripheral gate structure; and a capacitor structure extending through the cell etch stop film to contact the storage pad.

[0008] According to some example embodiments of the inventive concept, a semiconductor memory device is provided, which includes: a substrate including a cell area, a peripheral area, and an interface area between the cell area and the peripheral area; a cell area isolation film, which defines the cell area in the substrate and in the interface area; a bit line structure, which is arranged on the substrate and in the cell area, wherein the bit line structure includes a cell conductive line and a cell line cap film arranged on the cell conductive line; a cell gate electrode, which is arranged in the substrate and in the cell area and crosses the cell conductive line; an element isolation film, which defines an active area in the substrate and in the cell area; a storage pad, which is arranged on a side surface of the bit line structure and connected to the active area; a cell etch stop film, which is arranged on the storage pad; a capacitor structure, which includes a lower electrode extending through the cell etch stop film to contact the storage pad, a capacitor dielectric film arranged on the lower electrode, and an upper electrode arranged on the capacitor dielectric film; a peripheral gate structure, which is arranged on the substrate and in the peripheral area; a peripheral wiring line, which is arranged on the peripheral gate structure and connected to the substrate; and a peripheral etch stop film, which is arranged on the peripheral wiring line, wherein a side end of the cell etch stop film is arranged on the cell area isolation film arranged in the interface area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is a schematic layout diagram of a semiconductor memory device according to an example embodiment;

[0011] Figure 2 yes Figure 1 A schematic layout diagram of region R1 in FIG.

[0012] Figure 3 yes Figure 1 A schematic layout diagram of region R2 in FIG.

[0013] Figure 4 It is along Figure 1 An illustrative cross-sectional view taken along line AA in FIG.

[0014] Figure 5 It is along Figure 3 A cross-sectional view cut along line BB in FIG.

[0015] Figure 6 It is along Figure 3 A cross-sectional view cut along line CC in FIG.

[0016] Figures 7 to 10 is a diagram for explaining a semiconductor memory device according to an example embodiment;

[0017] Fig.11is a layout diagram for explaining a semiconductor memory device according to an example embodiment;

[0018] Fig.12 is a perspective view for explaining a semiconductor memory device according to an example embodiment;

[0019] Fig.13 It is along Fig.11 A cross-sectional view cut along lines DD and EE;

[0020] Fig.14 is a layout diagram for explaining a semiconductor memory device according to an example embodiment;

[0021] Fig.15 is a perspective view for explaining a semiconductor memory device according to an example embodiment; and

[0022] Figures 16 to 20 are diagrams of intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor memory device according to example embodiments. DETAILED DESCRIPTION

[0023] When referring to orientation, layout, position, shape, size, amount or other measurement, terms such as "same", "equal", "planar" or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, amount or other measurement, but are intended to cover nearly the same orientation, layout, position, shape, size, amount or other measurement within acceptable deviations that may occur, for example, due to manufacturing processes. The term "substantially" may be used here to emphasize this meaning, unless the context or other statements indicate otherwise.

[0024] It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it may be directly connected or coupled to or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “contacting” or “in contact with” another element (or any form of the word “contacting” is used), there are no intervening elements at the point of contact.

[0025] As used herein, the term “dummy” is used to refer to a component that has the same or similar structure and shape as other components but does not have a substantial function and exists in a device only as a pattern.

[0026] Like reference numerals refer to like elements throughout.

[0027] Figure 1 is a schematic layout diagram of a semiconductor memory device according to example embodiments. Figure 2 yes Figure 1 Schematic layout diagram of area R1 in FIG. Figure 3 yes Figure 1 Schematic layout diagram of area R2 in FIG. Figure 4 It is along Figure 1 An illustrative cross-sectional view taken along line AA in FIG. Figure 5 It is along Figure 3 Cross-sectional view cut along line BB. Figure 6 It is along Figure 3 For reference, Figure 4 It may be an illustrative cross-sectional view of a transistor formation region in the peripheral region.

[0028] Reference Figures 1 to 3 , a semiconductor memory device according to some embodiments may include a cell region CR, an interface region IR, and a peripheral region PR.

[0029] The cell region CR may be a memory cell region of a semiconductor memory device. The cell region CR may include a memory cell of a volatile memory device or a memory cell of a nonvolatile memory device. The peripheral region PR may include a peripheral circuit necessary for operating the memory cell located in the cell region CR. For example, the cell region CR may be a memory cell region of a DRAM (dynamic random access memory), and the peripheral region PR may be a core region or a peripheral circuit region of the DRAM.

[0030] The interface region IR may be disposed between the cell region CR and the peripheral region PR. The interface region IR may be formed along the periphery of the cell region CR. The interface region IR may surround the cell region CR. The peripheral region PR may be defined as a region around the cell region CR. For example, the peripheral region PR may surround the interface region IR and the cell region CR.

[0031] The cell region CR may include a plurality of cell active regions ACT. The cell active regions ACT may be formed on a substrate (eg, Figure 4 The cell element isolation film (eg, Figure 5 and Figure 6 As the design rule of semiconductor memory devices decreases, the cell active region ACT may be as follows. Figure 2 The cell active area ACT may be shown to have a strip shape extending in a diagonal or oblique line. For example, the cell active area ACT may extend longitudinally in the third direction D3.

[0032] Each of the plurality of gate electrodes may extend longitudinally in the first direction D1 and extend across the cell active area ACT. The plurality of gate electrodes may extend parallel to each other. Each of the plurality of gate electrodes may be embodied as, for example, each of the plurality of word lines WL. The word lines WL may extend parallel to each other. The word lines WL may be spaced apart from each other at equal intervals. The width of the word lines WL or the spacing between the word lines WL may be determined according to design rules.

[0033] Two word lines WL adjacent to each other and extending longitudinally in the first direction D1 may allow each cell active area ACT to be divided into three parts. The cell active area ACT may include a storage connection area and a bit line connection area. The bit line connection area may be located at the middle part of the cell active area ACT, and the storage connection area may be located at the end of the cell active area ACT.

[0034] A plurality of bit lines BL extending longitudinally in a second direction D2 perpendicular to the extension direction of the word line WL may be provided on the word line WL. The plurality of bit lines BL may extend parallel to each other. The bit lines BL may be arranged to be spaced apart from each other by the same (e.g., equal) spacing. The width of the bit line BL or the spacing between the bit lines BL may be determined according to a design rule.

[0035] The boundary bit line BL_IF may extend longitudinally in the second direction D2 and extend in parallel with the bit line BL. At least a portion of the boundary bit line BL_IF may be arranged to overlap the interface region IR in the fourth direction D4. For example, the boundary bit line BL_IF may extend longitudinally in the second direction D2 while overlapping both the cell region CR and the interface region IR. Unlike what is shown, the semiconductor memory device according to some embodiments may not include the boundary bit line BL_IF.

[0036] The boundary peripheral gate PR_ST1 may extend longitudinally in the second direction D2 and extend in parallel with the boundary bit line BL_IF. The boundary peripheral gate PR_ST1 may be disposed at a boundary between the interface region IR and the peripheral region PR. The boundary peripheral gate PR_ST1 may overlap the peripheral region PR. Different from what is shown, in a semiconductor memory device according to some embodiments, the boundary peripheral gate PR_ST1 may extend longitudinally in the first direction D1. In addition, the semiconductor memory device according to some embodiments may not include the boundary peripheral gate PR_ST1.

[0037] A semiconductor memory device according to some implementations may include various contact arrangements formed on a cell active area ACT. The various contact arrangements may include, for example, a direct contact DC, a buried contact BC, a landing pad LP, and the like.

[0038] In this regard, the direct contact DC may refer to a contact that electrically connects the cell active area ACT to the bit line BL. The buried contact BC may refer to a contact that connects the cell active area ACT to the lower electrode of the capacitor (eg, Figure 5 and Figure 6 In terms of the arrangement structure, the contact area between the buried contact BC and the cell active area ACT may be small. Therefore, a conductive landing pad LP may be introduced to expand the contact area between the cell active area ACT and the buried contact BC and expand the contact area between the buried contact BC and the lower electrode of the capacitor (e.g., Figure 5 and Figure 6 The contact area between the first lower electrode 191).

[0039] The landing pad LP may be disposed between the cell active region ACT and the buried contact BC, and may be disposed between the buried contact BC and the lower electrode of the capacitor (eg, Figure 5 and Figure 6 In the semiconductor memory device according to some implementations, a landing pad LP may be disposed between the buried contact BC and the lower electrode of the capacitor. Introducing the landing pad LP to expand the contact area may reduce the contact resistance between the cell active area ACT and the lower electrode of the capacitor.

[0040] The direct contact DC may be connected to the bit line connection region. The buried contact BC may be connected to the storage connection region. Since the buried contact BC is disposed in each of the two opposite ends of the cell active region ACT, the landing pad LP may be disposed adjacent to each of the two opposite ends of the cell active region ACT and partially overlap with the buried contact BC. In other words, the buried contact BC may be formed to contact the cell active region ACT and the cell element isolation film (e.g., Figure 5 and Figure 6 Overlapping the unit element isolation film 105).

[0041] The word line WL may be formed as a structure buried in the substrate 100. The word line WL may extend across the cell active area ACT between the direct contacts DC or between the buried contacts BC. As shown, two word lines WL may extend through one cell active area ACT. Since the cell active area ACT extends along the third direction D3, the extension direction of the word line WL may have an angle less than 90 degrees relative to the extension direction of the cell active area ACT.

[0042] The direct contact DC and the buried contact BC may be arranged in a symmetrical manner. Therefore, the direct contact DC and the buried contact BC may be arranged in a straight line along the first direction D1 and the second direction D2. Unlike the direct contact DC and the buried contact BC, the landing pad LP may be arranged in a zigzag manner in the second direction D2 in which the bit line BL extends. In addition, the landing pad LP may overlap with the same portion of the side surface of each bit line BL in the first direction D1 in which the word line WL extends. For example, each landing pad LP in the first line along the first direction D1 may overlap with the left side surface of the corresponding bit line BL, and each landing pad LP in the second line along the first direction D1 may overlap with the right side surface of the corresponding bit line BL.

[0043] Reference Figures 1 to 6 According to some implementations, a semiconductor memory device may include a substrate 100, a plurality of unit gate structures 110, a plurality of bit line structures 140ST, a plurality of storage pads 160, a capacitor structure 190, a peripheral gate structure 240ST, a peripheral wiring line 265, a peripheral etch stop film 296, and a unit etch stop film 297.

[0044] The substrate 100 may include a cell region CR, an interface region IR, and a peripheral region PR. The substrate 100 may be a silicon substrate or may be made of SOI (silicon on insulator). Alternatively, the substrate 100 may include silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the present disclosure is not limited thereto.

[0045] A plurality of cell gate structures 110, a plurality of bit line structures 140ST, a plurality of memory pads 160, and a capacitor structure 190 may be disposed in the cell region CR. A peripheral gate structure 240ST and a peripheral wiring line 265 may be disposed in the peripheral region PR.

[0046] The cell element isolation film 105 may be formed in the substrate 100 and in the cell region CR. The cell element isolation film 105 may have an STI (shallow trench isolation) structure having excellent element isolation capability. The cell element isolation film 105 may define a cell active region ACT within the cell region CR. Each cell active region ACT defined by the cell element isolation film 105 may be as follows: Figure 2 The cell active region ACT may have a diagonally extending shape to have an angle less than 90 degrees relative to an extending direction of a word line WL horizontally flush with the cell element isolation film 105. In addition, the cell active region ACT may have a diagonally extending shape to have an angle less than 90 degrees relative to an extending direction of a bit line BL formed on the cell element isolation film 105.

[0047] In the substrate 100 and in the interface region IR, a cell region isolation film 22 having an STI structure may be formed. The cell region CR may be defined by the cell region isolation film 22.

[0048] Each of the cell element isolation film 105 and the cell region isolation film 22 may include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. However, the present disclosure is not limited thereto. Figure 5 and Figure 6 , each of the cell element isolation film 105 and the cell region isolation film 22 is shown as being formed as a single insulating film. However, this is only for ease of explanation, and the present disclosure is not limited thereto. Depending on the width of each of the cell element isolation film 105 and the cell region isolation film 22, each of the cell element isolation film 105 and the cell region isolation film 22 may be formed as a single insulating film, or may be formed as a stack of multiple insulating films.

[0049] exist Figure 5 , the upper surface of the cell element isolation film 105, the upper surface of the substrate 100, and the upper surface of the cell area isolation film 22 are shown to be horizontally flush with each other. For example, the upper surfaces of the cell element isolation film 105, the substrate 100, and the cell area isolation film 22 can be coplanar with each other. However, this is only for ease of explanation, and the present disclosure is not limited to this. In the following, the upper surface is defined based on the fourth direction D4. The fourth direction D4 is a vertical direction perpendicular to the upper surface of the substrate 100.

[0050] The cell gate structure 110 may be formed in the substrate 100 and the cell element isolation film 105. The cell gate structure 110 may be formed across the cell element isolation film 105 and the cell active area ACT defined by the cell element isolation film 105. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate capping pattern 113, and a cell gate capping conductive film 114, and the cell gate trench 115 is formed in the substrate 100 and the cell element isolation film 105. In this regard, the cell gate electrode 112 may serve as a word line WL. Different from what is shown, in some embodiments, the cell gate structure 110 may not include the cell gate capping conductive film 114.

[0051] The cell gate insulating film 111 may extend along the sidewall and the lower surface of the cell gate trench 115. The cell gate insulating film 111 may extend along the outline of at least a portion of the cell gate trench 115. The cell gate insulating film 111 may be formed of, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide, or include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material can be formed of, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof, or include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof.

[0052] The cell gate electrode 112 may be formed on the cell gate insulating film 111. The cell gate electrode 112 may contact the cell gate insulating film 111. The cell gate electrode 112 may fill a portion of the cell gate trench 115. The cell gate capping conductive film 114 may extend along an upper surface of the cell gate electrode 112. For example, the cell gate capping conductive film 114 may contact an upper surface of the cell gate electrode 112 and a side surface of the cell gate insulating film 111.

[0053] The cell gate electrode 112 may include at least one of a metal, a metal alloy, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The cell gate electrode 112 may be made of, for example, at least one of TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrOx, RuOx, and combinations thereof. The cell gate cap conductive film 114 may be formed of, for example, polysilicon or polysilicon-germanium, or include, for example, polysilicon or polysilicon-germanium. However, the present disclosure is not limited thereto. The cell gate cap conductive film 114 may be formed of, for example, polysilicon or polysilicon-germanium, or include, for example, polysilicon or polysilicon-germanium. However, the present disclosure is not limited thereto.

[0054] The cell gate capping pattern 113 may be disposed on the cell gate electrode 112 and the cell gate capping conductive film 114. The cell gate capping pattern 113 may contact the upper surface of the cell gate capping conductive film 114 and the side surface of the cell gate insulating film 111. The cell gate capping pattern 113 may fill the remaining portion of the cell gate trench 115 except for the cell gate insulating film 111, the cell gate electrode 112, and the cell gate capping conductive film 114. The cell gate insulating film 111 is shown to extend along the sidewall of the cell gate capping pattern 113. However, the present disclosure is not limited thereto. The cell gate capping pattern 113 may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof, or including, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN) and at least one of a combination thereof.

[0055] Although not shown, an impurity doped region may be formed on at least one side of the cell gate structure 110. The impurity doped region may function as a source / drain region of the transistor.

[0056] The bit line structure 140ST may include a cell conductive line 140 and a cell line cap film 144. The cell conductive line 140 may be formed on the substrate 100 including the cell gate structure 110 and on the cell element isolation film 105 formed in the substrate 100. The cell conductive line 140 may cross the cell element isolation film 105 and the cell active region ACT defined by the cell element isolation film 105. The cell conductive line 140 may be formed to cross the cell gate structure 110. In this regard, the cell conductive line 140 may serve as a bit line BL.

[0057] The unit conductive line 140 may be embodied as a multi-film. The unit conductive line 140 may include, for example, a first unit conductive film 141, a second unit conductive film 142, and a third unit conductive film 143. The first to third unit conductive films 141, 142, and 143 may be sequentially stacked on the substrate 100 and the unit element isolation film 105. Although the unit conductive line 140 is shown as being composed of three films, the present disclosure is not limited thereto.

[0058] Each of the first to third unit conductive films 141, 142, and 143 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a metal, and a metal alloy. For example, the first unit conductive film 141 may include a doped semiconductor material, the second unit conductive film 142 may include at least one of a conductive silicide compound and a conductive metal nitride, and the third unit conductive film 143 may include at least one of a metal and a metal alloy. However, the present disclosure is not limited thereto.

[0059] The bit line contact 146 may be formed between the cell conductive line 140 and the substrate 100. That is, the cell conductive line 140 may be formed on the bit line contact 146. For example, the bit line contact 146 may be formed at a point where the cell conductive line 140 crosses the central portion of the cell active area ACT having an elongated island shape. The bit line contact 146 may be formed between the bit line connection region of the cell active area ACT and the cell conductive line 140.

[0060] The bit line contact 146 may electrically connect the cell conductive line 140 and the substrate 100 to each other. In this regard, the bit line contact 146 may serve as a direct contact DC. The bit line contact 146 may be formed of, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal, or include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

[0061] exist Figure 5 In the embodiment, in a region where the cell conductive line 140 overlaps with an upper surface of the bit line contact 146, the cell conductive line 140 may include a second cell conductive film 142 and a third cell conductive film 143. In a region where the cell conductive line 140 does not overlap with an upper surface of the bit line contact 146, the cell conductive line 140 may include first to third cell conductive films 141, 142, and 143.

[0062] exist Figure 5 , it is shown that the bit line contact 146 is not disposed between the cell conductive line 140 closest to the cell region isolation film 22 and the substrate 100. However, the present disclosure is not limited thereto. Alternatively, the bit line contact 146 may be disposed between the cell conductive line 140 closest to the cell region isolation film 22 and the substrate 100.

[0063] The cell line cap film 144 may be disposed on the cell conductive line 140. The cell line cap film 144 may contact the upper surface of the cell conductive line 140. The cell line cap film 144 may extend in the second direction D2 and extend along the upper surface of the cell conductive line 140. In this regard, the cell line cap film 144 may be formed of, for example, at least one of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon oxycarbon nitride, or include, for example, at least one of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon oxycarbon nitride. In a semiconductor memory device according to some implementations, the cell line cap film 144 may include, for example, a silicon nitride film. The cell line cap film 144 is shown as a single film. However, the present disclosure is not limited thereto. Different from what is shown, in one example, the cell line cap film 144 may have a double-layer structure. In another example, the cell line cap film 144 may have a three-layer structure. In yet another example, the cell line cap film 144 may have a four-layer or more-layer structure.

[0064] The cell insulating film 130 may be formed on the substrate 100 and the cell element isolation film 105. More specifically, the cell insulating film 130 may be formed on the upper surface of the substrate 100 in a region where the bit line contact 146 and the storage contact 120 are not formed, and on the cell element isolation film 105 and the cell region isolation film 22. The cell insulating film 130 may contact the upper surfaces of the substrate 100, the cell element isolation film 105, and the cell region isolation film 22. The cell insulating film 130 may be formed between the substrate 100 and the cell conductive line 140, and between the cell element isolation film 105 and the cell conductive line 140.

[0065] The unit insulating film 130 may be a single film. However, as shown, the unit insulating film 130 may be embodied as a multi-film including a first unit insulating film 131 and a second unit insulating film 132. For example, the first unit insulating film 131 may be formed of or include a silicon oxide film, and the second unit insulating film 132 may be formed of or include a silicon nitride film. In an example embodiment, the first unit insulating film 131 may contact the upper surface of the substrate 100, the unit element isolation film 105, and the unit area isolation film 22, and the second unit insulating film 132 may contact the upper surface of the first unit insulating film 131. However, the present disclosure is not limited thereto. Unlike what is shown, the unit insulating film 130 may be embodied as a triple film including a silicon oxide film, a silicon nitride film, and a silicon oxide film. However, the present disclosure is not limited thereto.

[0066] The cell buffer film 101 may be disposed between the cell insulating film 130 and the cell region isolation film 22. The cell buffer film 101 may contact an upper surface of the cell region isolation film 22, and the cell insulating film 130 may contact an upper surface of the cell buffer film 101. The cell buffer film 101 may be formed of, for example, a silicon oxide film or include, for example, a silicon oxide film. However, the present disclosure is not limited thereto.

[0067] The cell line spacer 150 may be disposed on a sidewall of each of the cell conductive line 140 and the cell line capping film 144. The cell line spacer 150 may be formed on the substrate 100 and the cell element isolation film 105 in a region where the cell conductive line 140 overlaps with the bit line contact 146. The cell line spacer 150 may be disposed on the sidewalls of the cell conductive line 140, the cell line capping film 144, and the bit line contact 146. The cell line spacer 150 may contact the sidewalls of the cell conductive line 140, the cell line capping film 144, and the bit line contact 146.

[0068] However, in a region where the cell conductive line 140 does not overlap the bit line contact 146, a cell line spacer 150 may be disposed on the cell insulating film 130. The cell line spacer 150 may be disposed on sidewalls of the cell conductive line 140 and the cell line capping film 144.

[0069] The cell line spacer 150 may be embodied as a single film. However, as shown, the cell line spacer 150 may have a multi-film structure including first to fourth cell line spacers 151, 152, 153, and 154. For example, each of the first to fourth cell line spacers 151, 152, 153, and 154 may include one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbon nitride film (SiOCN), air, and a combination thereof. However, the present disclosure is not limited thereto.

[0070] For example, the second cell line spacer 152 may not be disposed on the cell insulating film 130 but may be disposed on the sidewall of the bit line contact 146. Figure 3 and Figure 5 In the embodiment, the bit line structure 140ST may extend in an elongated manner in the second direction D2. The cell line spacer 150 may be disposed on a long sidewall extending in the second direction D2 among sidewalls of the bit line structure 140ST.

[0071] exist Figure 5 In the embodiment, the dummy bit line structure 140ST_1 may be disposed on the cell region isolation film 22. The dummy bit line structure 140ST_1 may have the same structure as the bit line structure 140ST. For example, the dummy bit line structure 140ST_1 may include a cell conductive line 140 and a cell line cap film 144. In this regard, the cell conductive line 140 of the dummy bit line structure 140ST_1 may be a boundary bit line BL_IF.

[0072] The fence pattern 170 may be disposed on the substrate 100 and the cell element isolation film 105. The fence pattern 170 may be formed to overlap the cell gate structure 110 formed in the substrate 100 and the cell element isolation film 105 in the fourth direction D4. The fence pattern 170 may be disposed between the bit line structures 140ST extending longitudinally along the second direction D2. The fence pattern 170 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof.

[0073] The storage contact 120 may be disposed between the cell conductive lines 140 adjacent to each other along the first direction D1. The storage contact 120 may be disposed between the fence patterns 170 adjacent to each other along the second direction D2. The storage contact 120 may contact the side surfaces of the fence pattern 170 and the cell line spacer 150. The storage contact 120 may overlap a portion of the substrate 100 and a portion of the cell element isolation film 105 between the adjacent cell conductive lines 140. The storage contact 120 may contact the substrate 100 and the cell element isolation film 105. The storage contact 120 may be connected to the storage connection region of the cell active area ACT. In this regard, the storage contact 120 may serve as a buried contact BC.

[0074] The storage contact 120 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

[0075] The storage pad 160 may be formed on the storage contact 120. The storage pad 160 may contact the upper surface of the storage contact 120. The storage pad 160 may be electrically connected to the storage contact 120. The storage pad 160 may be connected to the storage connection region of the cell active area ACT. In this regard, the storage pad 160 may serve as a landing pad LP.

[0076] The storage pad 160 may overlap a portion of the upper surface of the bit line structure 140ST. The storage pad 160 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

[0077] The pad isolation insulating film 180 may be formed on the storage pad 160 and the bit line structure 140ST. For example, the pad isolation insulating film 180 may be disposed on the cell line cap film 144. The pad isolation insulating film 180 may contact the storage pad 160 and the bit line structure 140ST. For example, the pad isolation insulating film 180 may contact the cell line cap film 144. The pad isolation insulating film 180 may define the storage pad 160 as each of a plurality of isolated regions. The pad isolation insulating film 180 may not cover the upper surface of the storage pad 160. The pad isolation recess 180R may isolate adjacent storage pads 160 from each other. The pad isolation insulating film 180 may fill the pad isolation recess 180R. The pad isolation insulating film 180 may isolate the storage pads 160 from each other. For example, based on the upper surface of the substrate 100, the vertical level of the upper surface of the storage pad 160 may be equal to the vertical level of the upper surface of the pad isolation insulating film 180. For example, upper surfaces of the memory pad 160 and the pad isolation insulating film 180 may be coplanar.

[0078] The pad isolation insulating film 180 may include an insulating material, and may electrically isolate adjacent storage pads 160 from each other among the plurality of storage pads 160. For example, the pad isolation insulating film 180 may be formed of or include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbon nitride film, and a silicon carbon nitride film.

[0079] The peripheral element isolation film 26 may be formed in the substrate 100 and in the peripheral region PR. The peripheral element isolation film 26 may define a peripheral active region in the peripheral region PR. The upper surface of the peripheral element isolation film 26 is shown to be coplanar with the upper surface of the substrate 100. However, the present disclosure is not limited thereto. The peripheral element isolation film 26 may include, but is not limited to, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0080] The peripheral gate structure 240ST may be disposed on the substrate 100 and in the peripheral region PR. The peripheral gate structure 240ST may be disposed on a peripheral active region defined by the peripheral element isolation film 26.

[0081] The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, and a peripheral capping film 244 sequentially stacked on the substrate 100. For example, the peripheral capping film 244 may contact the upper surface of the peripheral gate conductive film 240, and the peripheral gate conductive film 240 may contact the upper surface of the peripheral gate insulating film 230. The peripheral gate structure 240ST may include a peripheral spacer 245 disposed on the sidewalls of the peripheral gate conductive film 240 and the sidewalls of the peripheral capping film 244.

[0082] The peripheral gate conductive film 240 may include first to third peripheral conductive films 241, 242, and 243 sequentially stacked on the peripheral gate insulating film 230. In one example, no additional conductive film may be provided between the peripheral gate conductive film 240 and the peripheral gate insulating film 230. In another example, unlike what is shown, an additional conductive film, such as a work function conductive film, may be provided between the peripheral gate conductive film 240 and the peripheral gate insulating film 230.

[0083] Although two peripheral gate structures 240ST are shown to be disposed between adjacent peripheral element isolation films 26 , this is only for convenience of explanation and the present disclosure is not limited thereto.

[0084] The blocking conductive structure 240ST_1 may be disposed between the cell region CR and the peripheral region PR. A portion of the blocking conductive structure 240ST_1 is shown to overlap the cell region isolation film 22. However, the present disclosure is not limited thereto. The blocking conductive structure 240ST_1 may be a conductive structure closest to the dummy bit line structure 140ST_1 in the first direction D1.

[0085] The blocking conductive structure 240ST_1 may include a blocking gate insulating film 230_1, a blocking conductive line 240_1, and a blocking capping film 244_1 sequentially stacked on the substrate 100. The blocking conductive structure 240ST_1 may include a blocking spacer 245_1 disposed on a sidewall of the blocking conductive line 240_1 and a sidewall of the blocking capping film 244_1. In this regard, the blocking conductive line 240_1 may be a boundary peripheral gate PR_ST1.

[0086] The blocking conductive line 240_1 may include first-first to first-third blocking conductive films 241_1, 242_1, and 243_1 sequentially stacked on the blocking gate insulating film 230_1. The stacked film structure of the blocking conductive line 240_1 between the blocking gate insulating film 230_1 and the blocking cap film 244_1 may be the same as that of the peripheral gate conductive film 240.

[0087] The peripheral gate structure 240ST and the blocking conductive structure 240ST_1 may be located at the same level. In this regard, “A and B are located at the same level” may include A and B being formed in the same manufacturing process. Each of the peripheral gate conductive film 240 and the blocking conductive line 240_1 may have the same stacking structure as the stacking structure of the unit conductive line 140.

[0088] The first peripheral conductive film 241 and the first-first blocking conductive film 241_1 may include the same material as that of the first unit conductive film 141. The second peripheral conductive film 242 and the first-second blocking conductive film 242_1 may include the same material as that of the second unit conductive film 142. The third peripheral conductive film 243 and the first-third blocking conductive film 243_1 may include the same material as that of the third unit conductive film 143.

[0089] The peripheral gate insulating film 230 and the blocking gate insulating film 230_1 may include the same material. The peripheral gate insulating film 230 and the blocking gate insulating film 230_1 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide, or include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide.

[0090] The peripheral spacer 245 and the blocking spacer 245_1 may include the same material. For example, the peripheral spacer 245 and the blocking spacer 245_1 may be formed of at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon oxycarbon nitride, and a combination thereof, or include at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon oxycarbon nitride, and a combination thereof. Although each of the peripheral spacer 245 and the blocking spacer 245_1 is shown as embodied as a single film, this is only for ease of explanation and the present disclosure is not limited thereto. In another example, each of the peripheral spacer 245 and the blocking spacer 245_1 may be embodied as a stack of multiple layers.

[0091] The peripheral cap film 244 and the blocking cap film 244_1 may include the same material. For example, each of the peripheral cap film 244 and the blocking cap film 244_1 may include at least one of a silicon nitride film, silicon oxynitride, and silicon oxide.

[0092] The lower etch stop film 250 may be disposed on the substrate 100. The lower etch stop film 250 may contact the upper surface of the substrate 100 and the peripheral element isolation film 26. The lower etch stop film 250 may be formed according to the profile of the peripheral gate structure 240ST and the profile of the blocking conductive structure 240ST_1. The lower etch stop film 250 may extend along the sidewall of the dummy bit line structure 140ST_1. For example, the lower etch stop film 250 may include at least one of silicon nitride, silicon nitride oxide, carbon silicon nitride, and silicon oxycarbon nitride.

[0093] The lower peripheral interlayer insulating film 290 may be disposed on the lower etch stop film 250. The lower peripheral interlayer insulating film 290 may contact the upper surface of the lower etch stop film 250. The lower peripheral interlayer insulating film 290 may be disposed around the peripheral gate structure 240ST. The lower peripheral interlayer insulating film 290 may be disposed on the cell region isolation film 22 and between the dummy bit line structure 140ST_1 and the blocking conductive structure 240ST_1.

[0094] The lower peripheral interlayer insulating film 290 may include an oxide-based insulating material. An upper surface of the lower peripheral interlayer insulating film 290 may be coplanar with an upper surface of the lower etch stop film 250 extending along an upper surface of the peripheral gate structure 240ST.

[0095] The upper peripheral interlayer insulating film 291 is disposed on the peripheral gate structure 240ST and the lower peripheral interlayer insulating film 290. The upper peripheral interlayer insulating film 291 may cover the peripheral gate structure 240ST and the lower peripheral interlayer insulating film 290. For example, based on the upper surface of the substrate 100, the vertical level of the upper surface of the upper peripheral interlayer insulating film 291 may be the same as the vertical level of the upper surface of the cell line capping film 144.

[0096] The upper peripheral interlayer insulating film 291 includes a material different from that of the lower peripheral interlayer insulating film 290. The upper peripheral interlayer insulating film 291 may include, for example, a nitride-based insulating material. For example, the upper peripheral interlayer insulating film 291 may be formed of or include silicon nitride.

[0097] The peripheral contact plug 260 may be disposed on each of two opposite sides of the peripheral gate structure 240ST. The peripheral contact plug 260 may extend through the upper peripheral interlayer insulating film 291 and the lower peripheral interlayer insulating film 290, and then extend to the substrate 100 in the peripheral region PR. For example, the peripheral contact plug 260 may contact the upper peripheral interlayer insulating film 291, the lower peripheral interlayer insulating film 290, and the substrate 100. The peripheral contact plug 260 is connected to the substrate 100 in the peripheral region PR.

[0098] The peripheral wiring line 265 may be disposed on the peripheral gate structure 240ST. The peripheral wiring line 265 may be disposed on the upper peripheral interlayer insulating film 291 and the peripheral contact plug 260. The peripheral wiring line 265 may contact the upper peripheral interlayer insulating film 291 and the peripheral contact plug 260. The peripheral contact plug 260 is connected to the peripheral wiring line 265. The peripheral wiring line 265 may be isolated from each other via the wire isolation recess 280R. The width of the wire isolation recess 280R may vary. The wire isolation insulating film 280 may fill the wire isolation recess 280R. The wire isolation insulating film 280 may isolate the peripheral wiring lines 265 from each other. For example, the wire isolation insulating film 280 may contact the peripheral wiring line 265.

[0099] The peripheral contact plug 260 and the peripheral wiring line 265 may include the same material as that of the memory pad 160. The peripheral contact plug 260 and the peripheral wiring line 265 may be located at the same level as that of the memory pad 160. The upper surface of the peripheral wiring line 265 may be coplanar with the upper surface of the memory pad 160.

[0100] The peripheral etching stopper film 296 is disposed in the peripheral region PR. The peripheral etching stopper film 296 is disposed on the peripheral wiring line 265 and the line isolation insulating film 280. The peripheral etching stopper film 296 may contact the upper surfaces of the peripheral wiring line 265 and the line isolation insulating film 280. The peripheral etching stopper film 296 is not disposed on the storage pad 160.

[0101] The cell etch stop film 297 is disposed in the cell region CR. The cell etch stop film 297 is disposed on the memory pad 160 and the pad isolation insulating film 180. The cell etch stop film 297 may contact the upper surfaces of the memory pad 160 and the pad isolation insulating film 180. The cell etch stop film 297 is not disposed on the peripheral gate structure 240ST.

[0102] In some embodiments, the second thickness tc of the cell etch stop film 297 may be equal to the first thickness tp of the peripheral etch stop film 296. The upper surface of the cell etch stop film 297 on the cell region CR may be coplanar with the upper surface of the peripheral etch stop film 296 in the peripheral region PR. As used herein, thickness refers to a thickness or height measured in a direction perpendicular to the top surface of the substrate 100 (e.g., a vertical direction or a fourth direction D4).

[0103] In some embodiments, the second thickness tc of the cell etch stop film 297 may be different from the first thickness tp of the peripheral etch stop film 296. The upper surface of the cell etch stop film 297 on the cell region CR may not be coplanar with the upper surface of the peripheral etch stop film 296 in the peripheral region PR. For example, the first thickness tp of the peripheral etch stop film 296 may be less than the second thickness tc of the cell etch stop film 297.

[0104] The unit etch stop film 297 includes a material different from that of the peripheral etch stop film 296. For example, the unit etch stop film 297 may be formed of or include silicon boron nitride (SiBN), and the peripheral etch stop film 296 may include silicon carbon nitride (SiCN).

[0105] In some embodiments, the peripheral etch stop film 296 does not extend into the cell region CR. The peripheral etch stop film 296 extends to a portion of the interface region IR. The cell etch stop film 297 does not extend to the peripheral region PR. The cell etch stop film 297 extends to the interface region IR. The side end 296EP of the peripheral etch stop film 296 and the side end 297EP of the cell etch stop film 297 are disposed in the interface region IR.

[0106] The side end 296EP of the peripheral etch stopper film 296 and the side end 297EP of the cell etch stopper film 297 are disposed on the cell region isolation film 22 .

[0107] In some embodiments, the peripheral etch stop film 296 includes a first portion 296_1 overlapping the unit etch stop film 297 in the fourth direction D4 and a second portion 296_2 not overlapping the unit etch stop film 297 in the fourth direction D4. The first portion 296_1 of the peripheral etch stop film 296 is disposed in the interface region IR. In the interface region IR, a portion of the peripheral etch stop film 296 (i.e., the first portion 296_1 thereof) overlaps the unit etch stop film 297 in the fourth direction D4.

[0108] The side end 297EP of the unit etch stopper film 297 is disposed on the upper surface of the peripheral etch stopper film 296. The unit etch stopper film 297 covers the side end 296EP of the peripheral etch stopper film 296. The unit etch stopper film 297 extends onto a portion of the upper surface of the peripheral etch stopper film 296.

[0109] In other words, the etching stop film 295 including the peripheral etching stop film 296 and the unit etching stop film 297 is disposed in the unit region CR, the interface region IR, and the peripheral region PR. The maximum thickness tc+tp of the portion of the etching stop film 295 in the interface region IR is greater than each of the thickness tc of the portion of the etching stop film 295 in the unit region CR and the thickness tp of the portion of the etching stop film 295 in the peripheral region PR. The etching stop film 295 in the interface region IR includes a first portion having a first thickness tp, a second portion having a second thickness tc, and a third portion having a third thickness tc+tp. The first portion is adjacent to the peripheral region PR, the second portion is adjacent to the unit region CR, and the third portion is disposed between the first portion and the second portion. Each of the first portion and the second portion may have a single film structure, and the third portion may have a double film structure.

[0110] The capacitor structure 190 may be disposed on the storage pad 160. A portion of the capacitor structure 190 may be disposed on the cell etch stop film 297. A portion of the capacitor structure 190 may extend through the cell etch stop film 297 to be electrically connected to the storage pad 160. The capacitor structure 190 includes a first lower electrode 191, a first capacitor dielectric film 192, and a first upper electrode 193. For example, the first upper electrode 193 may have a plate shape.

[0111] The first lower electrode 191 may be disposed on the storage pad 160. For example, the lower surface of the first lower electrode 191 may contact the upper surface of the storage pad 160. The first lower electrode 191 is shown to have a columnar shape. However, the present disclosure is not limited thereto. In another example, the first lower electrode 191 may have a cylindrical shape. The first capacitor dielectric film 192 is formed on the first lower electrode 191. The first capacitor dielectric film 192 may be formed according to the contour of the first lower electrode 191. The first capacitor dielectric film 192 may contact the upper and side surfaces of the first lower electrode 191 and the upper surface of the cell etching stop film 297. The first upper electrode 193 is formed on the first capacitor dielectric film 192. The first upper electrode 193 may contact the upper and side surfaces of the first capacitor dielectric film 192. The first upper electrode 193 may surround the outer wall of the first lower electrode 191. The shape of the edge portion of the first upper electrode 193 is not limited to the shape shown.

[0112] The first capacitor dielectric film 192 overlaps the first upper electrode 193 in the fourth direction D4. The first capacitor dielectric film 192 is not disposed in a region in which the first capacitor dielectric film 192 does not overlap the first upper electrode 193 in the fourth direction D4.

[0113] The unit etch stop film 297 overlaps the capacitor structure 190 in the fourth direction D4. The unit etch stop film 297 is not disposed in a region in which the unit etch stop film 297 does not overlap the capacitor structure 190 in the fourth direction D4. A side end 190EP of the capacitor structure 190 is a side end of the first upper electrode 193 or a side end of the first capacitor dielectric film 192. The side end 190EP of the capacitor structure 190 may be aligned with a side end 297EP of the unit etch stop film 297 in the vertical direction D4.

[0114] The first portion 296_1 of the peripheral etch stop film 296 overlaps the capacitor structure 190 in the fourth direction D4. The second portion 296_2 of the peripheral etch stop film 296 does not overlap the capacitor structure 190 in the fourth direction D4.

[0115] Each of the first lower electrode 191 and the first upper electrode 193 may be formed of a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (such as ruthenium, iridium, titanium or tantalum, etc.) or a conductive metal oxide (such as iridium oxide or niobium oxide, etc.), or include a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (such as ruthenium, iridium, titanium or tantalum, etc.) or a conductive metal oxide (such as iridium oxide or niobium oxide, etc.). However, the present disclosure is not limited thereto. The first upper electrode 193 is shown as embodied as a single film. However, the present disclosure is not limited thereto. The first upper electrode 193 may include a stack of multiple conductive films, wherein the conductive films may include different conductive materials.

[0116] The first capacitor dielectric film 192 may include, but is not limited to, for example, one of silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material, and a combination thereof. In a semiconductor memory device according to some embodiments, the first capacitor dielectric film 192 may include a stacked film structure in which a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film are stacked in sequence. In a semiconductor memory device according to some embodiments, the first capacitor dielectric film 192 may include a dielectric film containing hafnium (Hf). In a semiconductor memory device according to some embodiments, the first capacitor dielectric film 192 may have a stacked structure of a ferroelectric material film and a paraelectric material film.

[0117] The interlayer insulating film 292 may be disposed on the peripheral etch stop film 296. The interlayer insulating film 292 covers the side end 190EP of the capacitor structure 190 and the side end 297EP of the unit etch stop film 297. The interlayer insulating film 292 may contact the side end 190EP of the capacitor structure 190 and the side end 297EP of the unit etch stop film 297. The interlayer insulating film 292 may be formed of, for example, an oxide-based insulating material or include, for example, an oxide-based insulating material. However, the present disclosure is not limited thereto.

[0118] Figures 7 to 10 is a diagram for explaining a semiconductor memory device according to an example embodiment. For ease of description, the following description is mainly based on its similarity to the above-referenced Figures 1 to 6 The difference between the descriptions. Duplicate descriptions will not be repeated.

[0119] Reference Figure 7 In the semiconductor memory device according to some embodiments, a thickness tp1 of the first portion 296_1 of the peripheral etch stop film 296 is greater than a thickness tp2 of the second portion 296_2 of the peripheral etch stop film 296 .

[0120] For example, when etching the first upper electrode 193, the first capacitor dielectric film 192 and the unit etch stop film 297 may be etched together. At this time, a portion of the peripheral etch stop film 296 may be etched together with the first capacitor dielectric film 192 and the unit etch stop film 297. Therefore, a thickness tp1 of a first portion 296_1 of the peripheral etch stop film 296 overlapping the unit etch stop film 297 may be greater than a thickness tp2 of a second portion 296_2 of the peripheral etch stop film 296 not overlapping the unit etch stop film 297.

[0121] Reference Figure 8 In the semiconductor memory device according to some embodiments, the peripheral etch stop film 296 extends to the cell region CR. A portion of the peripheral etch stop film 296 is disposed in the cell region CR. A side end 296EP of the peripheral etch stop film 296 is disposed in the cell region CR. A first portion 296_1 of the peripheral etch stop film 296 is disposed in the interface region IR and the cell region CR.

[0122] The peripheral etch stopper film 296 does not extend to the memory pad 160 closest to the cell region isolation film 22. The peripheral etch stopper film 296 does not cover the upper surface of the memory pad 160 closest to the cell region isolation film 22.

[0123] Reference Fig. 9 and Fig.10In the semiconductor memory device according to some embodiments, the peripheral etch stop film 296 does not overlap the unit etch stop film 297 in the fourth direction D4. The side end 296EP of the peripheral etch stop film 296 is spaced apart from the side end 297EP of the unit etch stop film 297 in the horizontal direction parallel to the upper surface of the substrate 100. The side end 296EP of the peripheral etch stop film 296 faces the side end 297EP of the unit etch stop film 297 in the horizontal direction (e.g., the first direction D1) parallel to the upper surface of the substrate 100.

[0124] The peripheral etch stop film 296 does not overlap the capacitor structure 190 in the fourth direction D4.

[0125] Reference Fig. 9 In the semiconductor memory device according to some embodiments, the side end 296EP of the peripheral etching stopper film 296 is disposed in the interface region IR. The etching stopper film 295 including the peripheral etching stopper film 296 and the unit etching stopper film 297 may not cover a portion of the peripheral wiring line 265 in the interface region IR to be exposed.

[0126] Reference Fig.10 In the semiconductor memory device according to some embodiments, the side end 296EP of the peripheral etch stop film 296 is disposed in the peripheral region PR. The side end 296EP of the peripheral etch stop film 296 may be disposed on a portion of the peripheral gate structure 240ST closest to the cell region isolation film 22 (i.e., the blocking conductive structure 240ST_1). The etch stop film 295 including the peripheral etch stop film 296 and the cell etch stop film 297 may not cover a portion of the peripheral wiring line 265 in the interface region IR and a portion of the peripheral wiring line 265 in the peripheral region PR to be exposed.

[0127] Fig.11 is a layout diagram for explaining a semiconductor memory device according to some embodiments. Fig.12 is a perspective view for explaining a semiconductor memory device according to some embodiments. Fig.13 It is along Fig.11 A cross-sectional view cut along lines DD and EE.

[0128] As a reference, Fig.11 Can be Figure 1 The enlarged view of the region R1 (unit region CR) in FIG. Fig.11 In a semiconductor memory device applied to a cell region CR, a cross section of a boundary portion of the cell region (for example, along Figure 3 The cross section taken by line BB in Figure 5 The cross section in .

[0129] Reference Figures 11 to 13 , a semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating film 450, and a capacitor 480. A semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT). A vertical channel transistor may refer to a structure in which a channel length of a channel layer 430 extends from the substrate 100 in a vertical direction (e.g., a fourth direction D4).

[0130] The lower insulating layer 412 may be disposed on the substrate 100. A plurality of first conductive lines 420 may be disposed on the lower insulating layer 412 and may be spaced apart from each other in the first direction D1 and extend longitudinally in the second direction D2. A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill spaces between adjacent first conductive lines 420 among the plurality of first conductive lines 420. The plurality of first insulating patterns 422 may extend longitudinally in the second direction D2. The upper surfaces of the plurality of first insulating patterns 422 may be located at the same vertical level as the vertical level of the upper surfaces of the plurality of first conductive lines 420. For example, the upper surfaces of the plurality of first insulating patterns 422 and the plurality of first conductive lines 420 may be coplanar. Each of the plurality of first conductive lines 420 may serve as a bit line.

[0131] Each of the plurality of first conductive lines 420 may include at least one of a semiconductor material doped with impurities, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, and a combination thereof. For example, each of the plurality of first conductive lines 420 may include at least one of polysilicon doped with impurities, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and a combination thereof, but may not be limited thereto. Each of the plurality of first conductive lines 420 may include a single layer or multiple layers made of the above-mentioned materials. In some embodiments, each of the plurality of first conductive lines 420 may be formed of graphene, carbon nanotubes, or a combination thereof, or include graphene, carbon nanotubes, or a combination thereof.

[0132] The channel layer 430 may have a matrix form in which the channels are spaced apart from each other in each of the first direction D1 and the second direction D2 and are respectively arranged on the plurality of first conductive lines 420. Each channel of the channel layer 430 may have a first width according to the first direction D1 and a first vertical dimension according to the fourth direction D4, wherein the first vertical dimension may be greater than the first width. In this regard, the fourth direction D4 may intersect the first direction D1 and the second direction D2, and may be, for example, a direction perpendicular to the upper surface of the substrate 100. For example, the first vertical dimension may be about 2 to 10 times the first width. However, the present disclosure is not limited thereto. The bottom of each channel of the channel layer 430 may be used as a third source / drain region (not shown), and the top of each channel of the channel layer 430 may be used as a fourth source / drain region (not shown). The portion of each channel of the channel layer 430 between the third source / drain region and the fourth source / drain region may be used as a channel region (not shown).

[0133] In some embodiments, the channel layer 430 may be formed of or include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga yO or a combination thereof. The channel layer 430 may include a single layer or multiple layers made of an oxide semiconductor. In some examples, the channel layer 430 may have a band gap energy greater than the band gap energy of silicon. For example, the channel layer 430 may have a band gap energy of about 1.5eV to about 5.6eV. For example, when the channel layer 430 has a band gap energy of about 2.0eV to 4.0eV, the channel layer 430 may have optimal channel performance. For example, the channel layer 430 may be made of polycrystalline or amorphous, but may not be limited thereto. In some embodiments, the channel layer 430 may be formed of graphene, carbon nanotubes, or a combination thereof, or include graphene, carbon nanotubes, or a combination thereof.

[0134] The gate electrode 440 may extend longitudinally in the first direction D1 and may be formed on both sidewalls of each channel of the channel layer 430. The gate electrode 440 may include a first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 and a second sub-gate electrode 440P2 facing the second sidewall of the channel layer 430 opposite to the first sidewall. Since one channel of the channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor device may have a dual-gate transistor structure. However, the technical spirit of the present disclosure is not limited thereto. The second sub-gate electrode 440P2 may be omitted, so that only the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 may be formed, thereby realizing a single-gate transistor structure. The description of the material of the gate electrode 440 may be the same as that of the unit gate electrode 112.

[0135] The gate insulating film 450 surrounds the sidewall of each channel of the channel layer 430 and may be interposed between each channel of the channel layer 430 and the gate electrode 440. The gate insulating film 450 may contact the sidewall of the channel layer 430. For example, as shown, the entire sidewall of each channel of the channel layer 430 may be surrounded by the gate insulating film 450, and a portion of the sidewall of the gate electrode 440 may contact the gate insulating film 450. In other embodiments, the gate insulating film 450 may extend in the extension direction (i.e., the first direction D1) of the gate electrode 440, and only two sidewalls facing the gate electrode 440 among all the sidewalls of each channel of the channel layer 430 may contact the gate insulating film 450. In some embodiments, the gate insulating film 450 may be embodied as a silicon oxide film, a silicon oxynitride film, a film made of a high dielectric constant material having a dielectric constant higher than that of the silicon oxide film, or a combination thereof.

[0136] The plurality of second insulating patterns 432 may extend longitudinally along the second direction D2 and may be respectively disposed on the plurality of first insulating patterns 422. Each channel of the channel layer 430 may be disposed between two adjacent second insulating patterns 432 among the plurality of second insulating patterns 432. The plurality of second insulating patterns 432 may contact the channel layer 430. In addition, the first buried layer 434 and the second buried layer 436 may be disposed between two adjacent second insulating patterns 432 and in a space between two adjacent channels of the channel layer 430. The first buried layer 434 may occupy the bottom of the space between the two adjacent channels of the channel layer 430. The second buried layer 436 may be formed to fill the remaining portion of the space between the two adjacent channels of the channel layer 430 and may be disposed on the first buried layer 434. The first buried layer 434 may contact the upper surface of the plurality of first conductive lines 420, and the second buried layer 436 may contact the upper surface of the first buried layer 434. Each of the second buried layer 436 and the first buried layer 434 may contact at least a portion of the side surface of the gate insulating film 450. The upper surface of the second buried layer 436 may be coplanar with the upper surface of the channel layer 430, and the second buried layer 436 may cover the upper surface of the gate electrode 440. For example, the second buried layer 436 may contact the upper surface of the gate electrode 440. Optionally, each of the plurality of second insulating patterns 432 and each of the plurality of first insulating patterns 422 may constitute a continuous material layer and thus may be monolithic. Optionally, the second buried layer 436 and the first buried layer 434 may constitute a continuous material layer and thus may be monolithic.

[0137] Each capacitor contact 460 may be disposed on each channel of the channel layer 430. Each capacitor contact 460 may vertically overlap each channel of the channel layer 430. For example, each capacitor contact 460 may be disposed on and vertically overlap a corresponding one of the channels of the channel layer 430. In example embodiments, the capacitor contact 460 may contact the channel layer 430. Therefore, the capacitor contacts 460 may be arranged in a matrix form in which the capacitor contacts 460 are spaced apart from each other in each of the first direction D1 and the second direction D2. The capacitor contact 460 may be formed of at least one of polysilicon doped with impurities, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and combinations thereof, or include at least one of polysilicon doped with impurities, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and combinations thereof, but may not be limited thereto. The upper insulating layer 462 may surround the sidewalls of each capacitor contact 460 and may be disposed on the plurality of second insulating patterns 432 and the second buried layer 436. For example, the upper insulating layer 462 may contact sidewalls of the capacitor contacts 460 and upper surfaces of the plurality of second insulating patterns 432 .

[0138] The unit etch stop film 470 may be disposed on the upper insulating layer 462. The unit etch stop film 470 may contact the upper surface of the upper insulating layer 462. The capacitor 480 may be disposed on the unit etch stop film 470. The unit etch stop film 470 may correspond to Figure 6 The unit etching stop film 297 in.

[0139] The capacitor 480 may include a second lower electrode 482, a second capacitor dielectric film 484, and a second upper electrode 486. The second lower electrode 482 may extend through the unit etch stop film 470 to be electrically connected to the upper surface of the capacitor contact 460. For example, the second lower electrode 482 may contact the upper surface of the capacitor contact 460. The second lower electrode 482 may be formed as a column structure extending in the fourth direction D4. However, the present disclosure is not limited thereto. In some embodiments, the second lower electrode 482 may be positioned to overlap vertically with the capacitor contact 460. The second lower electrode 482 may be arranged in a matrix form in the first direction D1 and the second direction D2, and may be spaced apart from each other in the first direction D1 and the second direction D2. Optionally, a landing pad (not shown) may be further disposed between the capacitor contact 460 and the second lower electrode 482, so that the second lower electrode 482 may be arranged in a hexagonal shape.

[0140] Fig.14 are layout diagrams for explaining a semiconductor memory device according to some example embodiments. Fig.15 is a perspective view for explaining a semiconductor memory device according to some example embodiments.

[0141] Reference Fig.14 and Fig.15 , a semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a capacitor 480. The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT).

[0142] A plurality of active regions AC may be defined in the substrate 100 by the first element isolation pattern 412A and the second element isolation pattern 414A. A channel structure 430A may be disposed in each active region AC. The channel structure 430A may include a first active pillar 430A1 and a second active pillar 430A2 extending in a vertical direction and a connection portion 430L connected to the bottom of the first active pillar 430A1 and the bottom of the second active pillar 430A2. The first source / drain region SD1 may be disposed in the connection portion 430L. The second source / drain region SD2 may be disposed in the top of each of the first active pillar 430A1 and the second active pillar 430A2. Each of the first active pillar 430A1 and the second active pillar 430A2 may constitute an independent unit memory cell.

[0143] A plurality of first conductive lines 420A may extend longitudinally in a direction intersecting with a plurality of active regions AC. For example, a plurality of first conductive lines 420A may extend in the second direction D2. One of the plurality of first conductive lines 420A may be disposed on the connection portion 430L and between the first active pillar 430A1 and the second active pillar 430A2. One first conductive line 420A may be disposed on the first source / drain region SD1. Another first conductive line 420A adjacent to the one first conductive line 420A may be disposed between two channel structures 430A. One first conductive line 420A among the plurality of first conductive lines 420A may be used as a common bit line commonly included in two unit memory cells, which correspond to the first active pillar 430A1 and the second active pillar 430A2 respectively disposed on both sides of the one first conductive line 420A.

[0144] A contact gate electrode 440A may be disposed between two channel structures 430A adjacent to each other along the second direction D2. For example, the contact gate electrode 440A may be disposed between a first active pillar 430A1 included in a channel structure 430A and a second active pillar 430A2 of another channel structure 430A adjacent to the one channel structure 430A in the second direction D2. A contact gate electrode 440A may be shared by a first active pillar 430A1 and a second active pillar 430A2 disposed on its two sidewalls, respectively. A gate insulating film 450A may be disposed between the contact gate electrode 440A and the first active pillar 430A1 and between the contact gate electrode 440A and the second active pillar 430A2. A plurality of second conductive lines 442A may extend longitudinally in the first direction D1. Each second conductive line 442A may be disposed on the upper surface of each contact gate electrode 440A. Each of the plurality of second conductive lines 442A may be used as a word line of a semiconductor device.

[0145] The capacitor contact 460A may be disposed on the channel structure 430A. The capacitor contact 460A may be disposed on the second source / drain region SD2. The capacitor 480 may be disposed on the capacitor contact 460A.

[0146] Figures 16 to 20 is a diagram of an intermediate structure corresponding to an intermediate step of a method of manufacturing a semiconductor memory device according to some example embodiments. Figures 1 to 10 Explanation of Description Repeated descriptions on the manufacturing method are briefly explained or omitted to avoid repetition.

[0147] Reference Figures 1 to 3 and Fig.16 , a substrate 100 including a cell region CR, a peripheral region PR, and an interface region IR is provided.

[0148] A cell gate structure 110 may be formed in the substrate 100 and in the cell region CR. The cell gate structure 110 may extend in an elongated manner in the first direction D1. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate capping pattern 113, and a cell gate capping conductive film 114.

[0149] Subsequently, a cell insulating film 130 may be formed on the substrate 100 and in the cell region CR. The cell insulating film 130 may not cover the peripheral region PR of the substrate 100 to be exposed.

[0150] Subsequently, a bit line structure 140ST may be formed on the substrate 100 and in the cell region CR The bit line structure 140ST may include a cell conductive line 140 and a cell line capping film 144 .

[0151] A peripheral gate structure 240ST may be formed on the substrate 100 and in the peripheral region PR. The peripheral gate structure 240ST may include a peripheral gate insulating film 230 , a peripheral gate conductive film 240 , a peripheral capping film 244 , and a peripheral spacer 245 .

[0152] Subsequently, a storage pad 160 disposed on the side surface of the bit line structure 140ST may be formed. The storage pads 160 may be isolated from each other via the pad isolation recess 180R. In addition, peripheral contact plugs 260 disposed on two opposite sides of the peripheral gate structure 240ST may be formed. Peripheral wiring lines 265 may be formed on the peripheral gate structure 240ST and the peripheral contact plugs 260. The peripheral wiring lines 265 may be isolated from each other via the line isolation recess 280R.

[0153] For example, the storage pad 160 , the peripheral contact plug 260 , and the peripheral wiring line 265 may be formed at the same time.

[0154] Subsequently, a pad isolation insulating film 180 filling the pad isolation recess 180R and a line isolation insulating film 280 filling the line isolation recess 280R may be formed. For example, the pad isolation insulating film 180 and the line isolation insulating film 280 may be formed simultaneously.

[0155] Reference Fig.17 , a pre-peripheral etching stopper film 296p may be formed on the storage pad 160, the pad isolation insulating film 180, the peripheral wiring line 265, and the line isolation insulating film 280. The pre-peripheral etching stopper film 296p may cover the upper surface of the storage pad 160, the upper surface of the pad isolation insulating film 180, the upper surface of the peripheral wiring line 265, and the upper surface of the line isolation insulating film 280.

[0156] Reference Fig.18, a portion of the pre-peripheral etch stopper film 296p disposed on the substrate 100 and in a portion of the interface region IR and the cell region CR may be removed. Thus, a peripheral etch stopper film 296 having a side end 296EP disposed on the substrate 100 and in the interface region IR may be formed.

[0157] Reference Fig.19 , a pre-cell etch stop film 297p may be formed on the peripheral etch stop film 296 to cover the peripheral region PR, the interface region IR, and the cell region CR. The pre-cell etch stop film 297p may cover the upper surface of the peripheral etch stop film 296, the side end 296EP of the peripheral etch stop film 296, and the upper surface of the peripheral wiring line 265 that is not covered by the peripheral etch stop film 296 and exposed, the upper surface of the pad isolation insulating film 180, and the upper surface of the storage pad 160.

[0158] Reference Fig. 20 , a first lower electrode 191 extending through the pre-cell etch stop film 297p may be formed. The first lower electrode 191 is connected to the storage pad 160. When the first lower electrode 191 is formed, the peripheral region PR and the interface region IR may be protected by the etch stop film because the portion of the etch stop film disposed in the peripheral region PR and the interface region IR (a combination of the peripheral etch stop film 296 and the pre-cell etch stop film 297p) is thicker than the portion of the etch stop film in the cell region CR. In addition, the pre-cell etch stop film 297p includes silicon boron nitride (SiBN). Therefore, a larger area of ​​the upper surface of the storage pad 160 may not be covered by the pre-cell etch stop film 297p to be exposed. Therefore, while the peripheral region PR and the interface region IR are protected, the first lower electrode 191 may be formed to contact the storage pad 160 with a set contact area size.

[0159] Subsequently, a pre-capacitor dielectric film 192p is formed on the first lower electrode 191. The pre-capacitor dielectric film 192p may be formed along the contour of the first lower electrode 191. The pre-capacitor dielectric film 192p may be formed on the pre-cell etch stop film 297p. The pre-capacitor dielectric film 192p may cover the cell region CR, the peripheral region PR, and the interface region IR.

[0160] Subsequently, a pre-upper electrode 193p is formed on the pre-capacitor dielectric film 192p. The pre-upper electrode 193p may cover the cell region CR, the peripheral region PR, and the interface region IR.

[0161] Next, refer to Figure 5, the first upper electrode 193 may be formed by patterning the pre-upper electrode 193p. At this time, the pre-capacitor dielectric film 192p and the pre-cell etch stop film 297p may be patterned together with the pre-upper electrode 193p. Thus, the first capacitor dielectric film 192 and the cell etch stop film 297 may be formed.

[0162] In the semiconductor memory device according to some embodiments, a cell etch stop film 297 and a peripheral etch stop film 296 including different materials are formed on a substrate 100 and in the cell region CR and the peripheral region PR, respectively. In other words, the cell etch stop film 297 in the cell region CR and the peripheral etch stop film 296 in the peripheral region PR are separated from each other. Therefore, the material and thickness of each of the cell etch stop film 297 and the peripheral etch stop film 296 in the cell region CR and the peripheral region PR, respectively, can be freely adjusted as needed. Therefore, a semiconductor memory device with improved reliability can be formed.

[0163] In addition, in the semiconductor memory device according to some embodiments, a peripheral etch stop film 296 including silicon carbon nitride (SiCN) having a relatively low dielectric constant is disposed on the substrate 100 and in the peripheral region PR. Therefore, the elements of the peripheral region PR and the capacitor structure 190 are electrically insulated from each other, so that the characteristics of the elements of the peripheral region PR can be improved.

[0164] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments. Without departing from the technical idea of ​​the present disclosure, the present disclosure can be implemented in various modified ways. Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of ​​the present disclosure, but are intended to describe the present disclosure. In fact, the scope of the technical idea of ​​the present disclosure is not limited by the disclosed embodiments. Therefore, it should be understood that the embodiments described above are illustrative and non-restrictive in all aspects. The scope of protection of the present disclosure should be interpreted by the claims, and all technical ideas within the scope of the present disclosure should be interpreted as included within the scope of the present disclosure.

[0165] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0141818 filed in the Korean Intellectual Property Office on October 23, 2023, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor memory device, comprising: A substrate, including a cell region and a peripheral region; a peripheral gate structure on the substrate in the peripheral region; a peripheral wiring circuit on the peripheral gate structure and connected to the substrate; a peripheral etching stop film on the peripheral wiring line; an element isolation film defining an active region in the cell region in the substrate; a storage pad connected to the active region defined in the cell region; a cell etch stop film on the storage pad; as well as a capacitor structure extending through the cell etch stop film to contact the storage pad, Wherein, the peripheral etching stop film and the unit etching stop film include materials different from each other.

2. The semiconductor memory device according to claim 1, in, The peripheral etching stop film includes silicon carbon nitride (SiCN), and Wherein, the unit etching stop film includes silicon boron nitride (SiBN).

3. The semiconductor memory device according to claim 1, in, The unit etching stopper film exists in a region where the unit etching stopper film overlaps with the capacitor structure in a vertical direction perpendicular to an upper surface of the substrate, and The unit etch stop film does not exist in a region where the unit etch stop film does not overlap with the capacitor structure in the vertical direction.

4. The semiconductor memory device according to claim 1, wherein: The first thickness of the peripheral etch stop film is equal to the second thickness of the unit etch stop film.

5. The semiconductor memory device according to claim 1, wherein: A first thickness of the peripheral etch stop film is different from a second thickness of the unit etch stop film.

6. The semiconductor memory device according to claim 5, wherein: The first thickness of the peripheral etch stop film is smaller than the second thickness of the unit etch stop film.

7. The semiconductor memory device according to claim 1, wherein: The cell etch stopper film and the peripheral etch stopper film do not overlap each other in a vertical direction perpendicular to an upper surface of the substrate in each of the cell region and the peripheral region.

8. A semiconductor memory device comprising: A substrate comprising a unit region, a peripheral region, and an interface region between the unit region and the peripheral region; a peripheral gate structure on the substrate and in the peripheral region; A peripheral wiring circuit on the peripheral gate structure; an element isolation film defining an active region in the cell region in the substrate; a storage pad on the active area defined in the cell area; a peripheral etching stop film on the peripheral wiring line and not on the storage pad; a cell etch stop film on the storage pad and not on the peripheral gate structure; as well as A capacitor structure extends through the cell etch stop film to contact the storage pad.

9. The semiconductor memory device according to claim 8, wherein: A side end of the unit etch stop film and a side end of the peripheral etch stop film are disposed on the substrate and in the interface region.

10. The semiconductor memory device according to claim 9, wherein: The peripheral etching stop film comprises: a first portion that does not overlap the unit etch stop film in a vertical direction perpendicular to an upper surface of the substrate; and The second portion overlaps the unit etching stopper film in the vertical direction.

11. The semiconductor memory device according to claim 10, wherein: The side end of the unit etch stopper film is disposed on the peripheral etch stopper film.

12. The semiconductor memory device according to claim 10, wherein: The thickness of the first portion is smaller than the thickness of the second portion.

13. The semiconductor memory device according to claim 9, wherein: The side end of the peripheral etch stopper film is spaced apart from the side end of the unit etch stopper film in a direction parallel to an upper surface of the substrate.

14. The semiconductor memory device according to claim 8, in, A side end of the unit etching stop film is disposed on the substrate and in the interface region, and Wherein, a side end of the peripheral etching stop film is disposed on the substrate and in the peripheral region.

15. The semiconductor memory device according to claim 8, in, A side end of the unit etching stop film is disposed on the substrate and in the interface region, and Wherein, a side end of the peripheral etching stop film is disposed on the substrate and in the cell area.

16. The semiconductor memory device according to claim 15, wherein: The side end of the unit etch stopper film is disposed on the peripheral etch stopper film.

17. The semiconductor memory device according to claim 8, wherein: The unit etch stop film and the peripheral etch stop film include materials different from each other.

18. A semiconductor memory device comprising: A substrate comprising a unit region, a peripheral region, and an interface region between the unit region and the peripheral region; a cell region isolation film defining the cell region in the substrate and in the interface region; a bit line structure on the substrate and in the cell region, wherein the bit line structure includes a cell conductive line and a cell line cap film on the cell conductive line; a cell gate electrode in the substrate and in the cell region and crossing the cell conductive line; an element isolation film in the substrate and defining an active region in the cell region; a storage pad on a side surface of the bit line structure and connected to the active region; a cell etch stop film on the storage pad; Capacitor structure, including: a lower electrode extending through the cell etch stop film to contact the storage pad; a capacitor dielectric film on the lower electrode; and an upper electrode on the capacitor dielectric film; a peripheral gate structure on the substrate and in the peripheral region; a peripheral wiring line on the peripheral gate structure and connected to the substrate; and a peripheral etching stop film, on the peripheral wiring line, Wherein, a side end of the cell etching stop film is arranged on the cell region isolation film in the interface region.

19. The semiconductor memory device according to claim 18, in, The unit etching stopper film exists in a region where the unit etching stopper film overlaps with the capacitor structure in a vertical direction perpendicular to an upper surface of the substrate, and The unit etch stop film does not exist in a region where the unit etch stop film does not overlap with the capacitor structure in the vertical direction.

20. The semiconductor memory device according to claim 18, wherein A side end of the peripheral etch stop film is disposed on the substrate and in the interface region.

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