Fabrication method of ETOX NOR type flash memory device

Abstract

This application provides a method for fabricating an ETOX NOR flash memory device. A first spin-coated carbon layer is spin-coated onto the memory region and the peripheral logic region. Using the first spin-coated carbon layer as a mask for the peripheral logic region, a first thinning of the memory region control gate material layer is performed through a single etch-back process. Further, after self-aligned source line ion implantation, a second spin-coated carbon layer is spin-coated. Another etch-back process is then performed, using the second spin-coated carbon layer as a mask for the peripheral logic region, to perform a second thinning of the memory region control gate material layer, thereby obtaining the final memory region control gate. The fabrication method for the ETOX NOR flash memory device provided by this application can reduce the aspect ratio of the first and second deep trenches between the control gates, increase the filling window of the interlayer insulating dielectric layer, and also save production costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a method for fabricating an ETOX NOR type flash memory device. Background Technology

[0002] Current 4X nanometer NOR Flash process platforms typically employ a photolithography and etching process after the control gate material layer deposition to increase the fill window of the interlayer insulating dielectric layer (equivalent to reducing the aspect ratio of the deep trenches between control gates). This process involves thinning the flat (plate-like) control gate material layer of the memory region to a certain thickness using a back-etching process. Further, after etching to form the deep trenches of the memory region and performing SAS (self-aligned source) processes, another photolithography and etching process is added to further thin the strip-shaped control gate of the memory region. Therefore, the traditional fabrication method for ETOX NOR flash memory devices requires these two additional photolithography and etching processes to thin the control gate and thus increase the fill window of the interlayer insulating dielectric layer, resulting in higher manufacturing costs. Summary of the Invention

[0003] This application provides a method for fabricating an ETOX NOR flash memory device, which can solve the problem of high manufacturing cost in the traditional method of fabricating ETOX NOR flash memory devices by increasing the filling window of the interlayer insulating dielectric layer (reducing the aspect ratio of the deep trench between the control gates).

[0004] This application provides a method for fabricating an ETOX NOR type flash memory device, including:

[0005] A substrate is provided, the substrate comprising a storage region and a peripheral logic region, wherein a pad oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are sequentially formed on the substrate surface of the storage region, and a gate oxide layer and a control gate material layer are sequentially formed on the substrate surface of the peripheral logic region.

[0006] The control gate material layer, ONO dielectric layer, floating gate material layer and pad oxide layer of the memory region are etched to the substrate surface to form a plurality of first deep trenches and second deep trenches, the first deep trenches and the second deep trenches being arranged alternately;

[0007] A first spin-coated carbon layer is formed, which fills the first deep trench and the second deep trench, as well as a control gate material layer covering the storage area and the control gate material layer covering the peripheral logic area.

[0008] The first spin-coated carbon layer of a certain thickness is etched through the etch-back process, and at the same time, the control gate material layer of the first thickness of the storage area is etched back.

[0009] Remove the remaining thickness of the first spin-coated carbon layer;

[0010] A source line ion implantation region is formed in the substrate at the bottom of the first deep trench using a self-aligned implantation process;

[0011] A second spin-coated carbon layer is formed, which fills the first deep trench and the second deep trench, as well as the control gate material layer covering the storage area and the control gate material layer covering the peripheral logic area.

[0012] The second spin-coated carbon layer of a certain thickness is etched using a reverse etching process, and simultaneously, the control gate material layer of a second thickness in the memory region is etched back; and

[0013] Remove the remaining thickness of the second spin-coated carbon layer.

[0014] Optionally, in the fabrication method of the ETOX NOR type flash memory device, during the etching process of etching a certain thickness of the first spin-coated carbon layer and simultaneously etching back the control gate material layer of the first thickness of the storage area, the etching gases include SO2 and O2, with the SO2 gas flow rate being 50 sccm to 100 sccm and the O2 gas flow rate being 10 sccm to 30 sccm; the etching time being 50 s to 100 s; and the process temperature being 20℃ to 60℃.

[0015] Optionally, in the fabrication method of the ETOX NOR type flash memory device, during the etching process of etching a certain thickness of the second spin-coated carbon layer and simultaneously etching back the control gate material layer of the second thickness of the storage area, the etching gas includes HBr and O2, the flow rate of HBr gas is 200 sccm~500 sccm, the etching time is 200 s~400 s, and the process temperature is 40℃~60℃.

[0016] Optionally, in the fabrication method of the ETOX NOR type flash memory device, the thickness of the control gate material layer of the memory region is 2000Å~2100Å before the first thickness of the control gate material layer of the memory region is etched back.

[0017] Optionally, in the fabrication method of the ETOX NOR type flash memory device, the first thickness of the control gate material layer of the memory region removed by etch-back is 350 Å to 450 Å.

[0018] Optionally, in the fabrication method of the ETOX NOR type flash memory device, the second thickness of the control gate material layer of the memory region removed by etch-back is 600 Å to 700 Å.

[0019] Optionally, in the method for fabricating the ETOX NOR flash memory device, after forming a plurality of first deep trenches and second deep trenches, and before forming the first spin-coated carbon layer, the method further includes:

[0020] Lightly doped drain regions are formed in the substrate at the bottom of the first and second deep trenches using an ion implantation process.

[0021] Optionally, in the fabrication method of the ETOX NOR flash memory device, the step of forming a source line ion implantation region in the substrate at the bottom of the first deep trench using a self-aligned implantation process includes:

[0022] A source line ion implantation region is formed at the bottom of the lightly doped drain region at the bottom of the first deep trench using a self-aligned implantation process.

[0023] Optionally, in the method for fabricating the ETOX NOR flash memory device, after removing the remaining thickness of the second spin-coated carbon layer, the method further includes:

[0024] The control gate material layer and gate oxide layer of the peripheral logic region are etched to form multiple third deep trenches.

[0025] The technical solution of this application has at least the following advantages:

[0026] This application adjusts the order of self-aligned source line ion implantation and etching of the control gate material layer of the peripheral logic region. Self-aligned source line ion implantation is performed before etching the control gate material layer of the peripheral logic region. Before self-aligned source line ion implantation, a first spin-on carbon layer (SOC) is spin-coated onto the memory region and the peripheral logic region. Utilizing the height difference between the first spin-on carbon layer on the memory region control gate material layer and the first spin-on carbon layer on the peripheral logic region control gate material layer, and using the first spin-on carbon layer as a mask for the peripheral logic region, a first thinning of the memory region control gate material layer is achieved through a single etch-back process. Further, after self-aligned source line ion implantation, a second spin-on carbon layer (SOC) is spin-coated, and another etch-back process is performed, using the second spin-on carbon layer as a mask for the peripheral logic region, to achieve a second thinning of the memory region control gate material layer, thus obtaining the final memory region control gate. Compared to the traditional ETOX NOR flash memory device fabrication method, the ETOX provided in this application... The fabrication method of NOR flash memory devices can eliminate the need for two photomasks / two photolithography processes, saving production costs. At the same time, it can also reduce the aspect ratio of the first and second deep trenches between the control gates and increase the filling window of the interlayer insulating dielectric layer.

[0027] Furthermore, the thickness of the control gate material layer for different devices (high-voltage devices, medium-voltage devices, low-voltage devices, etc.) in the peripheral logic area is no different from that of traditional ETOX NOR flash memory devices, so there is no need to adjust the thickness of the control gate material layer in the peripheral logic area. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a flowchart of the fabrication method of the ETOX NOR type flash memory device according to an embodiment of the present invention;

[0030] Figures 2-9 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of the ETOX NOR flash memory device according to an embodiment of the present invention;

[0031] The reference numerals in the attached figures are explained as follows:

[0032] 10-Substrate, 11-Lightly doped drain region, 12-Source line ion implantation region, 21-Pad oxide layer, 22-Gate oxide layer, 30-Floating gate material layer, 40-ONO dielectric layer, 50-Control gate material layer, 51-First deep trench, 52-Second deep trench, 53-Third deep trench, 61-First spin-coated carbon layer, 62-Second spin-coated carbon layer. Detailed Implementation

[0033] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0037] This application provides a method for fabricating an ETOX NOR type flash memory device, referring to... Figures 1-9 , Figure 1 This is a flowchart of the fabrication method of the ETOX NOR type flash memory device according to an embodiment of the present invention; Figures 2-9 This is a schematic diagram of the semiconductor structure in each process step of fabricating an ETOX NOR flash memory device according to an embodiment of the present invention. The fabrication method of the ETOX NOR flash memory device includes:

[0038] First, refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the first deep trench and the second deep trench according to an embodiment of this application. A substrate 10 is provided, the substrate 10 includes a storage region and a peripheral logic region. A pad oxide layer 21, a floating gate material layer 30, an ONO dielectric layer 40 and a control gate material layer 50 are sequentially formed on the surface of the substrate 10 of the storage region. A gate oxide layer 22 and a control gate material layer 50 are sequentially formed on the surface of the substrate 10 of the peripheral logic region.

[0039] In this embodiment, the conductivity type of the doped ions in the substrate of the storage region is P-type. The substrate of the storage region may also form several shallow trench isolation structures (not shown) for isolating different storage cells. Furthermore, the substrate of the storage region may also form a deep N-well, a high-voltage P-well located on the deep N-well, and a CVT region (not shown) located on the high-voltage P-well.

[0040] Furthermore, the peripheral logic region may include multiple device regions, such as a high-voltage device region, a medium-voltage device region, and a low-voltage device region, with each device region having its own well region (not shown) formed in its substrate. Additionally, the thickness of the gate oxide layer 22 differs between the different device regions within the peripheral logic region; specifically, the thickness of the gate oxide layer 22 in the high-voltage device region is greater than that in the medium-voltage device region, which in turn is greater than that in the low-voltage device region.

[0041] Then, continue to refer to Figure 2 The control gate material layer 50, ONO dielectric layer 40, floating gate material layer 30 and pad oxide layer 21 of the storage area are etched to the surface of the substrate 10 to form a plurality of first deep trenches 51 and second deep trenches 52, the first deep trenches 51 and the second deep trenches 52 being arranged alternately.

[0042] In this embodiment, a photoresist layer can be used as a mask to protect the peripheral logic area. A dry etching process is used to etch the control gate material layer 50, ONO dielectric layer 40, floating gate material layer 30 and pad oxide layer 21 of the memory area to the surface of the substrate 10 to form a plurality of first deep trenches 51 and second deep trenches 52.

[0043] Further reference Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of lightly doped drain regions in an embodiment of this application. After forming multiple first deep trenches 51 and second deep trenches 52, and before forming the first spin-coated carbon layer, the fabrication method of the ETOX NOR flash memory device may further include: forming multiple lightly doped drain regions 11 in the substrate at the bottom of the first deep trenches 51 and second deep trenches 52 by means of an ion implantation process.

[0044] In this embodiment, the conductivity type of the doped ions in the lightly doped drain region 11 is N-type doping.

[0045] Next, refer to Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the first spin-coated carbon layer according to an embodiment of this application. The first spin-coated carbon layer 61 is formed, which fills the first deep trench 51 and the second deep trench 52, and covers the control gate material layer 50 of the memory region and the control gate material layer 50 of the peripheral logic region.

[0046] It is worth noting that the first spin-coated carbon layer 61 is a SOC material, which has strong filling capacity, and its resistance to etching and ease of removal are all superior to those of photoresist.

[0047] Further reference Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the first spin-coated carbon layer and the control gate material layer are etched back according to an embodiment of this application. Through the etch-back process, the first spin-coated carbon layer 61 of a certain thickness is etched back, and at the same time, the control gate material layer 50 of the first thickness of the memory region is etched back.

[0048] Preferably, during the etching process, the first spin-coated carbon layer 61 of a certain thickness is etched back, and at the same time, the control gate material layer 50 of the first thickness of the storage area is etched back. The etching gases include SO2 and O2, with the SO2 gas flow rate being 50 sccm to 100 sccm and the O2 gas flow rate being 10 sccm to 30 sccm. The etching time is 50 s to 100 s and the process temperature is 20 ℃ to 60 ℃.

[0049] Next, refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the source line ion implantation region in an embodiment of this application, with the remaining thickness of the first spin-coated carbon layer 61 removed.

[0050] In this embodiment, the remaining thickness of the first spin-coated carbon layer 61 is removed using a dry strip and wet strip processes.

[0051] Further reference Figure 6 A source line ion implantation region 12 is formed at the bottom of the lightly doped drain region at the bottom of the first deep trench using a self-aligned implantation process.

[0052] In this embodiment, the doped ions in the source line ion implantation region 12 are of P-type and N-type conductivity.

[0053] Next, refer to Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the second spin-coated carbon layer according to an embodiment of this application. The second spin-coated carbon layer 62 is formed, which fills the first deep trench 51 and the second deep trench 52, as well as the control gate material layer 50 covering the memory region and the control gate material layer 50 covering the peripheral logic region.

[0054] Further reference Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after the second spin-coated carbon layer and the control gate material layer are etched back according to an embodiment of this application. Through the etch-back process, the second spin-coated carbon layer 62 of a certain thickness is etched back, and at the same time, the control gate material layer 50 of the second thickness of the memory region is etched back.

[0055] Specifically, the second spin-coated carbon layer 62 of a certain thickness is etched through the etch-back process. At the same time, during the etch-back process of the control gate material layer 50 of the storage area of ​​the second thickness, the etching gas includes HBr and O2. The flow rate of HBr gas is 200 sccm to 500 sccm; the etching time is 200 s to 400 s; and the process temperature is 40 ℃ to 60 ℃.

[0056] Preferably, the thickness of the control gate material layer 50 of the memory region is 2000 Å to 2100 Å before the first thickness of the control gate material layer 50 is etched back into the memory region. In this embodiment, the thickness of the control gate material layer 50 of the memory region is 2050 Å.

[0057] Preferably, the first thickness of the control gate material layer 50 of the memory region removed by etch-back is 350 Å to 450 Å. In this embodiment, the first thickness of the control gate material layer 50 of the memory region removed by etch-back is 400 Å.

[0058] Furthermore, the second thickness of the control gate material layer 50 of the memory region removed by etch-back is 600 Å to 700 Å. In this embodiment, the second thickness of the control gate material layer 50 of the memory region removed by etch-back is 650 Å.

[0059] Finally, refer to Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the third deep trench in an embodiment of this application, with the remaining thickness of the second spin-coated carbon layer 62 removed.

[0060] Further reference Figure 9 After removing the remaining thickness of the second spin-coated carbon layer 62, the fabrication method of the ETOXNOR flash memory device may further include: etching the control gate material layer 50 and the gate oxide layer 22 of the peripheral logic region to form a plurality of third deep trenches 53. The control gate material layer 50 serves as the gate of the device in the peripheral logic region. Therefore, while etching the control gate material layer 50 and the gate oxide layer 22 of the peripheral logic region to form a plurality of third deep trenches 53, corresponding gates on different device regions (high-voltage device region, medium-voltage device region, and low-voltage device region) can be obtained.

[0061] This application adjusts the order of self-aligned source line ion implantation and etching of the control gate material layer in the peripheral logic region. Before self-aligned source line ion implantation, a first spin-on carbon layer (SOC) is spin-coated on the memory region and the peripheral logic region. Utilizing the height difference between the first spin-on carbon layer on the memory region control gate material layer and the first spin-on carbon layer on the peripheral logic region control gate material layer, the first spin-on carbon layer is used as a mask for the peripheral logic region. A single etch-back process is then used to perform the first thinning of the memory region control gate material layer. Further, after self-aligned source line ion implantation, a second spin-on carbon layer (SOC) is spin-coated. Another etch-back process is then used, with the second spin-on carbon layer serving as a mask for the peripheral logic region, to perform a second thinning of the memory region control gate material layer. This results in the final memory region control gate, reducing the aspect ratio of the first and second deep trenches between the control gates and increasing the filling window of the interlayer insulating dielectric layer. Compared to the traditional ETOX NOR flash memory device fabrication method, the ETOX provided in this application... The fabrication method for NOR flash memory devices eliminates the need for two photomasks / two photolithography processes, increasing the filling window of the interlayer insulating dielectric layer while saving production costs. Furthermore, the thickness of the control gate material layer in the peripheral logic region of the flash memory device provided in this application is identical to the thickness of the control gate material layer (BSL) in the peripheral logic region of conventional flash memory devices, eliminating the need for additional adjustments to the peripheral logic region devices caused by differences in control gate material layer thickness.

[0062] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating an ETOX NOR type flash memory device, characterized in that, include: A substrate is provided, the substrate comprising a storage region and a peripheral logic region, wherein a pad oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are sequentially formed on the substrate surface of the storage region, and a gate oxide layer and a control gate material layer are sequentially formed on the substrate surface of the peripheral logic region. The control gate material layer, ONO dielectric layer, floating gate material layer and pad oxide layer of the memory region are etched to the substrate surface to form a plurality of first deep trenches and second deep trenches, the first deep trenches and the second deep trenches being arranged alternately; A first spin-coated carbon layer is formed, which fills the first deep trench and the second deep trench, as well as a control gate material layer covering the storage area and the control gate material layer covering the peripheral logic area. The first spin-coated carbon layer of a certain thickness is etched through the etch-back process, and at the same time, the control gate material layer of the first thickness of the storage area is etched back. Remove the remaining thickness of the first spin-coated carbon layer; A source line ion implantation region is formed in the substrate at the bottom of the first deep trench using a self-aligned implantation process; A second spin-coated carbon layer is formed, which fills the first deep trench and the second deep trench, as well as the control gate material layer covering the storage area and the control gate material layer covering the peripheral logic area. The second spin-coated carbon layer of a certain thickness is etched through the etch-back process, and at the same time, the control gate material layer of the second thickness of the storage area is etched back. as well as Remove the remaining thickness of the second spin-coated carbon layer.

2. The method for fabricating an ETOX NOR type flash memory device according to claim 1, characterized in that, During the etching process, a certain thickness of the first spin-coated carbon layer is etched back. At the same time, during the etching back of the control gate material layer of the storage area with a first thickness, the etching gases include SO2 and O2. The flow rate of SO2 gas is 50 sccm to 100 sccm; the flow rate of O2 gas is 10 sccm to 30 sccm; the etching time is 50 s to 100 s; and the process temperature is 20 ℃ to 60 ℃.

3. The method for fabricating an ETOX NOR type flash memory device according to claim 1, characterized in that, During the etching process, a second spin-coated carbon layer of a certain thickness is etched. At the same time, during the etching process of the control gate material layer of the second thickness in the storage area, the etching gas includes HBr and O2. The flow rate of HBr gas is 200 sccm to 500 sccm; the etching time is 200 s to 400 s; and the process temperature is 40 ℃ to 60 ℃.

4. The method for fabricating an ETOX NOR type flash memory device according to claim 1, characterized in that, Before the first thickness of the control gate material layer in the memory region is etched back, the thickness of the control gate material layer in the memory region is 2000Å~2100Å.

5. The method for fabricating an ETOX NOR type flash memory device according to claim 4, characterized in that, The first thickness of the control gate material layer of the memory region removed by etch-back is 350 Å to 450 Å.

6. The method for fabricating an ETOX NOR type flash memory device according to claim 5, characterized in that, The second thickness of the control gate material layer of the memory region removed by etch-back is 600 Å to 700 Å.

7. The method for fabricating an ETOX NOR type flash memory device according to claim 1, characterized in that, After forming multiple first deep trenches and second deep trenches, and before forming the first spin-coated carbon layer, the fabrication method of the ETOX NOR flash memory device further includes: Lightly doped drain regions are formed in the substrate at the bottom of the first and second deep trenches using an ion implantation process.

8. The method for fabricating an ETOX NOR type flash memory device according to claim 7, characterized in that, The step of forming a source line ion implantation region in the substrate at the bottom of the first deep trench using a self-aligned implantation process includes: A source line ion implantation region is formed at the bottom of the lightly doped drain region at the bottom of the first deep trench using a self-aligned implantation process.

9. The method for fabricating an ETOX NOR type flash memory device according to claim 1, characterized in that, After removing the remaining thickness of the second spin-coated carbon layer, the fabrication method of the ETOX NOR flash memory device further includes: The control gate material layer and gate oxide layer of the peripheral logic region are etched to form multiple third deep trenches.

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