Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, which comprises the following steps of: firstly, forming a first gate oxide layer on a substrate in a high-voltage MOS (Metal Oxide Semiconductor) device region, then removing the first gate oxide layer in a low-voltage MOS device region and re-depositing a second gate oxide layer, and then forming polycrystalline silicon material layers on the low-voltage MOS device region and the high-voltage MOS device region, and finally, opening the photomask of the first gate oxide layer of the low-voltage MOS device region, and back-etching the polycrystalline silicon material layer with a certain thickness in the low-voltage MOS device region. According to the method, the polycrystalline silicon material layer with a certain thickness in the low-voltage MOS device region can be etched back to form the low-voltage grid electrode by only depositing the polycrystalline silicon material layer once without a new photomask and directly adopting the photomask for etching back the first gate oxide layer, so that the polycrystalline silicon material layers with different thicknesses are formed in the high-voltage MOS device region and the low-voltage MOS device region; and the condition that the thin grid polycrystalline silicon of the high-voltage MOS device is mistakenly damaged by the subsequent LDD ion implantation process is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor device. Background Art

[0002] The gate thickness of high-voltage MOS devices (eg, 5V MOS devices) in the embedded flash (E-Flash) device platform at the 55nm technology node is 1000 angstroms.

[0003] In order to shorten the R&D cycle, high-voltage MOS devices (such as 5VMOS devices) in the E-Flash device platform of the 40nm technology node and high-voltage MOS devices (such as 5V MOS devices) in the E-Flash device platform of the 55nm technology node use the same set of process modes. Specifically, due to the use of the same set of process modes, in the E-Flash device platform of the 40nm technology node, the thickness of the gate polysilicon of the high-voltage MOS device (such as 5V MOS device) is consistent with the thickness of the gate polysilicon of the low-voltage MOS device (such as 1.1V MOS device) / medium-voltage MOS device (such as 2.5V MOS device), and usually needs to be thinned to 800 angstroms. However, since the gate polysilicon thickness of high-voltage MOS devices (such as 5V MOS devices) is thinned from 1000 angstroms to 800 angstroms, this limits the adjustment of lightly doped drain (LDD) ion implantation in the substrate. LDD ion implantation can easily damage the gate polysilicon of high-voltage MOS devices (such as 5V MOS devices) at the 40nm technology node by mistake. It can be seen that the current preparation process of E-Flash devices at the 40nm technology node is not fully compatible with the preparation process of high-voltage MOS devices in E-Flash devices at the 55nm technology node. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor device, which can solve the problem that the gate polysilicon of a high-voltage MOS device in the current 40nm technology node E-Flash device platform is accidentally damaged by a subsequent LDD ion implantation process.

[0005] The present invention provides a method for manufacturing a semiconductor device, comprising: A substrate is provided, the substrate comprising a flash memory device area, a high voltage MOS device area and a low voltage MOS device area, a plurality of shallow trench isolation structures are formed in the substrate, the shallow trench isolation structures are used to isolate different device areas, and a flash memory unit is formed on the substrate of the flash memory device area; forming a first gate oxide layer, wherein the first gate oxide layer covers the substrate of the high-voltage MOS device region and the substrate of the low-voltage MOS device region; Etching and removing the first gate oxide layer of the low voltage MOS device region; forming a second gate oxide layer, wherein the second gate oxide layer covers the substrate of the low voltage MOS device region; Forming a polysilicon material layer, wherein the polysilicon material layer covers the second gate oxide layer of the low voltage MOS device area, the flash memory unit of the flash memory device area, and the first gate oxide layer of the high voltage MOS device area, so as to form a high voltage gate in the high voltage MOS device area; A polysilicon material layer of a certain thickness in the low voltage MOS device region is etched to form a low voltage gate in the low voltage MOS device region.

[0006] Optionally, in the method for preparing the semiconductor device, the polysilicon material layer is formed by a furnace tube process.

[0007] Optionally, in the method for preparing the semiconductor device, in the process of forming the polysilicon material layer by adopting a furnace tube process, the process temperature is 600° C. to 800° C.

[0008] Optionally, in the method for preparing the semiconductor device, the thickness of the second gate oxide layer is smaller than the thickness of the first gate oxide layer.

[0009] Optionally, in the method for preparing the semiconductor device, after etching a polysilicon material layer of a certain thickness in the low-voltage MOS device region to form a low-voltage gate in the low-voltage MOS device region, the method for preparing the semiconductor device further includes: The polysilicon material layer on the flash memory cells of the flash memory device area is removed.

[0010] Optionally, in the method for preparing the semiconductor device, the flash memory unit is a split-gate flash memory unit.

[0011] Optionally, in the method for preparing the semiconductor device, the flash memory unit includes at least: a third gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer, a silicon nitride layer, a first side wall, a second side wall, a third side wall, a word line polysilicon and a word line protection layer; the third gate oxide layer, the floating gate layer, the ONO film layer, the control gate layer and the silicon nitride layer are stacked in sequence on the substrate of the flash memory device area; trenches are formed in the floating gate layer, the ONO film layer, the control gate layer and the silicon nitride layer; the first side wall, the second side wall and the third side wall cover the side walls of the trenches in sequence; the word line polysilicon fills the trenches; and the word line protection layer covers the word line polysilicon.

[0012] The technical solution of this application has at least the following advantages: In the present application, a first gate oxide layer is first formed on the substrate in the high-voltage MOS device region, and then the first gate oxide layer in the low-voltage MOS device region is removed and a second gate oxide layer is re-deposited on the low-voltage MOS device region, and then a thicker polysilicon material layer is formed in the high-voltage MOS device region and the low-voltage MOS device region to form a high-voltage gate, a mask is used to open the first gate oxide layer in the low-voltage MOS device region, and finally a polysilicon material layer of a certain thickness in the low-voltage MOS device region is back-etched, and the polysilicon material layer in the low-voltage MOS device region is thinned to a suitable thickness to form a low-voltage gate. It can be seen that the present application only requires a single deposition process of the polysilicon material layer, and there is no need to open the low-voltage MOS device region separately. By directly using a mask for opening the first gate oxide layer in the low-voltage MOS device area, a polysilicon material layer of a certain thickness in the low-voltage MOS device area can be backetched to form a low-voltage gate, thereby forming polysilicon material layers of different thicknesses in the high-voltage MOS device area and the low-voltage MOS device area, that is, a thicker polysilicon material layer is formed in the high-voltage MOS device area and a thinner polysilicon material layer is formed in the low-voltage MOS device area, thereby avoiding the situation where the thinner gate polysilicon of the high-voltage MOS device is accidentally damaged by the subsequent LDD ion implantation process. The preparation method of the semiconductor device provided by the present application is simple, avoids the cumbersome process flow, and reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention; Figure 2-Figure 8 is a schematic diagram of a semiconductor structure in each process step of preparing a semiconductor device according to an embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 11-shallow trench isolation structure, 21-third gate oxide layer, 22-floating gate layer, 23-ONO film layer, 24-control gate layer, 25-silicon nitride layer, 26-first side wall, 27-second side wall, 28-third side wall, 29-word line polysilicon, 30-word line protection layer, 41-first gate oxide layer, 42-second gate oxide layer, 50-polysilicon material layer, 51-low voltage gate. DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0016] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0017] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0018] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0019] The present application provides a method for preparing a semiconductor device, referring to Figure 1 , Figure 1 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention, wherein the method for preparing a semiconductor device comprises: First, perform step S1: refer to Figure 2 , Figure 2 It is a schematic diagram of a semiconductor structure after a flash memory unit is formed on a substrate in a flash memory device area according to an embodiment of the present application. A substrate 10 is provided, wherein the substrate 10 includes a flash memory device area, a high-voltage MOS device area, and a low-voltage MOS device area. A plurality of shallow trench isolation structures 11 are formed in the substrate 10, and the shallow trench isolation structures 11 are used to isolate different device areas. A flash memory unit is formed on the substrate in the flash memory device area.

[0020] Specifically, the shallow trench isolation structure 11 is used to isolate the flash memory device area, the high voltage MOS device area and the low voltage MOS device area.

[0021] In this embodiment, the flash memory unit is a split-gate flash memory unit.

[0022] Preferably, the flash memory unit at least includes: a third gate oxide layer 21, a floating gate layer 22, an ONO film layer 23, a control gate layer 24, a silicon nitride layer 25, a first sidewall 26, a second sidewall 27, a third sidewall 28, a word line polysilicon 29 and a word line protection layer 30, the third gate oxide layer 21, the floating gate layer 22, the ONO film layer 23, the control gate layer 24 and the silicon nitride layer 25 are stacked in sequence on the substrate 10 of the flash memory device area, a groove is formed in the floating gate layer 22, the ONO film layer 23, the control gate layer 24 and the silicon nitride layer 25, the first sidewall 26, the second sidewall 27 and the third sidewall 28 cover the sidewalls of the groove in sequence, the word line polysilicon 29 fills the groove, and the word line protection layer 30 covers the word line polysilicon 29.

[0023] In this embodiment, the first sidewall spacer 26 is made of silicon dioxide, the second sidewall spacer 27 is made of silicon nitride, and the third sidewall spacer 28 is made of silicon dioxide.

[0024] Furthermore, the word line protection layer 30 is made of silicon dioxide.

[0025] It is worth noting that the specific film layer structure of the flash memory unit may be the film layer structure of the flash memory unit in the E-Flash device of the conventional 40nm technology node, and the present application does not impose any limitation on the specific film layer structure of the flash memory unit.

[0026] Then, execute step S2: refer to Figure 3 , Figure 3 It is a schematic diagram of the semiconductor structure after forming the first gate oxide layer in an embodiment of the present application, wherein the first gate oxide layer 41 is formed, and the first gate oxide layer 41 covers the substrate 10 of the high-voltage MOS device area and the substrate 10 of the low-voltage MOS device area.

[0027] In this embodiment, the first gate oxide layer 41 is formed by a CVD process.

[0028] In other embodiments, the first gate oxide layer 41 is formed by a furnace process.

[0029] Next, execute step S3: refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after the first gate oxide layer of the low voltage MOS device region is etched away according to an embodiment of the present application, wherein the first gate oxide layer 41 of the low voltage MOS device region is etched away.

[0030] Specifically, step S3 may be: first, a first photoresist layer is coated on the flash memory unit in the flash memory device area, the first gate oxide layer 41 in the high-voltage MOS device area, and the first gate oxide layer 41 in the low-voltage MOS device area; then, a mask for opening the first gate oxide layer in the low-voltage MOS device area is used to open the first photoresist layer on the first gate oxide layer in the low-voltage MOS device area to form a patterned first photoresist layer; then, the patterned first photoresist layer is used as a mask to remove the first gate oxide layer 41 in the low-voltage MOS device area by a dry etching process; finally, the flash memory unit in the flash memory device area and the first photoresist layer on the first gate oxide layer 41 in the high-voltage MOS device area are removed.

[0031] Further, step S4 is performed: refer to Figure 5 , Figure 5 1 is a schematic diagram of a semiconductor structure after forming a second gate oxide layer according to an embodiment of the present application, wherein a second gate oxide layer 42 is formed, and the second gate oxide layer 42 covers the substrate 10 of the low-voltage MOS device region.

[0032] In this embodiment, the second gate oxide layer 42 is formed by a CVD process.

[0033] In other embodiments, the second gate oxide layer 42 is formed by a furnace process.

[0034] Preferably, the thickness of the second gate oxide layer 42 is smaller than the thickness of the first gate oxide layer 41 .

[0035] Next, execute step S5: refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the polysilicon material layer is formed in an embodiment of the present application, wherein a polysilicon material layer 50 is formed, and the polysilicon material layer 50 covers the second gate oxide layer 42 of the low-voltage MOS device area, the flash memory unit of the flash memory device area, and the first gate oxide layer 41 of the high-voltage MOS device area. At this time, the polysilicon material layer 50 on the high-voltage MOS device area serves as the high-voltage gate of the high-voltage MOS device area.

[0036] Preferably, the thickness of the high-voltage gate of the high-voltage MOS device region is greater than or equal to 1000 angstroms.

[0037] Preferably, the polysilicon material layer 50 is formed by a furnace tube process. Specifically, in the process of forming the polysilicon material layer 50 by a furnace tube process, the process temperature is 600°C to 800°C.

[0038] Finally, execute step S6: reference Figure 7 , Figure 7It is a schematic diagram of the semiconductor structure after etching a certain thickness of the polysilicon material layer in the low-voltage MOS device area according to an embodiment of the present application. The polysilicon material layer 50 of a certain thickness in the low-voltage MOS device area is etched to form a low-voltage gate 51 in the low-voltage MOS device area.

[0039] Preferably, the thickness of the low voltage gate 51 of the low voltage MOS device region is less than or equal to 800 angstroms.

[0040] In the present application, a first gate oxide layer is first formed on the substrate in the high-voltage MOS device area, and then the first gate oxide layer in the low-voltage MOS device area is removed and a second gate oxide layer is re-deposited on the low-voltage MOS device area, and then a thicker polysilicon material layer is formed in the high-voltage MOS device area and the low-voltage MOS device area to form a high-voltage gate, a mask is used to open the first gate oxide layer in the low-voltage MOS device area, and finally a polysilicon material layer of a certain thickness in the low-voltage MOS device area is back-etched, and the polysilicon material layer in the low-voltage MOS device area is thinned to a suitable thickness to form a low-voltage gate. It can be seen that the present application only requires a deposition process of the polysilicon material layer once, and there is no need to use a mask to open the polysilicon material layer in the low-voltage MOS device area. The low-voltage gate is directly formed by opening the first gate oxide layer in the low-voltage MOS device area. The photomask of the first gate oxide layer in the MOS device area can be used to backetch a certain thickness of the polysilicon material layer in the low-voltage MOS device area to form a low-voltage gate, thereby forming polysilicon material layers of different thicknesses in the high-voltage MOS device area and the low-voltage MOS device area, that is, a thicker polysilicon material layer is formed in the high-voltage MOS device area and a thinner polysilicon material layer is formed in the low-voltage MOS device area, which disguisedly thickens the gate thickness of the high-voltage MOS device area in the E-Flash device of the 40nm technology node, and avoids the situation where the thinner gate polysilicon of the high-voltage MOS device is accidentally damaged by the subsequent LDD ion implantation process. The preparation method of the semiconductor device provided by the present application is simple, avoids the cumbersome process flow, and reduces the manufacturing cost.

[0041] For further reference, Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after removing the polysilicon material layer on the flash memory unit of the flash memory device area in an embodiment of the present application. After etching a certain thickness of the polysilicon material layer 50 in the low-voltage MOS device area to form a low-voltage gate 51 in the low-voltage MOS device area, the preparation method of the semiconductor device may also include: removing the polysilicon material layer 50 on the flash memory unit of the flash memory device area.

[0042] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A substrate is provided, the substrate comprising a flash memory device area, a high voltage MOS device area and a low voltage MOS device area, a plurality of shallow trench isolation structures are formed in the substrate, the shallow trench isolation structures are used to isolate different device areas, and a flash memory unit is formed on the substrate of the flash memory device area; forming a first gate oxide layer, wherein the first gate oxide layer covers the substrate of the high-voltage MOS device region and the substrate of the low-voltage MOS device region; Etching and removing the first gate oxide layer of the low voltage MOS device region; forming a second gate oxide layer, wherein the second gate oxide layer covers the substrate of the low voltage MOS device region; Forming a polysilicon material layer, wherein the polysilicon material layer covers the second gate oxide layer of the low voltage MOS device area, the flash memory unit of the flash memory device area, and the first gate oxide layer of the high voltage MOS device area, so as to form a high voltage gate in the high voltage MOS device area; A polysilicon material layer of a certain thickness in the low voltage MOS device region is etched to form a low voltage gate in the low voltage MOS device region.

2. The method for preparing a semiconductor device according to claim 1, wherein: The polysilicon material layer is formed by a furnace tube process.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: In the process of forming the polysilicon material layer by adopting the furnace tube process, the process temperature is 600° C. to 800° C.

4. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the second gate oxide layer is smaller than the thickness of the first gate oxide layer.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: After etching a certain thickness of the polysilicon material layer in the low voltage MOS device region to form a low voltage gate in the low voltage MOS device region, the method for preparing the semiconductor device further includes: The polysilicon material layer on the flash memory cells of the flash memory device area is removed.

6. The method for preparing a semiconductor device according to claim 1, wherein: The flash memory unit is a split-gate flash memory unit.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The flash memory unit at least includes: a third gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer, a silicon nitride layer, a first sidewall, a second sidewall, a third sidewall, a word line polysilicon and a word line protection layer. The third gate oxide layer, the floating gate layer, the ONO film layer, the control gate layer and the silicon nitride layer are stacked in sequence on the substrate of the flash memory device area. Grooves are formed in the floating gate layer, the ONO film layer, the control gate layer and the silicon nitride layer. The first sidewall, the second sidewall and the third sidewall cover the sidewalls of the grooves in sequence. The word line polysilicon fills the grooves, and the word line protection layer covers the word line polysilicon.

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