Method for preparing semiconductor device

Abstract

This application provides a method for fabricating a semiconductor device. First, a first gate oxide layer is formed on a substrate in the high-voltage MOS device region. Then, the first gate oxide layer in the low-voltage MOS device region is removed, and a second gate oxide layer is re-deposited. Next, polysilicon material layers are formed on both the low-voltage and high-voltage MOS device regions. Finally, a photomask that opens the first gate oxide layer in the low-voltage MOS device region is used to etch back a polysilicon material layer of a certain thickness in the low-voltage MOS device region. This application only requires one deposition of the polysilicon material layer, eliminating the need for a new photomask. By directly using a photomask that etches back the first gate oxide layer, a polysilicon material layer of a certain thickness in the low-voltage MOS device region can be etched back to form a low-voltage gate. This results in polysilicon material layers of different thicknesses in the high-voltage and low-voltage MOS device regions, avoiding accidental damage to the thinner gate polysilicon of the high-voltage MOS device by subsequent LDD ion implantation processes.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for preparing a semiconductor device. Background Technology

[0002] The gate thickness of high-voltage MOS devices (such as 5V MOS devices) in the 55nm technology node embedded flash (E-Flash) device platform is 1000 angstroms.

[0003] To shorten the R&D cycle, the high-voltage MOS devices (e.g., 5V MOS devices) in the 40nm E-Flash device platform use the same process flow as the high-voltage MOS devices (e.g., 5V MOS devices) in the 55nm E-Flash device platform. Specifically, due to the use of the same process flow, the gate polysilicon thickness of the high-voltage MOS devices (e.g., 5V MOS devices) in the 40nm E-Flash device platform is the same as that of the gate polysilicon thickness of the low-voltage MOS devices (e.g., 1.1V MOS devices) / medium-voltage MOS devices (e.g., 2.5V MOS devices), which typically needs to be thinned to 800 angstroms. However, as the gate polysilicon thickness of high-voltage MOS devices (such as 5V MOS devices) is reduced from 1000 angstroms to 800 angstroms, this limits the adjustment of lightly doped drain (LDD) ion implantation in the substrate. LDD ion implantation can easily damage the gate polysilicon of high-voltage MOS devices (such as 5V MOS devices) at the 40nm technology node. It can be seen that the current fabrication process of E-Flash devices at the 40nm technology node is not fully compatible with the fabrication process of high-voltage MOS devices in E-Flash devices at the 55nm technology node. Summary of the Invention

[0004] This application provides a method for fabricating semiconductor devices that can solve the problem of the gate polysilicon of high-voltage MOS devices in the current 40nm E-Flash device platform being accidentally damaged by the subsequent LDD ion implantation process.

[0005] This application provides a method for fabricating a semiconductor device, including:

[0006] A substrate is provided, the substrate comprising a flash memory device region, a high-voltage MOS device region and a low-voltage MOS device region, a plurality of shallow trench isolation structures are formed in the substrate, the shallow trench isolation structures are used to isolate different device regions, and flash memory cells are formed on the substrate of the flash memory device region;

[0007] A first gate oxide layer is formed, which covers the substrate of the high-voltage MOS device region and the substrate of the low-voltage MOS device region.

[0008] Etching removes the first gate oxide layer of the low-voltage MOS device region;

[0009] A second gate oxide layer is formed, which covers the substrate of the low-voltage MOS device region;

[0010] A polysilicon material layer is formed, which covers the second gate oxide layer of the low-voltage MOS device region, the flash memory cell of the flash memory device region, and the first gate oxide layer of the high-voltage MOS device region, so as to form a high-voltage gate in the high-voltage MOS device region.

[0011] A polysilicon material layer of a certain thickness is etched in the low-voltage MOS device region to form a low-voltage gate in the low-voltage MOS device region.

[0012] Optionally, in the method for fabricating the semiconductor device, the polycrystalline silicon material layer is formed using a furnace tube process.

[0013] Optionally, in the method for fabricating the semiconductor device, the process temperature is 600°C to 800°C during the formation of the polycrystalline silicon material layer using a furnace tube process.

[0014] Optionally, in the method for fabricating the semiconductor device, the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0015] Optionally, in the method for fabricating the semiconductor device, after etching a polysilicon material layer of a certain thickness in the low-voltage MOS device region to form a low-voltage gate in the low-voltage MOS device region, the method for fabricating the semiconductor device further includes:

[0016] Remove the polysilicon material layer on the flash memory cell of the flash memory device region.

[0017] Optionally, in the method for fabricating the semiconductor device, the flash memory cell is a grid-type flash memory cell.

[0018] Optionally, in the method for fabricating the semiconductor device, the flash memory cell includes at least: a third gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer, a silicon nitride layer, a first sidewall, a second sidewall, a third sidewall, word line polysilicon, and a word line protection layer. The third gate oxide layer, the floating gate layer, the ONO film layer, the control gate layer, and the silicon nitride layer are sequentially stacked on the substrate of the flash memory device region. Trenches are formed in the floating gate layer, the ONO film layer, the control gate layer, and the silicon nitride layer. The first sidewall, the second sidewall, and the third sidewall sequentially cover the sidewalls of the trenches. The word line polysilicon fills the trenches, and the word line protection layer covers the word line polysilicon.

[0019] The technical solution of this application has at least the following advantages:

[0020] In this application, a first gate oxide layer is first formed on the substrate of the high-voltage MOS device region. Then, the first gate oxide layer of the low-voltage MOS device region is removed, and a second gate oxide layer is deposited again on the low-voltage MOS device region. Next, a relatively thick polysilicon material layer is formed in both the high-voltage and low-voltage MOS device regions to form the high-voltage gate. A photomask is used to open the first gate oxide layer of the low-voltage MOS device region. Finally, a certain thickness of the polysilicon material layer in the low-voltage MOS device region is etched back to thin it to a suitable thickness to form the low-voltage gate. Therefore, this application only requires one polysilicon material layer deposition process and does not require a separate process to open the low-voltage MOS device region. The photomask for the polysilicon material layer can be directly used by opening the first gate oxide layer of the low-voltage MOS device region. This allows for the etching back of a certain thickness of polysilicon material layer in the low-voltage MOS device region to form a low-voltage gate. This results in the formation of polysilicon material layers of different thicknesses in the high-voltage MOS device region and the low-voltage MOS device region. Specifically, a thicker polysilicon material layer is formed in the high-voltage MOS device region and a thinner polysilicon material layer is formed in the low-voltage MOS device region. This avoids the situation where the thinner gate polysilicon of the high-voltage MOS device is accidentally damaged by the subsequent LDD ion implantation process. The semiconductor device fabrication method provided in this application is simple, avoids complicated process flow, and reduces manufacturing costs. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0023] Figures 2-8 This is a schematic diagram of the semiconductor structure in each process step of the semiconductor device fabrication according to an embodiment of the present invention;

[0024] The reference numerals in the attached figures are explained as follows:

[0025] 10-Substrate, 11-Shallow trench isolation structure, 21-Third gate oxide layer, 22-Floating gate layer, 23-ONO film layer, 24-Control gate layer, 25-Silicon nitride layer, 26-First sidewall, 27-Second sidewall, 28-Third sidewall, 29-Word line polysilicon, 30-Word line protection layer, 41-First gate oxide layer, 42-Second gate oxide layer, 50-Polysilicon material layer, 51-Low voltage gate. Detailed Implementation

[0026] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0030] This application provides a method for fabricating a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor device includes:

[0031] First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of the semiconductor structure after forming flash memory cells on the substrate of the flash memory device region according to an embodiment of this application. A substrate 10 is provided, the substrate 10 includes a flash memory device region, a high voltage MOS device region and a low voltage MOS device region. A plurality of shallow trench isolation structures 11 are formed in the substrate 10. The shallow trench isolation structures 11 are used to isolate different device regions. Flash memory cells are formed on the substrate of the flash memory device region.

[0032] Specifically, the shallow trench isolation structure 11 is used to isolate the flash memory device area, the high-voltage MOS device area, and the low-voltage MOS device area.

[0033] In this embodiment, the flash memory cell is a grid-type flash memory cell.

[0034] Preferably, the flash memory cell includes at least: a third gate oxide layer 21, a floating gate layer 22, an ONO film layer 23, a control gate layer 24, a silicon nitride layer 25, a first sidewall 26, a second sidewall 27, a third sidewall 28, a word line polysilicon 29, and a word line protection layer 30. The third gate oxide layer 21, the floating gate layer 22, the ONO film layer 23, the control gate layer 24, and the silicon nitride layer 25 are sequentially stacked on the substrate 10 of the flash memory device region. Trenches are formed in the floating gate layer 22, the ONO film layer 23, the control gate layer 24, and the silicon nitride layer 25. The first sidewall 26, the second sidewall 27, and the third sidewall 28 sequentially cover the sidewalls of the trenches. The word line polysilicon 29 fills the trenches, and the word line protection layer 30 covers the word line polysilicon 29.

[0035] In this embodiment, the first sidewall 26 is made of silicon dioxide, the second sidewall 27 is made of silicon nitride, and the third sidewall 28 is made of silicon dioxide.

[0036] Furthermore, the word line protective layer 30 is made of silicon dioxide.

[0037] It is worth noting that the specific film layer structure of the flash memory cell can be the film layer structure of the flash memory cell in a conventional 40nm technology node E-Flash device, and this application does not impose any limitation on the specific film layer structure of the flash memory cell.

[0038] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the first gate oxide layer according to an embodiment of this application. The first gate oxide layer 41 is formed, and the first gate oxide layer 41 covers the substrate 10 of the high voltage MOS device region and the substrate 10 of the low voltage MOS device region.

[0039] In this embodiment, the first gate oxide layer 41 is formed using a CVD process.

[0040] In other embodiments, the first gate oxide layer 41 is formed using a furnace tube process.

[0041] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after etching away the first gate oxide layer of the low-voltage MOS device region according to an embodiment of this application. The first gate oxide layer 41 of the low-voltage MOS device region is etched away.

[0042] Specifically, step S3 can be as follows: First, a first photoresist layer is coated on the flash memory cell in the flash memory device region, the first gate oxide layer 41 in the high voltage MOS device region, and the first gate oxide layer 41 in the low voltage MOS device region. Then, the first photoresist layer on the first gate oxide layer in the low voltage MOS device region is opened using a photomask to open the first gate oxide layer in the low voltage MOS device region to form a patterned first photoresist layer. Next, using the patterned first photoresist layer as a mask, the first gate oxide layer 41 in the low voltage MOS device region is etched away using a dry etching process. Finally, the first photoresist layer on the flash memory cell in the flash memory device region and the first gate oxide layer 41 in the high voltage MOS device region is removed.

[0043] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the second gate oxide layer according to an embodiment of this application. The second gate oxide layer 42 is formed and covers the substrate 10 of the low-voltage MOS device region.

[0044] In this embodiment, the second gate oxide layer 42 is formed using a CVD process.

[0045] In other embodiments, a furnace tube process is used to form the second gate oxide layer 42.

[0046] Preferably, the thickness of the second gate oxide layer 42 is less than the thickness of the first gate oxide layer 41.

[0047] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the polysilicon material layer in an embodiment of this application. A polysilicon material layer 50 is formed, which covers the second gate oxide layer 42 of the low-voltage MOS device region, the flash memory cell of the flash memory device region, and the first gate oxide layer 41 of the high-voltage MOS device region. At this time, the polysilicon material layer 50 on the high-voltage MOS device region serves as the high-voltage gate of the high-voltage MOS device region.

[0048] Preferably, the thickness of the high-voltage gate in the high-voltage MOS device region is greater than or equal to 1000 angstroms.

[0049] Preferably, the polycrystalline silicon material layer 50 is formed using a furnace tube process. Specifically, during the formation of the polycrystalline silicon material layer 50 using the furnace tube process, the process temperature is 600℃~800℃.

[0050] Finally, proceed to step S6: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after etching a polysilicon material layer of a certain thickness in the low-voltage MOS device region according to an embodiment of this application. The polysilicon material layer 50 of a certain thickness in the low-voltage MOS device region is etched to form a low-voltage gate 51 in the low-voltage MOS device region.

[0051] Preferably, the thickness of the low-voltage gate 51 in the low-voltage MOS device region is less than or equal to 800 angstroms.

[0052] In this application, a first gate oxide layer is first formed on the substrate of the high-voltage MOS device region. Then, the first gate oxide layer of the low-voltage MOS device region is removed, and a second gate oxide layer is deposited again on the low-voltage MOS device region. Next, a relatively thick polysilicon material layer is formed in both the high-voltage and low-voltage MOS device regions to form the high-voltage gate. A photomask is used to open the first gate oxide layer of the low-voltage MOS device region. Finally, a certain thickness of the polysilicon material layer in the low-voltage MOS device region is etched back to thin the polysilicon material layer in the low-voltage MOS device region to a suitable thickness to form the low-voltage gate. Therefore, this application only requires one polysilicon material layer deposition process and does not require a separate photomask to open the polysilicon material layer of the low-voltage MOS device region. It directly uses the low-voltage gate opening process. The photomask of the first gate oxide layer in the MOS device region can be used to etch back a certain thickness of polysilicon material layer in the low-voltage MOS device region to form a low-voltage gate. This results in polysilicon material layers of different thicknesses in the high-voltage MOS device region and the low-voltage MOS device region. Specifically, a thicker polysilicon material layer is formed in the high-voltage MOS device region and a thinner polysilicon material layer is formed in the low-voltage MOS device region. This effectively increases the gate thickness of the high-voltage MOS device region in the 40nm E-Flash device and avoids the situation where the thinner gate polysilicon of the high-voltage MOS device is accidentally damaged by the subsequent LDD ion implantation process. The semiconductor device fabrication method provided in this application is simple, avoids complicated process flow, and reduces manufacturing costs.

[0053] For further reference, Figure 8 , Figure 8This is a schematic diagram of the semiconductor structure after removing the polysilicon material layer on the flash memory cell of the flash memory device region according to an embodiment of this application. After etching a polysilicon material layer 50 of a certain thickness in the low-voltage MOS device region to form a low-voltage gate 51 in the low-voltage MOS device region, the method for fabricating the semiconductor device may further include: removing the polysilicon material layer 50 on the flash memory cell of the flash memory device region.

[0054] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a flash memory device region, a high-voltage MOS device region and a low-voltage MOS device region, a plurality of shallow trench isolation structures are formed in the substrate, the shallow trench isolation structures are used to isolate different device regions, and flash memory cells are formed on the substrate of the flash memory device region; A first gate oxide layer is formed, which covers the substrate of the high-voltage MOS device region and the substrate of the low-voltage MOS device region. Etching removes the first gate oxide layer of the low-voltage MOS device region; A second gate oxide layer is formed, which covers the substrate of the low-voltage MOS device region; A polysilicon material layer is formed, which covers the second gate oxide layer of the low-voltage MOS device region, the flash memory cell of the flash memory device region, and the first gate oxide layer of the high-voltage MOS device region, so as to form a high-voltage gate in the high-voltage MOS device region. A polysilicon material layer of a certain thickness is etched in the low-voltage MOS device region to form a low-voltage gate in the low-voltage MOS device region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The polycrystalline silicon material layer is formed using a furnace tube process.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, During the formation of the polycrystalline silicon material layer using the furnace tube process, the process temperature is 600℃~800℃.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, After etching a polysilicon material layer of a certain thickness in the low-voltage MOS device region to form a low-voltage gate in the low-voltage MOS device region, the method for fabricating the semiconductor device further includes: Remove the polysilicon material layer on the flash memory cell of the flash memory device region.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The flash memory cell is a grid-type flash memory cell.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The flash memory cell includes at least: a third gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer, a silicon nitride layer, a first sidewall, a second sidewall, a third sidewall, word line polysilicon, and a word line protection layer. The third gate oxide layer, the floating gate layer, the ONO film layer, the control gate layer, and the silicon nitride layer are stacked sequentially on the substrate of the flash memory device region. Trenches are formed in the floating gate layer, the ONO film layer, the control gate layer, and the silicon nitride layer. The first sidewall, the second sidewall, and the third sidewall sequentially cover the sidewalls of the trenches. The word line polysilicon fills the trenches, and the word line protection layer covers the word line polysilicon.

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