Method for improving one-time programmable performance

Abstract

The invention provides a method for improving one-time programmable performance, which comprises the following steps of: providing a substrate, forming shallow trench isolation on the substrate to define an active region, forming a gate structure on the active region, forming a gate oxide layer and a gate layer on the gate oxide layer on the active region, forming an active region and a drain region on the substrate at two sides of the gate structure by utilizing ion implantation, a side wall is formed on the side wall of the gate structure; forming an etching stop layer, and depositing an HARP layer on the etching stop layer; forming an O3-TEOS layer by using a deposition method; and forming a contact for leading out the source region and the drain region. The one-time programmable data retention performance of the device prepared by the invention is obviously improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving one-time programmable performance. Background Art

[0002] The existing BCD (bipolar CMOS DMOS platform OTP (One Time Programmable) performance comparison margin, Ea (electron volt unit) 1.21. The interlayer dielectric layer is mainly HDP (high density plasma process) + PETEOS (plasma enhanced tetraethyl orthosilicate layer) and HARP (high aspect ratio plasma) + PETEOS (plasma enhanced tetraethyl orthosilicate layer). The high concentration plasma process is easy to damage the gate oxide due to the high plasma characteristics, the charge storage capacity is reduced, and the one-time programmable performance is poor; the HARP film layer is easy to affect the subsequent process due to the large tensile stress (unable to pass goods / fragmentation, etc.).

[0003] The process flow of the prior art includes:

[0004] Step 1: Please refer to Figure 1 , providing a substrate 101, a shallow trench isolation 102 is formed on the substrate 101 to define an active area, a gate structure is formed on the active area, the gate structure is composed of a gate oxide layer 103 and a gate layer 104 located on the gate oxide layer 103, the material of the gate layer 104 is usually polysilicon, a sidewall 105 is formed on the sidewall of the gate structure, an active region and a drain region are formed on the substrate 101 on both sides of the gate structure by ion implantation, and a metal silicide 110 is formed in the contact hole region on the active area;

[0005] Step 2: forming an etch stop layer 106, forming Figure 2 The structure shown in FIG. 1 is formed by forming a HARP layer 107 on the etch stop layer 106 to form a Figure 8 The structure shown;

[0006] Step 3: Form a HDP (high density plasma) layer 107 covering the etch stop layer 106 by deposition and grinding, and then form a PETEOS layer 108 on the HDP layer 107 to form a Figure 3 The structure shown;

[0007] Step 4: forming a contact 109 for leading out the source and drain regions, forming Figure 4 The structure shown.

[0008] In order to solve the above problems, a new method for improving the performance of one-time programmability needs to be proposed. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for improving the one-time programmable performance, which is used to solve the problems in the prior art that the high-concentration plasma process is prone to damage to the gate oxide due to the high plasma characteristics, the charge storage capacity is reduced, and the one-time programmable performance is poor; the HARP film layer is prone to being unable to pass goods / fragmentation due to the large tensile stress.

[0010] To achieve the above objectives and other related objectives, the present invention provides a method for improving one-time programmable performance, comprising:

[0011] Step 1, providing a substrate, wherein shallow trench isolation is formed on the substrate to define an active area, a gate structure is formed on the active area, the gate structure is composed of a gate oxide layer and a gate layer located on the gate oxide layer, an active region and a drain region are formed on the substrate on both sides of the gate structure by ion implantation, and a sidewall is formed on the sidewall of the gate structure;

[0012] Step 2: forming an etch stop layer, and depositing a HARP layer on the etch stop layer;

[0013] Step 3: forming an O3-TEOS layer by a deposition method;

[0014] Step 4: forming contacts for leading out the source and drain regions.

[0015] Preferably, metal silicide is formed in the contact hole region on the active area in step one.

[0016] Preferably, the etch stop layer in step 2 is formed by chemical vapor deposition.

[0017] Preferably, the etching stop layer in step 2 is composed of a SION layer and a nitride layer stacked in sequence from bottom to top.

[0018] Preferably, the HARP layer in step 2 is formed by chemical vapor deposition.

[0019] Preferably, the thickness of the HARP layer in step 2 is 800 to 1000 angstroms.

[0020] Preferably, the O3-TEOS layer in step three is formed by chemical vapor deposition.

[0021] Preferably, the thickness of the O3-TEOS layer in step three is 7000 to 8000 angstroms.

[0022] Preferably, step three also includes grinding the upper surface of the O3-TEOS layer to make it flat.

[0023] Preferably, the grinding method in step three is chemical mechanical planarization grinding.

[0024] As described above, the method for improving one-time programmable performance of the present invention has the following beneficial effects:

[0025] The one-time programmable data retention performance of the device prepared by the invention is significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of the initial device structure of the prior art;

[0027] Figure 2 A schematic diagram of forming an etch stop layer in the prior art is shown;

[0028] Figure 3 Shown is a schematic diagram of forming a HDP layer and a PETEOS layer in the prior art;

[0029] Figure 4 Shown is a schematic diagram of forming contacts in the prior art;

[0030] Figure 5 Shown is a schematic diagram of the process flow of the present invention;

[0031] Figure 6 Shown is a schematic diagram of the initial device structure of the present invention;

[0032] Figure 7 It is a schematic diagram of forming an etch stop layer according to the present invention;

[0033] Figure 8 Shown is a schematic diagram of forming a HARP layer according to the present invention;

[0034] Fig. 9 Shown is a schematic diagram of the O3-TEOS layer of the present invention;

[0035] Fig.10 Shown is a schematic diagram of forming a contact member of the present invention;

[0036] Fig.11 It is a schematic diagram showing the improvement effect of Ea (electron volt) of the present invention. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] See also Figure 5The present invention provides a method for improving one-time programmable performance, comprising:

[0039] Step 1: Please refer to Figure 6 , providing a substrate 201, a shallow trench isolation 202 is formed on the substrate 201 to define an active area, a gate structure is formed on the active area, the gate structure is composed of a gate oxide layer 203 and a gate layer 204 located on the gate oxide layer 203, the material of the gate layer 204 is usually polysilicon, an active region and a drain region are formed on the substrate 201 on both sides of the gate structure by ion implantation, and a sidewall 205 is formed on the sidewall of the gate structure;

[0040] In an embodiment of the present invention, a metal silicide 210 is formed in the contact hole region on the active region in step 1, and the material of the metal silicide 210 may be nickel silicide.

[0041] Step 2: forming an etch stop layer 206, such as Figure 7 The structure shown in FIG. 1 is a HARP layer 207 deposited on the etch stop layer 206 to form a Figure 8 The structure shown;

[0042] In an embodiment of the present invention, the etch stop layer 206 in step 2 is formed by chemical vapor deposition.

[0043] In an embodiment of the present invention, the etch stop layer 206 in step 2 is composed of a SION layer 2061 and a nitride layer 2062 stacked sequentially from bottom to top. In other embodiments, the material of the etch stop layer 206 may also be replaced by other known materials.

[0044] In an embodiment of the present invention, the HARP layer 207 in step 2 is formed by chemical vapor deposition.

[0045] In the embodiment of the present invention, the thickness of the HARP layer 207 in step 2 is 800 to 1000 angstroms. The HARP layer 207 is used for filling small line widths, and the HARP layer 207 has good filling performance.

[0046] Step 3: Form an O3-TEOS layer 208 by deposition. Fig. 9The structure shown in the figure; this interlayer dielectric layer adopts a method of combining a HARP layer 207 with an O3-TEOS layer 208 to significantly improve the OTP performance. The HARP layer 207 and the O3-TEOS layer 208 are formed by thermal reaction. The HARP layer 207 can be applied to a high aspect ratio structure, but the deposition speed is slow. The O3-TEOS layer 208 has the characteristics of fast deposition speed, but the filling speed is worse than the HARP layer 207. A small amount of HARP layer 207 is first deposited for filling, and the O3-TEOS layer 208 is used for deposition. The combination of the HARP layer 207 and the O3-TEOS layer 208 not only avoids the damage of the plasma to the gate oxide layer 203 in the high-density plasma process, but also reduces the problem of fragmentation caused by the large tensile stress of the HARP layer 207;

[0047] In an embodiment of the present invention, the O3-TEOS layer 208 in step three is formed by chemical vapor deposition.

[0048] In an embodiment of the present invention, the thickness of the O3-TEOS layer 208 in step three is 7000 to 8000 angstroms.

[0049] In an embodiment of the present invention, step three further includes grinding the upper surface of the O3-TEOS layer 208 to make it flat.

[0050] In an embodiment of the present invention, the polishing method in step three is chemical mechanical planarization polishing.

[0051] Step 4: forming a contact 209 for leading out the source and drain regions, forming Fig.10 The structure shown.

[0052] Specifically, a photoresist layer may be formed on the O3-TEOS layer 208, the photoresist layer may be opened by photolithography to define a formation area for the contact 209, then a contact hole may be formed by etching, and then the contact hole may be filled with metal to form the contact 209. The contact 209 may include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof.

[0053] See also Fig.11 The method of using HARP layer 207 and O3-TEOS layer 208 to fill the smallest space in the chip is complete and has no gaps or voids. The one-time programmable data retention performance is significantly improved, and Ea is increased by 25.62%, meeting customer requirements (1.52>1.20), and the service life is significantly improved.

[0054] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] In summary, the one-time programmable data retention performance of the device produced by the present invention is significantly improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0056] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving one-time programmable performance, characterized in that: At least: Step 1, providing a substrate, wherein shallow trench isolation is formed on the substrate to define an active area, a gate structure is formed on the active area, the gate structure is composed of a gate oxide layer and a gate layer located on the gate oxide layer, an active region and a drain region are formed on the substrate on both sides of the gate structure by ion implantation, and a sidewall is formed on the sidewall of the gate structure; Step 2: forming an etch stop layer, and depositing a HARP layer on the etch stop layer; Step 3: forming an O3-TEOS layer by a deposition method; Step 4: forming contacts for leading out the source and drain regions.

2. The method for improving one-time programmable performance according to claim 1, characterized in that: In step 1, metal silicide is formed in the contact hole region on the active region.

3. The method for improving one-time programmable performance according to claim 1, characterized in that: The etching stop layer in step 2 is formed by chemical vapor deposition.

4. The method for improving one-time programmable performance according to claim 1, characterized in that: The etching stop layer in step 2 is composed of a SION layer and a nitride layer stacked in sequence from bottom to top.

5. The method for improving one-time programmable performance according to claim 1, characterized in that: The HARP layer in step 2 is formed by chemical vapor deposition.

6. The method for improving one-time programmable performance according to claim 1, characterized in that: The thickness of the HARP layer in step 2 is 800 to 1000 angstroms.

7. The method for improving one-time programmable performance according to claim 1, characterized in that: The O3-TEOS layer in step three is formed by chemical vapor deposition.

8. The method for improving one-time programmable performance according to claim 1, characterized in that: The thickness of the O3-TEOS layer in step 3 is 7000 to 8000 angstroms.

9. The method for improving one-time programmable performance according to claim 1, characterized in that: Step three also includes grinding the upper surface of the O3-TEOS layer to make it flat.

10. The method for improving one-time programmable performance according to claim 1, characterized in that: The grinding method in step three is chemical mechanical planarization grinding.

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