Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device includes: a gate stack structure including interlayer insulating layers and conductive layers alternately stacked with each other; a first plug pattern and a second plug pattern extending in a vertical direction corresponding to a stacking direction of the gate stack structure; a first data storage layer disposed between the first plug pattern and the conductive layer and a second data storage layer disposed between the second plug pattern and the conductive layer; an isolation structure extending in a vertical direction and separating the first plug pattern and the second plug pattern from each other; and insulating patterns disposed between the first data storage layers adjacent to each other in the vertical direction and between the second data storage layers adjacent to each other in the vertical direction.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] A nonvolatile memory device retains stored data regardless of power on / off conditions. An increase in the integration density of a two-dimensional nonvolatile memory device in which memory cells are formed in a single layer over a substrate has recently been limited. Therefore, a three-dimensional nonvolatile memory device in which memory cells are stacked in a vertical direction over a substrate has been proposed.

[0003] A three-dimensional nonvolatile memory device may include interlayer insulating layers and gate electrodes alternately stacked with each other, and a channel layer passing therethrough, wherein memory cells are stacked along the channel layer. Various structures and manufacturing methods have been developed to improve the operational reliability of the three-dimensional nonvolatile memory device. Summary of the invention

[0004] According to an embodiment, a semiconductor device may include: a gate stack structure including interlayer insulating layers and conductive layers alternately stacked with each other; a first plug pattern and a second plug pattern extending in a vertical direction corresponding to a stacking direction of the gate stack structure; a first data storage layer disposed between the first plug pattern and the conductive layer and a second data storage layer disposed between the second plug pattern and the conductive layer; an isolation structure extending in the vertical direction and separating the first plug pattern and the second plug pattern from each other; and an insulating pattern disposed between first data storage layers adjacent to each other in the vertical direction and between second data storage layers adjacent to each other in the vertical direction.

[0005] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a hole passing through at least a portion of a stacked structure, the stacked structure including a first material layer and a second material layer alternately stacked on each other; forming a recessed area by etching a side wall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the recessed area; forming an insulating pattern that protrudes further than the side wall of the second material layer in a direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between insulating patterns adjacent to each other in a vertical direction; forming a plug pattern extending in a vertical direction in the hole; and forming an isolation structure that passes through the plug pattern in a vertical direction and separates the plug pattern into a first plug pattern and a second plug pattern.

[0006] According to an embodiment, a method for manufacturing a semiconductor memory device may include: forming a hole passing through at least a portion of a stacked structure, the stacked structure including a first material layer and a second material layer alternately stacked on each other; forming a protrusion pattern on a side wall of the second material layer exposed by the hole; forming an insulating pattern that protrudes further than the side wall of the protrusion pattern in a direction of the hole in a space between the protrusion patterns adjacent to each other in a vertical direction; forming a data storage layer in the space between the insulating patterns adjacent to each other in the vertical direction; forming a plug pattern extending in the vertical direction in the hole; and forming an isolation structure that passes through the plug pattern in the vertical direction and separates the plug pattern into a first plug pattern and a second plug pattern.

[0007] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a hole passing through at least a portion of a stacked structure, the stacked structure including a first material layer and a second material layer alternately stacked with each other; forming an insulating pattern on a side wall of the first material layer exposed by the hole; forming a data storage layer in a space between the insulating patterns adjacent to each other in a vertical direction; forming a plug pattern extending in a vertical direction in the hole; and forming an isolation structure, the isolation structure passing through the plug pattern in the vertical direction and separating the plug pattern into a first plug pattern and a second plug pattern.

[0008] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a hole having an elliptical shape passing through at least a portion of a stacked structure, the stacked structure including a first material layer and a second material layer alternately stacked with each other; forming a recessed area by etching a side wall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the recessed area; forming an insulating pattern that protrudes further than the side wall of the second material layer in the direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other in a vertical direction; sequentially forming a tunnel isolation layer and a channel layer extending in a vertical direction on the side wall of the hole, wherein a thickness of a cross section of the channel layer in a first horizontal direction is greater than a thickness of a cross section in a second horizontal direction substantially perpendicular to the first horizontal direction; forming a first channel layer and a second channel layer by etching the channel layer to a predetermined thickness so that the channel layer is divided into a first channel layer and a second channel layer in the first horizontal direction, and exposing a portion of the tunnel isolation layer between the first channel layer and the second channel layer; and sequentially etching the exposed portions of the data storage layer and the tunnel isolation layer to divide the tunnel isolation layer and the data storage layer into two portions in the first horizontal direction.

[0009] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a stacked structure including a first material layer and a second material layer alternately stacked on each other; forming a first isolation pattern that passes through the stacked structure in a vertical direction and extends in a first horizontal direction; forming a hole that passes through the stacked structure and the first isolation pattern; forming a recessed area by etching the sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the recessed area; forming an insulating pattern that protrudes further than the sidewall of the second material layer in the direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other in the vertical direction; sequentially forming a tunnel isolation layer, a channel layer, and a core insulation layer extending in the vertical direction on the sidewall of the hole; and forming a second isolation pattern that passes through the tunnel isolation layer, the channel layer, and the core insulation layer in the vertical direction and separates the channel layer into a first channel layer and a second channel layer.

[0010] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a stacked structure including a first material layer and a second material layer alternately stacked on each other; forming a first isolation pattern passing through the stacked structure in a vertical direction and extending in a first horizontal direction; forming a hole passing through the stacked structure and the first isolation pattern; forming a first recessed area by etching the sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the first recessed area; forming an insulating pattern that protrudes further than the sidewall of the second material layer in the direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other in the vertical direction; sequentially forming a tunnel isolation layer, a channel layer, and a core insulating layer extending in the vertical direction on the sidewall of the hole; forming a second recessed area by removing the first isolation pattern; and separating the channel layer into a first channel layer and a second channel layer spaced apart from each other by etching the tunnel isolation layer and the channel layer exposed through the second recessed area.

[0011] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a stacked structure including a first material layer and a second material layer alternately stacked on each other; forming a first isolation pattern passing through the stacked structure in a vertical direction and extending in a first horizontal direction; forming a hole passing through the stacked structure and the first isolation pattern; forming a first recessed area by etching the sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the first recessed area; forming an insulating pattern that protrudes further than the sidewall of the second material layer in the direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other in the vertical direction; sequentially forming a tunnel isolation layer, a channel layer, and a core insulating layer extending in the vertical direction on the sidewall of the hole; forming a second recessed area by removing the first isolation pattern; and forming a channel isolation structure by performing a wet oxidation process through the second recessed area to oxidize a portion of the channel layer adjacent to the second recessed area.

[0012] According to an embodiment, a method for manufacturing a semiconductor device may include: forming a hole passing through at least a portion of a stacked structure, the stacked structure including a first material layer and a second material layer alternately stacked with each other; forming a first isolation pattern and a second isolation pattern at an interface between a first side wall and a second side wall opposite to each other in a contact hole and extending in a vertical direction; forming an insulating pattern on a side wall of the first material layer exposed through the hole; removing the first isolation pattern and the second isolation pattern and forming a data storage layer in a space between the insulating patterns adjacent to each other in a vertical direction on the first side wall and the second side wall; sequentially forming a tunnel isolation layer, a channel layer, and a core insulating layer on the side wall of the hole; performing an etching process to expose the side wall of the stacked structure; forming a recessed area by removing the exposed portion of the second material layer; and forming a channel isolation structure by performing a wet oxidation process through the recessed area to oxidize a portion of the channel layer adjacent to the recessed area. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A , Figure 1B and Figure 1C are cross-sectional views and plan views for illustrating a semiconductor device according to an embodiment of the present disclosure;

[0014] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H and Fig.2I are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0015] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0016] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a cross-sectional view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0017] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig.5I , Figure 5J , Figure 5K , Figure 5L and Figure 5M are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0018] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H , Fig.6I , Figure 6J and Figure 6K are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0019] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F is a plan view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0020] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F is a plan view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0021] Fig. 9A, Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Fig.9O , Figure 9P , Figure 9Q , Figure 9R , Figure 9S , Figure 9T , Figure 9U , Figure 9V , Figure 9W , Figure 9X and Figure 9Y are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure; and

[0022] Fig.10 is a block diagram illustrating a memory system including a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The specific structural or functional descriptions of the examples of implementations of the concepts disclosed in this specification are merely exemplified to describe the examples of implementations of these concepts, and the examples of implementations of these concepts may be implemented in various forms, but the descriptions are not limited to the examples of implementations described in this specification.

[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0025] Embodiments of the present disclosure provide a semiconductor device including a vertical structure including a plurality of plug patterns and a method for manufacturing the semiconductor device.

[0026] Figure 1A , Figure 1B and Figure 1C are cross-sectional views and plan views for illustrating a semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 1A is a cross-sectional view of a semiconductor device. Figure 1B is a plan view at the height of a single conductive layer CP. Figure 1C is a plan view at the height of a single interlayer insulating layer ILD.

[0028] Reference Figure 1A , Figure 1Band Figure 1C , the gate stack structure GST provided on the substrate SUB may include a conductive layer CP and an interlayer insulating layer ILD alternately stacked with each other. The conductive layer CP may be a gate electrode of a selection transistor, a memory cell, etc. The conductive layer CP may be a selection line connected to the selection transistor, a word line connected to the memory cell, etc. The conductive layer CP may include a conductive material such as polysilicon, tungsten, or metal. An interlayer insulating layer ILD may be provided to insulate the stacked conductive layers CP from each other. The interlayer insulating layer ILD may include an insulating material such as an oxide or a nitride. The conductive layer CP may include a lateral portion that protrudes further than the interlayer insulating layer ILD toward the first plug pattern PP1 or the second plug pattern PP2. The insulating pattern IP may be arranged on a sidewall of the interlayer insulating layer ILD adjacent to the first plug pattern PP1 or the second plug pattern PP2. The insulating pattern IP may include a lateral portion that protrudes further than the conductive layer CP toward the first plug pattern PP1 or the second plug pattern PP2. In an embodiment, as Figure 1A As shown, the insulation pattern IP may include a lateral portion protruding further than the conductive layer CP toward the first plug pattern PP1 or the second plug pattern PP2 .

[0029] The first plug pattern PP1 and the second plug pattern PP2 may pass through the gate stack structure GST and extend in a first direction Z perpendicular to the substrate SUB. That is, the first plug pattern PP1 and the second plug pattern PP2 may extend in the stacking direction of the gate stack structure GST. The stacking direction of the gate stack structure GST may be defined as a direction in which the conductive layer CP and the interlayer insulating layer ILD included in the gate stack structure GST are alternately stacked with each other. In an embodiment, the conductive layer CP and the interlayer insulating layer ILD may be stacked in a direction perpendicular to the substrate SUB (i.e., the first direction Z). In this way, as Figure 1A As shown, in an embodiment, the first plug pattern PP1 and the second plug pattern PP2 extend in a vertical direction corresponding to a stacking direction of the gate stack structure GST.

[0030] In an embodiment, the plug pattern may include both a first plug pattern PP1 and a second plug pattern PP2. In an embodiment, an isolation structure SS may pass through the plug pattern in a vertical direction to separate the plug pattern into the first plug pattern PP1 and the second plug pattern PP2. The first plug pattern PP1 may include a first tunnel isolation layer TI1, a first channel layer CH1, and a first core insulation layer CO1.

[0031] The first core insulating layer CO1 may extend in the first direction Z and include an insulating material such as an oxide. An inner wall of the first core insulating layer CO1 may contact the isolation structure SS. The first channel layer CH1 may contact an outer wall of the first core insulating layer CO1 and extend in the first direction Z. The first channel layer CH1 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene. The first tunnel isolation layer TI1 may contact an outer wall of the first channel layer CH1 and extend in the first direction Z. Charges may be tunneled into the first tunnel isolation layer TI1 through Fowler-Nordheim (FN) tunneling. The first tunnel isolation layer TI1 may include an insulating material such as an oxide or a nitride.

[0032] The second plug pattern PP2 may include a second tunnel isolation layer TI2 , a second channel layer CH2 , and a second core insulating layer CO2 .

[0033] The second core insulating layer CO2 may extend in the first direction Z and include an insulating material such as an oxide. An inner wall of the second core insulating layer CO2 may contact the isolation structure SS. The second channel layer CH2 may contact an outer wall of the second core insulating layer CO2 and extend in the first direction Z. The second channel layer CH2 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene. The second tunnel isolation layer TI2 may contact an outer wall of the second channel layer CH2 and extend in the first direction Z. Charges may be tunneled into the second tunnel isolation layer TI2 by FN tunneling. The second tunnel isolation layer TI2 may include an insulating material such as an oxide or a nitride.

[0034] The isolation structure SS may be disposed between the first plug pattern PP1 and the second plug pattern PP2, may extend in the first direction Z, and may include an insulating material such as an oxide. The first plug pattern PP1 and the second plug pattern PP2 may have a symmetrical structure with respect to the isolation structure SS. For example, the first plug pattern PP1 and the second plug pattern PP2 may have a symmetrical structure in the second direction X corresponding to the horizontal direction.

[0035] The isolation structure SS may extend in the first direction Z and may physically and electrically separate the first plug pattern PP1 and the second plug pattern PP2 from each other. In addition, the isolation structure SS may extend in a third direction Y that is a horizontal direction perpendicular to the second direction X. For example, the isolation structure SS may extend in the third direction Y and may physically and electrically separate the first data storage layer DS1 and the second data storage layer DS2 from each other. In addition, the isolation structure SS may pass through the blocking insulating layer BI in the third direction Y.

[0036] Although not shown, the isolation structure SS may further extend in the third direction Y and pass through the conductive layer CP in the third direction Y.

[0037] The blocking insulating layer BI and the data storage layer DS1 or DS2 may be disposed between the conductive layer CP and the first plug pattern PP1 and the second plug pattern PP2. For example, the first data storage layer DS1 may be disposed in a space between the insulating patterns IP adjacent to each other in the first direction Z and between the first plug pattern PP1 and the conductive layer CP. The blocking insulating layer BI may be disposed in contact with the upper and lower surfaces of the first data storage layer DS1 and the sidewall of the first data storage layer DS1 adjacent to the conductive layer CP. In addition, the second data storage layer DS2 may be disposed in a space between the insulating patterns IP adjacent to each other in the first direction Z and between the second plug pattern PP2 and the conductive layer CP. In an embodiment, as Figure 1A As shown, the blocking insulating layer BI may be disposed in contact with the upper and lower surfaces of the first data storage layer DS1 and the sidewall of the first data storage layer DS1 adjacent to the conductive layer CP. Figure 1A As shown, the second data storage layer DS2 may be disposed in a space between the insulating patterns IP adjacent to each other in the first direction Z and between the second plug pattern PP2 and the conductive layer CP. The blocking insulating layer BI may be disposed in contact with the upper and lower surfaces of the second data storage layer DS2 and the sidewalls of the second data storage layer DS2 adjacent to the conductive layer CP. In addition, the blocking insulating layer BI may extend between the insulating pattern IP and the first tunnel isolation layer TI1. In an embodiment, as shown in FIG. Figure 1A As shown, the blocking insulating layer BI may be disposed in contact with the upper and lower surfaces of the second data storage layer DS2 and the sidewall of the second data storage layer DS2 adjacent to the conductive layer CP. Figure 1A As shown, the blocking insulating layer BI may extend between the insulating pattern IP and the first tunnel isolation layer TI1. In other words, the blocking insulating layer BI may surround the upper and lower surfaces of the insulating pattern IP and extend to the interface between the insulating pattern IP and the first plug pattern PP1 and the interface between the insulating pattern IP and the second plug pattern PP2.

[0038] The blocking insulating layer BI may include a high-k dielectric layer. The data storage layer DS (ie, the first data storage layer DS1 and the second data storage layer DS2) may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0039] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H and Fig.2I are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0040] Reference Figure 2A , a stacked structure ST may be formed on a substrate SUB. The stacked structure ST may include first material layers 11 and second material layers 12 alternately stacked with each other. The first material layers 11 and the second material layers 12 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 11 and the second material layers 12 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0041] The first material layer 11 may include a material having a high etching selectivity with respect to the second material layer 12. For example, the first material layer 11 may include an insulating material such as an oxide and the second material layer 12 may include a sacrificial material such as a nitride. In another example, the first material layer 11 may include an insulating material such as an oxide and the second material layer 12 may include a conductive material such as polysilicon and tungsten.

[0042] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST, and an etching process using the hard mask pattern may be performed to form a hole H passing through at least a portion of the stack structure ST. The hole H may partially extend into the substrate SUB.

[0043] Reference Figure 2B , the recessed region R can be formed by etching the first material layer 11 exposed through the hole H to a predetermined depth in the horizontal direction. In other words, the sidewall of the first material layer 11 can be etched to a predetermined depth so that the second material layer 12 can protrude further than the first material layer 11 in the horizontal direction. The term "predetermined" used herein with respect to a parameter (such as a predetermined depth or a predetermined thickness) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm starts. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0044] Reference Figure 2C , you can Figure 2B The sacrificial pattern 13 is formed in the recessed region R in the hole H. The sacrificial pattern 13 may include a polysilicon layer or a silicon nitride layer. For example, a polysilicon layer or a silicon nitride layer may be formed on the sidewall of the hole H so that the hole H is completely buried. Figure 2B The recessed region R is formed in the recessed region R. An etch-back process may be performed to expose the sidewall of the second material layer 12 so that the polysilicon layer or the silicon nitride layer may only remain on the sidewall of the second material layer 12. Figure 2BThe concave region R is formed to thereby form a sacrificial pattern 13 .

[0045] Reference Figure 2D , an oxidation process may be performed to selectively oxidize Figure 2C The sacrificial pattern 13 is formed so that the insulating pattern 14 can be formed. The insulating pattern 14 may have a protrusion protruding in the direction of the hole H. As a result, a space S may be formed between the protrusions of the insulating pattern 14 adjacent to each other in the first direction Z. As a result, an irregular portion may be formed on the sidewall of the hole H.

[0046] Reference Figure 2E , a blocking insulating layer 15 may be formed on the sidewalls of the hole H. The blocking insulating layer 15 may be formed on the surface of the protrusion of the insulating pattern 14 and the sidewalls of the second material layer 12. The blocking insulating layer 15 may include a high-k dielectric layer. For example, the blocking insulating layer 15 may include a high-k material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0047] Afterwards, you can Figure 2D The data storage layer 16 is formed in the space S in the blocking insulating layer 15. For example, after the data storage layer 16 is formed on the sidewall of the blocking insulating layer 15, an etch-back process may be performed thereon so that the data storage layer 16 may only remain on the sidewall of the blocking insulating layer 15. Figure 2D As a result, the blocking insulating layer 15 contacting the sidewall of the insulating pattern 14 may be exposed through the hole H. The data storage layer 16 may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0048] Reference Figure 2F , the tunnel isolation layer 17 may be formed through Figure 2E The hole H exposes the sidewalls of the blocking insulating layer 15 and the sidewalls of the data storage layer 16. The tunnel isolation layer 17 may be a layer through which charges tunnel by Fowler-Nordheim (FN) tunneling, and may include an insulating material such as oxide or nitride.

[0049] Then, a channel layer 18 may be formed on the sidewalls of the tunnel isolation layer 17. The channel layer 18 may include a semiconductor material. According to an embodiment, the channel layer 18 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene.

[0050] The core insulating layer 19 may be formed to fill the central region of the hole H. The core insulating layer 19 may include an insulating material such as an oxide layer.

[0051] Figure 2G is Figure 2F A cross-sectional view at a first height h1 - h1 ′. Figure 2H is Figure 2F A cross-sectional view at a second height h2-h2′. Figure 2G and Figure 2H , an etching process may be performed to form a groove having a line shape, which passes through the core insulating layer 19, the channel layer 18, the tunnel isolation layer 17, the data storage layer 16, and the blocking insulating layer 15 formed in the hole in the first direction Z, and an isolation structure 20 may be formed by filling the groove with an insulating material. The isolation structure 20 may extend in the third direction Y. According to an embodiment, the isolation structure 20 may extend in the third direction Y to pass through the core insulating layer 19, the channel layer 18, the tunnel isolation layer 17, the data storage layer 16, the blocking insulating layer 15, the first material layer 11, and the second material layer 12, and these layers may be divided into two symmetrical parts in the second direction X.

[0052] Reference Fig.2I , an etching process may be performed to make Figure 2F The sidewalls of the stacked structure ST are exposed and can be removed Figure 2F The exposed portion of the second material layer 12 is removed. Subsequently, a third material layer 21 may be formed in the space from which the exposed portion of the second material layer is removed. The third material layer 21 may include a conductive material such as polysilicon, tungsten, or metal. The first material layer 11 and the third material layer 21 may be defined as a gate stack structure GST.

[0053] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0054] Reference Figure 3A , a stacked structure ST may be formed on a substrate SUB, and a gate stacked structure may be formed later, such as Figure 3G As shown. The stacked structure ST may include first material layers 31 and second material layers 32 alternately stacked with each other. The first material layers 31 and the second material layers 32 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 31 and the second material layers 32 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0055] The first material layer 31 may include a material having a high etching selectivity with respect to the second material layer 32. For example, the first material layer 31 may include an insulating material such as an oxide and the second material layer 32 may include a sacrificial material such as a nitride. In another example, the first material layer 31 may include an insulating material such as an oxide and the second material layer 32 may include a conductive material such as polysilicon and tungsten.

[0056] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST, and an etching process using the hard mask pattern may be performed to form a hole H passing through at least a portion of the stack structure ST. The hole H may partially extend into the substrate SUB.

[0057] Reference Figure 3B , the protruding pattern 33 may be formed on the sidewall of the second material layer exposed by the hole H. For example, the protruding pattern 33 may be formed on the sidewall of the second material layer 32 by performing a selective deposition process. As a result, a first space S1 may be formed between the protruding patterns 33 adjacent to each other in the first direction Z. The protruding pattern 33 may include the same material as the second material layer 32.

[0058] Reference Figure 3C , the insulating pattern 34 may be formed on Figure 3B For example, a polysilicon layer or a silicon nitride layer may be formed on the sidewall of the hole H to completely fill the first space S1. Figure 3B Subsequently, an etch-back process may be performed to expose the sidewalls of the protruding pattern 33 so that the polysilicon layer or the silicon nitride layer may remain only at Figure 3B The insulating pattern 34 may be selectively oxidized by an oxidation process to form the insulating pattern 34. The insulating pattern 34 may have a protrusion protruding in a direction toward the hole H. As a result, a second space S2 may be formed between the protrusions of the insulating pattern 34 adjacent to each other in the first direction Z. As a result, an irregular portion may be formed on the sidewall of the hole H.

[0059] Reference Figure 3D , you can Figure 3C The blocking insulating layer 35 is formed on the sidewalls of the hole H in the insulating pattern 34. The blocking insulating layer 35 may be formed on the surface of the protrusion of the insulating pattern 34 and the sidewalls of the protruding pattern 33. The blocking insulating layer 35 may include a high-k dielectric layer. For example, the blocking insulating layer 35 may include a high-k material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0060] Afterwards, you can Figure 3CThe data storage layer 36 is formed in the second space S2. For example, after the data storage layer 36 is formed on the sidewall of the blocking insulating layer 35, an etch-back process may be performed so that the data storage layer 36 may remain only on the sidewall of the blocking insulating layer 35. Figure 3C As a result, the blocking insulating layer 35 contacting the sidewall of the insulating pattern 34 may be formed by Figure 3C The data storage layer 36 may be exposed by the hole H. The data storage layer 36 may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0061] Subsequently, a tunnel isolation layer 37 may be formed on the sidewalls of the blocking insulating layer 35 and the data storage layer 36 exposed by the hole H. The tunnel isolation layer 37 may be a layer through which charges tunnel by Fowler-Nordheim (FN) tunneling, and may include an insulating material such as oxide or nitride.

[0062] A channel layer 38 may be formed on a sidewall of the tunnel isolation layer 37. The channel layer 38 may include a semiconductor material. According to an embodiment, the channel layer 38 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene.

[0063] Then, a core insulating layer 39 may be formed to fill the central region of the hole. The core insulating layer 39 may include an insulating material such as an oxide layer.

[0064] Figure 3E is Figure 3D A cross-sectional view at a first height h1 - h1 ′. Figure 3F is Figure 3D A cross-sectional view at a second height h2-h2′. Figure 3E and Figure 3F , an etching process may be performed to form a groove having a line shape, which passes through the core insulating layer 39, the channel layer 38, the tunnel isolation layer 37, the data storage layer 36, and the blocking insulating layer 35 formed in the hole in the first direction Z, and an isolation structure 40 may be formed by filling the groove with an insulating material. The isolation structure 40 may extend in the third direction Y. According to an embodiment, the isolation structure 40 may extend in the third direction Y to pass through the core insulating layer 39, the channel layer 38, the tunnel isolation layer 37, the data storage layer 36, the blocking insulating layer 35, the first material layer 31, and the second material layer 32, and these layers may be divided into two symmetrical parts in the second direction X.

[0065] Reference Figure 3G , an etching process may be performed to make Figure 3D The sidewalls of the stacked structure ST are exposed and can be removed Figure 3D The exposed portion of the second material layer 32 may be removed Figure 3DThe exposed protruding pattern 33 is formed. Subsequently, a third material layer 41 may be formed in the space from which the protruding pattern and the exposed portion of the second material layer are removed. The third material layer 41 may include a conductive material such as polysilicon, tungsten, or metal. The first material layer 31 and the third material layer 41 may be defined as a gate stack structure GST.

[0066] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a cross-sectional view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0067] Reference Figure 4A , a stacked structure ST may be formed on a substrate SUB, and a gate stacked structure may be formed on the substrate later, such as Figure 4D As shown. The stacked structure ST may include first material layers 51 and second material layers 52 alternately stacked with each other. The first material layers 51 and the second material layers 52 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 51 and the second material layers 52 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0068] The first material layer 51 may include a material having a high etching selectivity with respect to the second material layer 52. For example, the first material layer 51 may include an insulating material such as an oxide and the second material layer 52 may include a sacrificial material such as a nitride. In another example, the first material layer 51 may include an insulating material such as an oxide and the second material layer 52 may include a conductive material such as polysilicon and tungsten.

[0069] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST, and an etching process using the hard mask pattern may be performed to form a hole H passing through at least a portion of the stack structure ST. The hole H may partially extend into the substrate SUB.

[0070] Reference Figure 4B , an insulating pattern 53 may be formed on the sidewall of the first material layer 51 exposed by the hole H. The insulating pattern 53 may be formed using a selective deposition process and include an oxide. As a result, a space S may be formed between the insulating patterns 53 adjacent to each other in the first direction Z. As a result, an irregular portion may be formed on the sidewall of the hole H.

[0071] Reference Figure 4C , you can Figure 4BA blocking insulating layer 54 is formed on the sidewalls of the hole H. The blocking insulating layer 54 may be formed on the exposed surface of the insulating pattern 53 and the sidewalls of the second material layer 52. The blocking insulating layer 54 may include a high-k dielectric layer. For example, the blocking insulating layer 54 may include a high-k material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0072] Afterwards, you can Figure 4B The data storage layer 55 is formed in the space S in the blocking insulating layer 54. For example, after the data storage layer 55 is formed on the sidewall of the blocking insulating layer 54, an etch-back process may be performed so that the data storage layer 55 may remain only on the sidewall of the blocking insulating layer 54. Figure 4B As a result, the blocking insulating layer 54 contacting the sidewall of the insulating pattern 53 may be formed by Figure 4B The data storage layer 55 may be exposed by the hole H. The data storage layer 55 may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0073] Afterwards, you can Figure 4B A tunnel isolation layer 56 is formed on the sidewalls of the blocking insulating layer 54 and the data storage layer 55 exposed by the hole H in the hole. The tunnel isolation layer 56 may be a layer through which charges tunnel by Fowler-Nordheim (FN) tunneling, and may include an insulating material such as oxide or nitride.

[0074] A channel layer 57 may be formed on a sidewall of the tunnel isolation layer 56. The channel layer 57 may include a semiconductor material. According to an embodiment, the channel layer 57 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene.

[0075] Then, a core insulating layer 58 may be formed to fill the central region of the hole H. The core insulating layer 58 may include an insulating material such as an oxide layer.

[0076] Reference Figure 4D , an isolation structure 59 may be formed. The isolation structure 59 may pass through the core insulating layer 58, the channel layer 57, the tunnel isolation layer 56, the data storage layer 55, and the blocking insulating layer 54 in the first direction Z. Figure 2G and Figure 2H or Figure 3E and Figure 3F The etching process is performed as described to form a trench having a line shape that passes through the core insulating layer 58, the channel layer 57, the tunnel isolation layer 56, the data storage layer 55, and the blocking insulating layer 54 formed in the hole in the first direction Z, and the hole can be filled with an insulating material. In this way, an isolation structure 59 can be formed.

[0077] Subsequently, an etching process may be performed to Figure 4C The sidewalls of the stacked structure ST are exposed and can be removed Figure 4C The exposed portion of the second material layer 52 is removed. Subsequently, a third material layer 60 may be formed in the space from which the exposed portion of the second material layer is removed. The third material layer 60 may include a conductive material such as polysilicon, tungsten, or metal. The first material layer 51 and the third material layer 60 may be defined as a gate stack structure GST.

[0078] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig.5I , Figure 5J , Figure 5K , Figure 5L and Figure 5M are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0079] Reference Figure 5A and Figure 5B , a stacked structure ST may be formed on a substrate SUB. The stacked structure ST may include first material layers 61 and second material layers 62 alternately stacked with each other. The first material layers 61 and the second material layers 62 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 61 and the second material layers 62 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0080] The first material layer 61 may include a material having a high etching selectivity with respect to the second material layer 62. For example, the first material layer 61 may include an insulating material such as an oxide and the second material layer 62 may include a sacrificial material such as a nitride. In another example, the first material layer 61 may include an insulating material such as an oxide and the second material layer 62 may include a conductive material such as polysilicon and tungsten.

[0081] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST, and an etching process using the hard mask pattern may be performed to form a hole H passing through at least a portion of the stack structure ST. The hole H may partially extend into the substrate SUB.

[0082] The hole H may have an elliptical shape. For example, a diameter X1 of the hole H in the second direction X may be greater than a diameter X2 of the hole H in the third direction Y.

[0083] Reference Figure 5CThe recessed region R may be formed by etching the first material layer 61 exposed through the hole H to a predetermined depth in a horizontal direction. In other words, the sidewall of the first material layer 61 may be etched to a predetermined depth so that the second material layer 62 may protrude more than the first material layer 61 .

[0084] Reference Figure 5D , you can Figure 5C The sacrificial pattern 63 is formed in the recessed region R in the hole H. The sacrificial pattern 63 may include a polysilicon layer or a silicon nitride layer. For example, the polysilicon layer or the silicon nitride layer may be formed along the sidewall of the hole H so that the hole H can be completely buried. Figure 5C The recessed region R may be formed in the recessed region R. An etch-back process may be performed to expose the sidewalls of the second material layer 62 so that the polysilicon layer or the silicon nitride layer may remain only at Figure 5C The concave region R is formed to form a sacrificial pattern 63 .

[0085] Reference Figure 5E , an oxidation process may be performed to selectively oxidize Figure 5D The sacrificial pattern 63 is formed so that the insulating pattern 64 can be formed. The insulating pattern 64 may have a protrusion protruding in the direction of the hole H. Therefore, a space S may be formed between the protrusions of the insulating pattern 64 adjacent to each other in the first direction Z. As a result, an irregular portion may be formed on the sidewall of the hole H.

[0086] Reference Fig. 5F , a blocking insulating layer 65 may be formed on the sidewalls of the hole H. The blocking insulating layer 65 may be formed on the surface of the protrusion of the insulating pattern 64 and the sidewalls of the second material layer 62. The blocking insulating layer 65 may include a high-k dielectric layer. For example, the blocking insulating layer 65 may include a high-k material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0087] Afterwards, you can Figure 5E The data storage layer 66 is formed in the space S in the blocking insulating layer 65. For example, after the data storage layer 66 is formed on the sidewall of the blocking insulating layer 65, an etch-back process may be performed so that the data storage layer 66 may remain only on the sidewall of the blocking insulating layer 65. Figure 5E As a result, the blocking insulating layer 65 contacting the sidewall of the insulating pattern 64 may be exposed through the hole H. The data storage layer 66 may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0088] Reference Figure 5G A tunnel isolation layer 67 may be formed on sidewalls of the blocking insulating layer 65 and the data storage layer 66 exposed by the hole H. The tunnel isolation layer 67 may be a layer through which charges tunnel by Fowler-Nordheim (FN) tunneling, and may include an insulating material such as oxide or nitride.

[0089] A channel layer 68 may be formed on a sidewall of the tunnel isolation layer 67. The channel layer 68 may include a semiconductor material. According to an embodiment, the channel layer 68 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene.

[0090] Figure 5H is Figure 5G A cross-sectional view at a first height h1 - h1 ′. Fig.5I is Figure 5G A cross-sectional view at a second height h2-h2′. Figure 5H and Fig.5I Since the hole H has an elliptical shape, a thickness of a cross section X3 of the channel layer 68 in the second direction X may be greater than a thickness of a cross section X4 of the channel layer 68 in the third direction Y.

[0091] Reference Figure 5J and Figure 5K , exposed through hole H Figure 5H and Fig.5I The channel layer 68 may be etched to a predetermined thickness to form a first channel layer 68A and a second channel layer 68B divided in the second direction X. The first channel layer 68A and the second channel layer 68B may each have a crescent shape so that the first channel layer 68A and the second channel layer 68B may be symmetrical with respect to each other. In addition, a portion of the tunnel isolation layer 67 opposite to the first channel layer 68A and the second channel layer 68B in the third direction Y may be etched.

[0092] Reference Figure 5L and Figure 5M , the exposed tunnel isolation layer 67 may be etched and divided into two parts in the second direction X. The data storage layer 66 may be exposed. Subsequently, the exposed data storage layer 66 may be etched and divided into two parts in the second direction X.

[0093] Subsequently, an isolation structure may be formed by filling the hole H. FIG.

[0094] As mentioned above Figure 4D As described, an etching process may be performed to Figure 5G The sidewalls of the stacked structure ST are exposed and can be removed Figure 5G The exposed portion of the second material layer 62 is removed. Subsequently, a third material layer may be formed in the space from which the exposed portion of the second material layer is removed. The third material layer may include a conductive material such as polysilicon, tungsten, or metal.

[0095] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H , Fig.6I , Figure 6J and Figure 6K are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0096] Reference Fig. 6A and Figure 6B , a stacked structure ST can be formed on the substrate SUB, and then Fig.6I The gate stack structure GST may be formed in the stack structure ST. The stack structure ST may include first material layers 71 and second material layers 72 alternately stacked with each other. The first material layers 71 and the second material layers 72 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 71 and the second material layers 72 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0097] The first material layer 71 may include a material having a high etching selectivity with respect to the second material layer 72. For example, the first material layer 71 may include an insulating material such as oxide and the second material layer 72 may include a conductive material such as polysilicon and tungsten.

[0098] Subsequently, the first isolation structure 73 may pass through the stack structure ST in the first direction Z and extend in the second direction X. For example, a trench having a line shape passing through the stack structure ST in the first direction Z and extending in the second direction X may be formed by performing an etching process, and the trench may be filled with an insulating material, thereby forming the first isolation structure 73.

[0099] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST and the first isolation structure 73, and an etching process using the hard mask pattern may be performed to thereby form a hole H passing through the first isolation structure 73. The hole H may partially extend into the substrate SUB. The hole H may also pass through a portion of the stack structure ST adjacent to the first isolation structure 73.

[0100] The hole H may have an elliptical shape. For example, a diameter of the hole H in the second direction X may be greater than a diameter of the hole H in the third direction Y.

[0101] Fig.6D is Figure 6C A cross-sectional view at a first height h1 - h1 ′. Fig. 6E is Figure 6C A cross-sectional view at a second height h2-h2′. Figure 6C , Fig.6D and Fig. 6E, an insulating pattern 74 may be formed on the sidewall of the first material layer 71 exposed by the hole H. The insulating pattern 74 may be formed using a selective deposition process and include an oxide. As a result, a space S may be formed between the insulating patterns 74 adjacent to each other in the first direction Z. As a result, an irregular portion may be formed on the sidewall of the hole H.

[0102] The insulating pattern 74 may not be formed at both sides of the hole H intersecting the first isolation structure 73 in the second direction X. As a result, the insulating pattern 74 may be formed in a C shape such that the insulating patterns 74 may face each other based on the second direction X.

[0103] Subsequently, a blocking insulating layer 75 may be formed along the surface of the insulating pattern 74 and the surface of the second material layer 72 exposed by the hole H. The blocking insulating layer 75 may include a high-k dielectric layer. For example, the blocking insulating layer 75 may include a high-k material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0104] Figure 6G is Fig. 6F A cross-sectional view at a first height h1 - h1 ′. Figure 6H is Fig. 6F A cross-sectional view at a second height h2-h2′. Fig. 6F , Figure 6G and Figure 6H , you can Figure 6C The data storage layer 76 is formed in the space S in the blocking insulating layer 75. For example, after the data storage layer 76 is formed on the sidewall of the blocking insulating layer 75, an etch-back process may be performed so that the data storage layer 76 may remain only on the sidewall of the blocking insulating layer 75. Figure 6C As a result, the blocking insulating layer 75 contacting the sidewall of the insulating pattern 74 may be formed by Fig.6D and Fig. 6E The data storage layer 76 may be exposed by the hole H. The data storage layer 76 may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0105] Afterwards, you can Fig.6D and Fig. 6E The tunnel isolation layer 77 is formed on the entire sidewall of the hole H. For example, Fig.6D A tunnel isolation layer 77 is formed on the sidewalls of the data storage layer 76 exposed by the hole H, the sidewalls of the blocking insulating layer 75, and the sidewalls of the first isolation structure 73. The tunnel isolation layer 77 may be a layer through which charges tunnel by Fowler-Nordheim (FN) tunneling, and may include an insulating material such as oxide or nitride.

[0106] A channel layer 78 may be formed on a sidewall of the tunnel isolation layer 77. The channel layer 78 may include a semiconductor material. According to an embodiment, the channel layer 78 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene.

[0107] Then, a core insulating layer 79 may be formed to fill the central region of the hole. The core insulating layer 79 may include an insulating material such as an oxide layer.

[0108] Figure 6J is Fig.6I A cross-sectional view at a first height h1 - h1 ′. Figure 6K is Fig.6I A cross-sectional view at a second height h2-h2′. Fig.6I , Figure 6J and Figure 6K A second isolation structure 80 may be formed through the core insulation layer 79 , the channel layer 78 , the tunnel isolation layer 77 , the data storage layer 76 , and the blocking insulation layer 75 in the first direction Z. The second isolation structure 80 may extend in the second direction X and be coupled to the first isolation structure 73 .

[0109] An etching process may be performed to form a line-shaped trench passing through the core insulating layer 79 , the channel layer 78 , the tunnel isolation layer 77 , the data storage layer 76 , the blocking insulating layer 75 in the first direction Z, and the trench may be filled with an insulating material so that a second isolation structure 80 may be formed.

[0110] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F is a plan view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0111] The method for manufacturing a semiconductor device according to an embodiment of the present disclosure may include performing the above-mentioned Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H The process described and then performed as follows with reference to Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F Process described.

[0112] Will omit the Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H Description of the process shown in .

[0113] Fig. 7A , Figure 7C and Fig. 7E is a plan view at the height of the second material layer 72 . Figure 7B , Fig.7D and Figure 7F is a plan view at the height of the first material layer 71 .

[0114] Reference Fig. 7A and Figure 7B , can be removed by performing an etching process Fig. 6A and Figure 6H The recess region R is formed by the first isolation structure 73. As a result, the tunnel isolation layer 77 at both sides in the second direction X may be exposed through the recess region R.

[0115] Reference Figure 7C and Fig.7D By etching the portion of the tunnel isolation layer 77 exposed by the recessed region R, Fig. 7A and Figure 7B The channel layer 78 of the core insulating layer 79 may be exposed, and the exposed portion of the channel layer 78 may be etched to physically separate the first channel layer 78A and the second channel layer 78B from each other. Therefore, the first channel layer 78A and the second channel layer 78B may be separated from each other at both ends in the second direction X, and may have a symmetrical structure with respect to the third direction Y. The recessed region R may extend into the core insulating layer 79.

[0116] Reference Fig. 7E and Figure 7F , by filling with insulating material Figure 7C and Fig.7D A third isolation structure 81 can be formed in the recessed region R.

[0117] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F is a plan view for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0118] The method for manufacturing a semiconductor device according to an embodiment of the present disclosure may include performing the above-mentioned Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H The process described and then performed as follows with reference to Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F Process described.

[0119] Will omit the Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H Description of the process shown in .

[0120] Reference Fig. 8A and Figure 8B , an etching process may be performed to remove Figure 6G and Figure 6H The first isolation structure 73 is formed to form the recess region R. As a result, the tunnel isolation layer 77 at both sides in the second direction X may be exposed through the recess region R.

[0121] Reference Figure 8C and Fig.8D , a wet etching oxidation process may be performed through the recessed region R to oxidize the channel layer adjacent to the recessed region R, so that a trench isolation structure 82 may be formed. As a result, Fig. 8A and Figure 8B The channel layer 78 may be divided into a first channel layer 78A and a second channel layer 78B separated by a trench isolation structure 82. Therefore, the first channel layer 78A and the second channel layer 78B may be separated from each other at both ends in the second direction X and may have a symmetrical structure with respect to the third direction Y.

[0122] Reference Fig. 8E and Fig.8F , by filling with insulating material Figure 8C and Fig.8D A third isolation structure 81 can be formed in the recessed region R.

[0123] Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Fig.9O , Figure 9P , Figure 9Q , Figure 9R , Figure 9S , Figure 9T , Figure 9U , Figure 9V , Figure 9W , Figure 9X and Figure 9Y are cross-sectional views and plan views for illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0124] Reference Fig. 9A , Fig. 9B and Fig. 9C , a stacked structure ST may be formed on a substrate SUB. The stacked structure ST may include first material layers 101 and second material layers 102 alternately stacked with each other. The first material layers 101 and the second material layers 102 may be stacked in a direction perpendicular to the substrate SUB. The first material layers 101 and the second material layers 102 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0125] The first material layer 101 may include a material having a high etching selectivity with respect to the second material layer 102. For example, the first material layer 101 may include an insulating material such as an oxide and the second material layer 102 may include a sacrificial material such as a nitride. In another example, the first material layer 101 may include an insulating material such as an oxide and the second material layer 102 may include a conductive material such as polysilicon and tungsten.

[0126] Subsequently, a hard mask pattern (not shown) may be formed on the stack structure ST, and an etching process using the hard mask pattern may be performed to form a hole H passing through at least a portion of the stack structure ST. The hole H may partially extend into the substrate SUB.

[0127] A width X12 of the hole H in the first horizontal direction AA′ may be smaller than a thickness X11 of the hole H in the second horizontal direction BB′. For example, the hole H may have an elliptical cross-section.

[0128] Reference Fig.9D , Fig.9E and Fig.9F, an insulating layer 103 may be formed on the sidewall of the hole H. The insulating layer 103 may be an oxide layer. The insulating layer 103 may include silicon oxide. The thickness D1 of the insulating layer 103 formed on the sidewall of the hole H in the first horizontal direction AA′ may be different from the thickness D2 of the insulating layer 103 formed on the sidewall of the hole H in the second horizontal direction BB′. The thickness D1 of the insulating layer 103 formed on the sidewall of the hole H in the first horizontal direction AA′ may be less than the thickness D2 of the insulating layer 103 formed on the sidewall of the hole H in the second horizontal direction BB′.

[0129] Reference Figure 9G , Figure 9H and Fig.9I , by Fig.9D , Fig.9E and Fig.9F The insulating layer 103 in the hole H is etched to a predetermined thickness, and a portion of the insulating layer can be removed. The etching process can be performed using an isotropic etching process. For example, a portion of the insulating layer 103 can be etched to expose the sidewall of the hole H in the first horizontal direction AA'. During the etching process, since the thickness of the insulating layer 103 formed on the sidewall of the hole H in the first horizontal direction AA' is less than the thickness of the insulating layer 103 formed on the sidewall of the hole H in the second horizontal direction BB', even when the insulating layer 103 is etched to expose the sidewall of the hole H in the first horizontal direction AA', the insulating layer 103 can remain on the sidewall of the hole H in the second horizontal direction BB'. In addition, due to the difference in surface area and surface angle exposed by the etchant during the isotropic etching process, the etching rate in the second horizontal direction BB' can be slower than the etching rate in the first horizontal direction AA'. As a result, a sacrificial pattern 103P can be formed on both sidewalls of the hole H in the second horizontal direction BB'. The horizontal cross-section of the sacrificial pattern 103P can have a crescent shape. The thickness D3 of the sacrificial pattern 103P may be less than Fig.9F θ is the thickness D2 of the insulating layer 103 formed on the sidewall of the hole H in the second horizontal direction BB′.

[0130] The sidewall of the hole H may be divided into the first sidewall SW1 and the second sidewall SW2 based on the sacrificial pattern 103P. For example, both sides of the sidewall of the hole H in the first horizontal direction AA′ may be divided into the first sidewall SW1 and the second sidewall SW2.

[0131] Reference Figure 9J , Figure 9K and Figure 9L, an insulating pattern 104 may be formed on the sidewall of the first material layer 101 exposed by the hole H. The insulating pattern 104 may be separately formed on the first sidewall SW1 and the second sidewall SW2 on both sides along the first horizontal direction AA′. The insulating pattern 104 formed on the first sidewall SW1 and the second sidewall SW2 may have a symmetrical structure so that the insulating patterns 104 may be opposite to each other. The insulating pattern 104 may be formed using a selective deposition process and include an oxide.

[0132] As a result, a space S may be formed between the insulating patterns 104 adjacent to each other in a vertical direction. As a result, irregularities may be formed on the first and second side walls SW1 and SW2 of the hole H.

[0133] Reference Figure 9M , Figure 9N and Fig.9O , can be removed by performing an etching process Figure 9J and Fig.9I As a result, irregularities may remain on the first and second sidewalls SW1 and SW2 of the hole H, and sidewalls of the first and second material layers 101 and 102 may be partially exposed from both sides of the hole H in the second horizontal direction BB′.

[0134] Reference Figure 9P , Figure 9Q , Figure 9R and Figure 9S , you can Figure 9M and Figure 9N The blocking insulating layer 105 is formed on the sidewalls of the hole H in the first sidewall SW1 and the second sidewall SW2 of the hole H. The blocking insulating layer 105 on the first sidewall SW1 and the second sidewall SW2 of the hole H may be formed on the exposed surface of the insulating pattern 104 and the sidewalls of the second material layer 102. The blocking insulating layer 105 on both sides of the hole H along the second horizontal direction BB′ may be formed on the sidewalls of the first material layer 101 and the second material layer 102. The blocking insulating layer 105 may include a high-k dielectric layer. For example, the blocking insulating layer 105 may include a high-k material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0135] Afterwards, you can Figure 9N The data storage layer 106 is formed in the space S in the blocking insulating layer 105. For example, after the data storage layer 106 is formed on the sidewall of the blocking insulating layer 105, an etch-back process may be performed so that the data storage layer 106 may remain only on the sidewall of the blocking insulating layer 105. Figure 9N As a result, the space S in Figure 9NThe data storage layers 106 in the space S may be separated from each other in the vertical direction, and the data storage layers 106 formed on the first and second sidewalls SW1 and SW2 of the hole may be separated from each other at both sides of the hole in the second horizontal direction.

[0136] The data storage layer 106 may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0137] Subsequently, a tunnel isolation layer 107 may be formed on the sidewalls of the data storage layer 106 and the blocking insulating layer 105 exposed by the hole. The tunnel isolation layer 107 may be a layer through which charges tunnel by Fowler-Nordheim (FN) tunneling and may include an insulating material such as oxide or nitride.

[0138] A channel layer 108 may be formed on a sidewall of the tunnel isolation layer 107. The channel layer 108 may include a semiconductor material. According to an embodiment, the channel layer 108 may include a semiconductor material such as silicon or germanium, or a nanostructure such as nanodots, nanotubes, or graphene.

[0139] Then, a core insulating layer 109 may be formed to fill the central region of the hole. The core insulating layer 109 may include an insulating material such as an oxide layer.

[0140] Reference Figure 9T , Figure 9U , Figure 9V and Figure 9W , an etching process may be performed to make Figure 9P and Figure 9Q The sidewalls of the stacked structure ST are exposed and can be removed Figure 9P and Figure 9Q The exposed portion of the second material layer 102 is formed to form a recessed region R11.

[0141] Subsequently, a wet oxidation process may be performed through the recessed region R11 to oxidize the channel layer adjacent to the recessed region R12, so that a channel isolation structure 110 may be formed. The channel isolation structure 110 may be formed at both side portions in the second horizontal direction BB′ where the data storage layer 106 is not formed. The channel layer adjacent to the data storage layer 106 may be divided into a first channel layer 108A and a second channel layer 108B by the channel isolation structure 110.

[0142] Subsequently, a third material layer 111 may be formed in the space from which the second material layer is removed. The third material layer 111 may include a conductive material such as polysilicon, tungsten, or metal, etc. The first material layer 101 and the third material layer 111 may be defined as a gate stack structure GST.

[0143] Reference Figure 9Xand Figure 9Y , the third material layer 111 may be formed on Figure 9T and Figure 9U The third material layer 111 may include a conductive material such as polysilicon, tungsten, or metal. The first material layer 101 and the third material layer 111 may be defined as a gate stack structure.

[0144] Fig.10 is a block diagram illustrating a memory system 1000 including a semiconductor device according to an embodiment of the present disclosure.

[0145] Reference Fig.10 , the memory system 1000 may include a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 may include a plurality of semiconductor memory devices 500. The plurality of semiconductor memory devices 500 may be divided into a plurality of groups GR1 to GRn. According to an embodiment of the present disclosure, it is shown that the host 1300 is included in the memory system 1000. However, the memory system 1000 may include only the controller 1200 and the memory device 1100, and the host 1300 may be provided outside the memory system 1000.

[0146] like Fig.10 As shown, the plurality of groups GR1 to GRn in the memory device 1100 may communicate with the controller 1200 through the first channel CH1 to the nth channel CHn, respectively. Each of the semiconductor memory devices 500 may be as described above with reference to Figure 1A , Figure 1B and Figure 1C A semiconductor device is described.

[0147] Each of the plurality of groups GR1 to GRn may be configured to communicate with the controller 1200 through a single common channel. The controller 1200 may be configured to control the plurality of semiconductor memory devices 500 of the memory device 1100 through a plurality of first to n-th channels CH1 to CHn.

[0148] The controller 1200 may be coupled between the host 1300 and the memory device 1100. The controller 1200 may be configured to access the memory device 1100 in response to a request from the host 1300. For example, the controller 1200 may be configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 1100 in response to a host command Host_CMD received from the host 1300. The host 1300 may transmit an address ADD and data DATA to be programmed together with the host command Host_CMD to the memory device 1100 during a program operation. During a read operation, the controller 1200 may transmit a command corresponding to a read operation to the memory device 1100, receive read data DATA from the memory device, and transmit the transmitted data DATA to the host 1300. The controller 1200 may be configured to provide an interface between the memory device 1100 and the host 1300. The controller 1200 may run firmware for controlling the memory device 1100.

[0149] The host 1300 may include a portable electronic device such as a PDA, a PMP, an MP3 player, a camera, a camcorder, or a cellular phone. The host 1300 may request a program operation, a read operation, and an erase operation of the memory system 1000 through a host command Host_CMD. The host 1300 may transmit a host command Host_CMD corresponding to a program operation, an address ADD for a program operation, and data DATA to the controller 1200. The host 1300 may transmit a host command Host_CMD corresponding to a read operation and an address ADD for a read operation to the controller 1200. The address ADD may be a logical address.

[0150] The controller 1200 and the memory device 1100 may be integrated into one semiconductor device. According to an exemplary embodiment, the controller 1200 and the memory device 1100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into a single semiconductor device and form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash (CF) card, a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or Micro MMC), an SD card (SD, Mini SD, Micro SD or SDHC), a Universal Flash Storage (UFS), etc.

[0151] In another example, the memory system 1000 may be provided as one of various elements of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a network book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital photo player, a digital photo recorder, a digital video recorder, a device capable of sending / receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of a variety of electronic devices for forming a telematics network, an RFID device, or one of various elements for forming a computing system.

[0152] In an exemplary embodiment, the memory device 1100 or the memory system 1000 may be embedded in various forms of packages. For example, the memory device 1100 or the memory system 1000 may be installed using a package such as a stacked package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic lead chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in a waffle package, a wafer form die, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), or a wafer-level processing stacked package (WSP).

[0153] According to the present disclosure, in an embodiment, the number of memory cells may be increased by separating a plurality of plug patterns from each other using isolation patterns.

[0154] It will be apparent to those skilled in the art that various modifications may be made to the above-described embodiments without departing from the spirit or scope of the present disclosure. Therefore, it is intended that the embodiments cover all such modifications as long as they fall within the scope of the appended claims and their equivalents.

[0155] CROSS-REFERENCE TO RELATED APPLICATIONS

[0156] This application claims the priority of Korean Patent Application No. 10-2023-0143918 filed on October 25, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A gate stack structure, the gate stack structure comprising interlayer insulating layers and conductive layers alternately stacked on each other; a first plug pattern and a second plug pattern, the first plug pattern and the second plug pattern extending in a vertical direction corresponding to a stacking direction of the gate stack structure; a first data storage layer and a second data storage layer, the first data storage layer being disposed between the first plug pattern and the conductive layer, and the second data storage layer being disposed between the second plug pattern and the conductive layer; an isolation structure extending in the vertical direction and separating the first plug pattern and the second plug pattern from each other; as well as An insulating pattern is disposed between the first data storage layers adjacent to each other along the vertical direction and between the second data storage layers adjacent to each other along the vertical direction.

2. The semiconductor device according to claim 1, wherein The isolation structure extends in a horizontal direction substantially perpendicular to the vertical direction and spaces the first data storage layer and the second data storage layer apart from each other.

3. The semiconductor device according to claim 1, wherein The insulating pattern is disposed between the interlayer insulating layer and the first plug pattern and between the interlayer insulating layer and the second plug pattern.

4. The semiconductor device according to claim 1, wherein Each of the first plug pattern and the second plug pattern includes: a core insulating layer extending in the vertical direction and including an inner sidewall contacting the isolation structure; a channel layer contacting an outer sidewall of the core insulating layer; and A tunnel isolation layer contacts an outer sidewall of the channel layer.

5. The semiconductor device according to claim 1, further comprising a blocking insulating layer surrounding upper and lower surfaces of the first and second data storage layers and sidewalls of the first and second data storage layers adjacent to the conductive layer.

6. The semiconductor device according to claim 5, wherein: The blocking insulating layer surrounds upper and lower surfaces of the insulating pattern and extends to an interface between the insulating pattern and the first plug pattern and to an interface between the insulating pattern and the second plug pattern.

7. The semiconductor device according to claim 1, in, The conductive layer protrudes further than the interlayer insulating layer in a direction toward the first plug pattern, and The conductive layer protrudes further than the insulating layer in a direction toward the second plug pattern.

8. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a hole through at least a portion of a stacked structure including first material layers and second material layers alternately stacked with each other; forming a recessed area by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the recessed area; forming an insulating pattern protruding further than a sidewall of the second material layer in a direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other in a vertical direction; forming a plug pattern extending in the vertical direction in the hole; as well as An isolation structure is formed that passes through the plug pattern in the vertical direction and separates the plug pattern into a first plug pattern and a second plug pattern.

9. The method according to claim 8, further comprising the steps of: Before forming the data storage layer, a blocking insulating layer is formed, the blocking insulating layer extending along sidewalls of the insulating pattern and the second material layer exposed by the hole.

10. The method according to claim 9, wherein: The step of forming the plug pattern comprises the following steps: forming a tunnel isolation layer on a sidewall of the data storage layer and a sidewall of the blocking insulating layer exposed through the hole; forming a channel layer on a sidewall of the tunnel isolation layer; and A core insulating layer is formed by filling a central region of the hole with an insulating material.

11. The method according to claim 9, wherein: The step of forming the isolation structure comprises the following steps: forming a trench having a substantially line shape passing through the plug pattern by performing an etching process; and The isolation structure is formed by filling the trench with an insulating material.

12. The method according to claim 11, wherein: The trench extends in a horizontal direction and passes through the data storage layer.

13. The method according to claim 11, wherein: The trench extends in a horizontal direction and passes through the data storage layer, the blocking insulating layer, and the second material layer.

14. The method according to claim 8, further comprising the steps of: performing an etching process to expose the sidewalls of the stacked structure; removing the exposed portion of the second material layer; as well as A third material layer is filled in the space from which the exposed portion of the second material layer is removed.

15. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a hole through at least a portion of a stacked structure including first material layers and second material layers alternately stacked with each other; forming a protruding pattern on a sidewall of the second material layer exposed through the hole; forming an insulating pattern protruding further than a sidewall of the protruding pattern in a direction of the hole in a space between the protruding patterns adjacent to each other in a vertical direction; forming a data storage layer in a space between the insulating patterns adjacent to each other along the vertical direction; forming a plug pattern extending in the vertical direction in the hole; as well as An isolation structure is formed that passes through the plug pattern in the vertical direction and separates the plug pattern into a first plug pattern and a second plug pattern.

16. The method according to claim 15, wherein: The step of forming the insulating pattern comprises the following steps: forming a sacrificial pattern in the space between the protruding patterns; and The insulating pattern protruding further than a sidewall of the protruding pattern in a direction of the hole is formed by oxidizing the sacrificial pattern.

17. The method according to claim 15, further comprising the steps of: Before forming the data storage layer, a blocking insulating layer is formed, the blocking insulating layer extending on sidewalls of the insulating pattern and the second material layer exposed by the hole.

18. The method according to claim 17, wherein: The step of forming the plug pattern comprises the following steps: forming a tunnel isolation layer on a sidewall of the data storage layer and a sidewall of the blocking insulating layer exposed through the hole; forming a channel layer on a sidewall of the tunnel isolation layer; and A core insulating layer is formed by filling a central region of the hole with an insulating material.

19. The method according to claim 18, wherein: The trench extends in a horizontal direction and passes through the data storage layer.

20. The method according to claim 18, wherein: The trench extends in a horizontal direction and passes through the data storage layer, the blocking insulating layer, and the second material layer.

21. The method according to claim 15, further comprising the steps of: performing an etching process to expose the sidewalls of the stacked structure; removing the protruding pattern and the exposed portion of the second material layer; as well as A third material layer is filled in the space from which the protruding pattern and the exposed portion of the second material layer are removed.

22. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a hole through at least a portion of a stacked structure including first material layers and second material layers alternately stacked with each other; forming an insulating pattern on a sidewall of the first material layer exposed through the hole; forming a data storage layer in a space between the insulating patterns adjacent to each other in a vertical direction; forming a plug pattern extending in the vertical direction in the hole; as well as An isolation structure is formed that passes through the plug pattern in the vertical direction and separates the plug pattern into a first plug pattern and a second plug pattern.

23. The method according to claim 22, wherein: The step of forming the insulating pattern includes the step of forming the insulating pattern protruding further than a sidewall of the second material layer in a direction of the hole by using a selective deposition process.

24. The method according to claim 22, further comprising the steps of: Before forming the data storage layer, a blocking insulating layer is formed, the blocking insulating layer extending along sidewalls of the insulating pattern and the second material layer exposed by the hole.

25. The method according to claim 24, wherein: The step of forming the plug pattern comprises the following steps: forming a tunnel isolation layer on a sidewall of the data storage layer and a sidewall of the blocking insulating layer exposed through the hole; forming a channel layer on a sidewall of the tunnel isolation layer; and A core insulating layer is formed by filling a central region of the hole with an insulating material.

26. The method according to claim 25, wherein: The trench extends in a horizontal direction and passes through the data storage layer.

27. The method according to claim 25, wherein: The trench extends in a horizontal direction and passes through the data storage layer, the blocking insulating layer, and the second material layer.

28. The method according to claim 22, further comprising the steps of: performing an etching process to expose the sidewalls of the stacked structure; removing the exposed portion of the second material layer; as well as A third material layer is filled in the space from which the exposed portion of the second material layer is removed.

29. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a hole having a substantially elliptical shape through at least a portion of a stacked structure including first material layers and second material layers alternately stacked on each other; forming a recessed area by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the recessed area; forming an insulating pattern protruding further than a sidewall of the second material layer in a direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other in a vertical direction; sequentially forming a tunnel isolation layer and a channel layer extending in the vertical direction on the sidewalls of the hole, wherein a thickness of a cross section of the channel layer in a first horizontal direction is greater than a thickness of a cross section in a second horizontal direction substantially perpendicular to the first horizontal direction; forming the first channel layer and the second channel layer by etching the channel layer to a predetermined thickness so that the channel layer is divided into a first channel layer and a second channel layer in the first horizontal direction, and exposing a portion of the tunnel isolation layer between the first channel layer and the second channel layer; and The exposed portion of the tunnel isolation layer and the data storage layer are sequentially etched to divide the tunnel isolation layer and the data storage layer into two parts in the first horizontal direction.

30. The method according to claim 29, further comprising the steps of: An isolation pattern is formed by filling a central area of ​​the hole with an insulating material.

31. The method of claim 29, wherein: A diameter of the hole in the first horizontal direction is greater than a diameter of the hole in the second horizontal direction.

32. The method of claim 29, wherein: The first channel layer and the second channel layer have substantially symmetrical meniscus shapes opposite to each other in the second horizontal direction.

33. The method according to claim 29, further comprising the steps of: performing an etching process to expose the sidewalls of the stacked structure; removing the exposed portion of the second material layer; as well as A third material layer is filled in the space from which the exposed portion of the second material layer is removed.

34. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a first isolation pattern that passes through the stacked structure in a vertical direction and extends in a first horizontal direction; forming a hole passing through the stacked structure and the first isolation pattern; forming a recessed area by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the recessed area; forming an insulating pattern protruding further than a sidewall of the second material layer in a direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other along the vertical direction; sequentially forming a tunnel isolation layer, a channel layer, and a core insulation layer extending in the vertical direction on the sidewalls of the hole; as well as A second isolation pattern is formed that passes through the tunnel isolation layer, the channel layer, and the core insulation layer in the vertical direction and separates the channel layer into a first channel layer and a second channel layer.

35. The method according to claim 34, further comprising the steps of: Before forming the data storage layer, a blocking insulating layer is formed, the blocking insulating layer extending along sidewalls of the insulating pattern and the second material layer exposed by the hole.

36. The method of claim 34, wherein: The step of forming the second isolation pattern comprises the following steps: forming a trench having a line shape extending in the first horizontal direction and exposing a sidewall of the first isolation pattern by performing an etching process; and A second isolation pattern is formed by filling the trench with an insulating material.

37. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a first isolation pattern that passes through the stacked structure in a vertical direction and extends in a first horizontal direction; forming a hole passing through the stacked structure and the first isolation pattern; forming a first recessed region by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the first recessed region; forming an insulating pattern protruding further than a sidewall of the second material layer in a direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other along the vertical direction; sequentially forming a tunnel isolation layer, a channel layer, and a core insulation layer extending in the vertical direction on the sidewalls of the hole; forming a second recessed area by removing the first isolation pattern; as well as The channel layer is separated into a first channel layer and a second channel layer spaced apart from each other by etching the tunnel isolation layer and the channel layer exposed through the second recess region.

38. The method according to claim 37, further comprising the steps of: An isolation structure is formed by filling the second recessed region with an insulating material.

39. The method according to claim 37, further comprising the steps of: Before forming the data storage layer, a blocking insulating layer is formed, the blocking insulating layer extending along sidewalls of the insulating pattern and the second material layer exposed by the hole.

40. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure including first material layers and second material layers alternately stacked on each other; forming a first isolation pattern that passes through the stacked structure in a vertical direction and extends in a first horizontal direction; forming a hole passing through the stacked structure and the first isolation pattern; forming a first recessed region by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial pattern in the first recessed region; forming an insulating pattern protruding further than a sidewall of the second material layer in a direction of the hole by oxidizing the sacrificial pattern; forming a data storage layer in a space between the insulating patterns adjacent to each other along the vertical direction; sequentially forming a tunnel isolation layer, a channel layer, and a core insulation layer extending in the vertical direction on the sidewalls of the hole; forming a second recessed area by removing the first isolation pattern; as well as A trench isolation structure is formed by performing a wet oxidation process through the second recessed region to oxidize a portion of the channel layer adjacent to the second recessed region.

41. The method of claim 40, wherein: The channel layer is separated into a first channel layer and a second channel layer spaced apart from each other by the trench isolation structure.

42. The method according to claim 40, further comprising the steps of: An isolation structure is formed by filling the second recessed region with an insulating material.

43. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a hole through at least a portion of a stacked structure including first material layers and second material layers alternately stacked with each other; forming a first isolation pattern and a second isolation pattern contacting an interface between a first side wall and a second side wall in the hole that are opposite to each other and extending in a vertical direction; forming an insulating pattern on a sidewall of the first material layer exposed through the hole; removing the first isolation pattern and the second isolation pattern, and forming a data storage layer in a space between the isolation patterns adjacent to each other in the vertical direction on the first sidewall and the second sidewall; sequentially forming a tunnel isolation layer, a channel layer and a core insulation layer on the sidewalls of the hole; performing an etching process to expose the sidewalls of the stacked structure; forming a recessed area by removing an exposed portion of the second material layer; as well as A trench isolation structure is formed by performing a wet oxidation process through the recessed region to oxidize a portion of the channel layer adjacent to the recessed region.

44. The method of claim 43, wherein: The channel layer is separated into a first channel layer and a second channel layer by the trench isolation structure.

45. The method according to claim 43, further comprising the steps of: The recessed area is filled with a third material layer.

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