Preparation method of semiconductor device, semiconductor device and storage system

Abstract

The invention provides a preparation method of a semiconductor device, the semiconductor device and a storage system, relates to the technical field of semiconductor chips, and aims to solve the problem of poor stability of the semiconductor device. The preparation method of the semiconductor device comprises the steps that a storage stacking structure is formed, the storage stacking structure comprises a lamination structure and a plurality of channel structures, the channel structures penetrate through the lamination structure in the lamination direction of the lamination structure, and each channel structure comprises a channel part. A plurality of strip-shaped conductive parts are formed on the surface of one side, in the stacking direction, of the stacked structure, the strip-shaped conductive parts extend in the first direction intersecting with the stacking direction, and the strip-shaped conductive parts are arranged at intervals in the second direction. And removing a part in the at least one strip-shaped conductive part, so that the reserved part in the strip-shaped conductive part forms a plurality of channel contact parts which are arranged at intervals along the first direction, and the channel contact parts are in contact with the channel parts. The semiconductor device is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a method for preparing a semiconductor device, a semiconductor device, and a storage system. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] As the number of stacked layers of memory cells in a three-dimensional memory increases, the distance between memory cells decreases, and the existing method for preparing three-dimensional memory results in poor stability of semiconductor devices. Summary of the invention

[0005] The embodiments of the present disclosure provide a method for preparing a semiconductor device, a semiconductor device, and a storage system, aiming to solve the problem of poor stability of the semiconductor device.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a method for preparing a semiconductor device is provided, the method comprising: forming a storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along the stacking direction of the stack structure, and each channel structure comprising a channel portion. A plurality of strip-shaped conductive portions are formed on a surface of one side of the stack structure along the stacking direction, the plurality of strip-shaped conductive portions extend along a first direction intersecting the stacking direction, and the plurality of strip-shaped conductive portions are arranged at intervals in a second direction. The second direction intersects the first direction, and the second direction intersects the stacking direction. A portion of at least one strip-shaped conductive portion is removed so that the remaining portion of the strip-shaped conductive portion constitutes a plurality of channel contact portions arranged at intervals along the first direction. The channel contact portion contacts the channel portion.

[0008] The method for preparing a semiconductor device provided by the above-mentioned embodiment of the present disclosure forms a plurality of strip-shaped conductive parts on the surface of the side of the stacked structure away from the substrate. When the strip-shaped conductive part is used to align and cover a row of channel parts in the direction in which the strip-shaped conductive part extends, the strip-shaped conductive part provided by the present disclosure has a larger contact window, which can improve the accuracy of the alignment and covering between the strip-shaped conductive part and a row of channel parts. Then, based on the aforementioned strip-shaped conductive part, a portion of the strip-shaped conductive part is removed to form a channel contact part that is arranged at intervals and in contact with the channel part. The embodiment of the present disclosure can control the position and length of the removed portion of the strip-shaped conductive part according to the position of the channel part, and control the position and length of the channel contact part retained in the strip-shaped conductive part, thereby improving the accuracy of the contact between the channel contact part and the corresponding channel part, thereby improving the electrical connection effect between the channel contact part and the channel part, and thereby improving the stability of the semiconductor device.

[0009] In some embodiments, before forming a plurality of strip-shaped conductive parts on a side surface of the stacked structure along the stacking direction, the method further includes: forming a first insulating layer on a side surface of the stacked structure along the stacking direction. Forming a plurality of strip-shaped conductive parts on a side surface of the stacked structure along the stacking direction includes: forming a first mask layer on the first insulating layer, the first mask layer including a plurality of first openings. Using the plurality of first openings of the first mask layer, a plurality of strip-shaped grooves are formed in the first insulating layer, the strip-shaped grooves exposing the channel portions. A plurality of strip-shaped conductive parts are formed in the plurality of strip-shaped grooves.

[0010] In some embodiments, removing a portion of at least one strip-shaped conductive portion so that the remaining portion of the strip-shaped conductive portion forms a plurality of channel contacts arranged at intervals along a first direction includes: forming a second mask layer, the second mask layer covers the first mask layer and the plurality of strip-shaped conductive portions, the second mask layer includes a plurality of second openings. Using the plurality of second openings of the second mask layer, removing a portion of at least one strip-shaped conductive portion to form a plurality of partitions. The plurality of partitions separate the remaining portion of the strip-shaped conductive portion into a plurality of channel contacts.

[0011] In some embodiments, the plurality of second openings are arranged in a plurality of rows, the plurality of second openings in a row of second openings are arranged sequentially along the first direction, and the plurality of second openings in a row of second openings are arranged sequentially along the second direction. The plurality of second openings in a row of second openings are arranged at intervals on the strip-shaped conductive portion.

[0012] In some embodiments, the distance between two adjacent second openings in the first direction is the spacing between the grooves, and the spacing between at least two grooves is not equal.

[0013] In some embodiments, the method for preparing a semiconductor device further includes: filling the plurality of trenches with an insulating material and removing the first mask layer and the second mask layer.

[0014] In some embodiments, the method for preparing a semiconductor device further includes: forming a second insulating layer on a side of the plurality of channel contacts away from the stacked structure, forming a connection hole on the second insulating layer, forming a connection portion in the connection hole, the connection portion contacting the channel contact portion. Forming a third insulating layer on a side of the second insulating layer away from the stacked structure, forming a connection groove on the third insulating layer, and forming a conductive line in the connection groove.

[0015] On the other hand, a semiconductor device is provided, comprising: a storage stack structure and a plurality of spaced channel contacts. The storage stack structure comprises a stack structure and a plurality of channel structures, wherein the plurality of channel structures penetrate the stack structure along the stacking direction of the stack structure, and each channel structure comprises a channel portion. The plurality of spaced channel contacts are arranged on a side surface of the stack structure along the stacking direction, and the channel contacts are in contact with the channel portions. At least two of the channel contacts have different widths in a first direction, and the first direction intersects with the stacking direction.

[0016] In some embodiments, the channel contact portion includes two first surfaces arranged opposite to each other in the stacking direction and a plurality of side surfaces connected to the first surfaces, wherein the plurality of side surfaces include at least a first side surface extending along the first direction and a second side surface extending along the second direction.

[0017] In some embodiments, the number of the first side surfaces is two, and the two first side surfaces are arranged opposite to each other in the second direction. The number of the second side surfaces is two, and the two second side surfaces are arranged opposite to each other in the first direction.

[0018] In some embodiments, first side surfaces of a plurality of channel contacts arranged at intervals in the first direction and located on the same side of the first surface in the second direction are coplanar.

[0019] In some embodiments, a cross-section of the channel contact portion on a reference plane is rectangular or quasi-rectangular, wherein the reference plane is perpendicular to the stacking direction.

[0020] In some embodiments, a cross-sectional area of ​​the channel portion on the reference plane is smaller than a cross-sectional area of ​​the channel contact portion on the reference plane.

[0021] In some embodiments, the semiconductor device further comprises: a plurality of connection portions, which are arranged on a side of the channel contact portion away from the stacked structure, one connection portion contacts one channel contact portion, and the cross-sectional area of ​​the connection portion on the reference plane is smaller than the cross-sectional area of ​​the channel contact portion on the reference plane.

[0022] In some embodiments, the semiconductor device further comprises: a plurality of conductive wires. The plurality of conductive wires are arranged on a side of the plurality of connection portions away from the plurality of channel contact portions, and one conductive wire contacts at least one connection portion.

[0023] In some embodiments, the semiconductor device further includes a peripheral device, and the peripheral device is electrically connected to the conductive line.

[0024] In another aspect, a storage system is provided, comprising: the semiconductor device as described above and a controller. The controller is coupled to the semiconductor device to control the semiconductor device to store data.

[0025] On the other hand, an electronic device is provided, comprising the storage system as described above.

[0026] It can be understood that the beneficial effects that can be achieved by the semiconductor device, three-dimensional memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device preparation method mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0028] Figure 1 A structural block diagram of an electronic device provided for some embodiments of the present disclosure;

[0029] Figure 2A A schematic diagram of the structure of a storage device provided in some embodiments of the present disclosure;

[0030] Figure 2B A schematic diagram of the structure of another storage device provided for some embodiments of the present disclosure;

[0031] Figure 3 A schematic diagram of a three-dimensional structure of a three-dimensional memory provided in some embodiments of the present disclosure;

[0032] Figure 4 A cross-sectional view of a three-dimensional memory provided for some embodiments of the present disclosure;

[0033] Figure 5 for Figure 3 A cross-sectional view of a memory cell string along section line AA' in the memory;

[0034] Figure 6 for Figure 5 Equivalent circuit diagram of the storage cell string in FIG.

[0035] Fig. 7AA top view of a semiconductor device according to an embodiment of the present disclosure;

[0036] Figure 7B A top view of a semiconductor device according to another embodiment of the present disclosure;

[0037] Figure 7C A top view of a semiconductor device according to another embodiment of the present disclosure;

[0038] Figure 8A to Figure 8B A flowchart of a method for preparing a semiconductor device provided for some embodiments of the present disclosure;

[0039] FIG. 9A to FIG. 9E Cross-sectional views corresponding to some steps in the method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0040] Figures 10A to 10C A top view structural diagram corresponding to some steps of a method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0041] Fig.11 A flowchart of a method for preparing a semiconductor device provided for some embodiments of the present disclosure;

[0042] Fig.12 A top view of a semiconductor device provided for some embodiments of the present disclosure;

[0043] Fig.13 A schematic structural diagram of a channel contact portion provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0045] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0047] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0048] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0049] Figure 1 A structural block diagram of an electronic device 9000 provided for some embodiments of the present disclosure. The electronic device 9000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0050] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a host 920. The storage system 910 may be integrated into various types of storage devices 900, such as a memory card. The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital MemorZ Card (SD) card, and a Universal Flash Storage (UFS). That is, the storage system 910 may be applied to and packaged in different types of electronic products.

[0051] The host 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 920 may be configured to send data to the memory 911 or receive data from the memory 911.

[0052] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage of mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays. Alternatively, in some examples, the controller 912 is coupled to the memory 911 and the host 920, and is configured to control the data in the memory 911, and can communicate with an external device (such as a host).

[0053] Figure 2A A schematic diagram of a storage device 900 provided in some embodiments of the present disclosure is shown in FIG. Figure 2B A schematic diagram of the structure of another storage device 900 provided for some embodiments of the present disclosure.

[0054] See also Figure 2A and Figure 2BThe storage device 900 may include a storage system 910 and an interface 913, wherein the number of memories 911 in the storage system 910 may be one or more. For example, Figure 2A A single memory 911 is used as an example for illustration. Figure 2B 911 as an example. The controller 912 can manage the data stored in each memory 911 and communicate with the host 920 outside the storage device 900 through the interface 913. The controller 912 can be configured to control the operation of each memory 911, such as read, write and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0055] In some embodiments, the controller 912 is also configured to determine the maximum memory capacity, the number of memory banks, memory types and speeds, memory granule data depth and data width, and other important parameters that the computer system can use. Any other suitable function may also be performed by the controller 912. The controller 912 may communicate with an external device (e.g., a host 920) according to a specific communication protocol. For example, the controller 912 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI high-speed (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0056] Figure 3 A schematic diagram of a three-dimensional structure of a three-dimensional memory provided in some embodiments of the present disclosure, Figure 4 A cross-sectional view of a three-dimensional memory provided for some embodiments of the present disclosure.

[0057] See also Figure 3 and Figure 4The memory 911 may include a memory stack structure 12, a source layer SL coupled to the memory stack structure 12, and a peripheral device 13 coupled to the memory stack structure 12. The peripheral device 13 may be disposed on a side of the memory stack structure 12 away from the source layer SL.

[0058] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0059] The memory stack structure 12 may include memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 400 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400 .

[0060] Figure 5 for Figure 3 A cross-sectional view of a memory cell string in the memory along the section line AA', Figure 6 for Figure 5 Equivalent circuit diagram of the storage cell string in .

[0061] See also Figure 5 and Figure 6 , the memory cell string 400 may include a channel structure 122 and a plurality of gate lines G, and the plurality of gate lines G may be disposed around the channel structure 122 .

[0062] For example, the channel structure 122 may include a support portion 1226 , and a channel layer 1222 , a tunneling layer 1225 , a charge trapping layer 1224 , and a charge blocking layer 1221 sequentially disposed on the periphery of the support portion 1226 .

[0063] In some examples, the channel structure 122 may further include a channel portion 1223 , wherein the channel portion 1223 is connected between the channel layer 1222 and the channel contact 1331 .

[0064] The memory cell string 400 may include a plurality of transistors T, for example Figure 6 T1-T6 in the figure, wherein one transistor T can be set as a memory cell, and these transistors T are connected together to form a memory cell string.

[0065] One transistor T (for example, each transistor T) may be formed by one gate line G and a portion of the channel structure 122 surrounded by the gate line G. The gate line G is configured to control the conduction state of the transistor.

[0066] It should be noted that Figure 3 to Figure 6 The number of transistors in the embodiment is only illustrative, and the memory cell string of the three-dimensional memory provided in the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, 64. In the embodiment of the present disclosure, the number of transistors in the memory cell string is not limited.

[0067] Further, along the third direction Z, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source end channel in the memory cell string 400. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain end channel in the memory cell string 400. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (for example, transistor T) in the memory cell string 400 can be completed.

[0068] Continue to see Figure 3 and Figure 4 In some embodiments, the memory stack structure 12 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

[0069] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, a bit line contact BL-CNT and a drain select gate contact SGD-CNT. The bit line contact BL-CNT is coupled to the bit line BL, and for example, the bit line contact BL-CNT may include a connection portion 160 and a channel contact portion 1331.

[0070] The drain selection gate contact SGD-CNT is coupled to the drain selection gate SGD. The array interconnect layer 290 may further include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, the plurality of connection lines may include a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0071] The peripheral device 13 may include a peripheral circuit. The peripheral circuit is configured to control and sense the array device. The peripheral circuit may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array device, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (e.g., a processor and a programmable logic device (PLD) or a storage circuit (e.g., a static random access memory (SRAM)).

[0072] Specifically, in some embodiments, the peripheral device 13 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0073] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0074] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0075] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, so that the storage stack structure 12 and the peripheral device 13 can be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 13 can be coupled to the storage cell string in the semiconductor device 10 to achieve the transmission of electrical signals between the peripheral circuit and the storage cell string. In some possible implementations, a bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other through the bonding interface 500.

[0076] Fig. 7A A top view of a semiconductor device 10 according to an embodiment of the present disclosure; Figure 7B A top view of a semiconductor device 10 according to another embodiment of the present disclosure; Figure 7C The present invention provides a top view of a semiconductor device 10 according to another embodiment.

[0077] See also Fig. 7A , the channel contact portion 1331 is provided in the channel portion 1223 (such as Figure 4 As shown in the figure), the connecting portion 160 is arranged on the channel contact portion 1331, and the bit line BL is arranged on the connecting portion 160. Among them, during the preparation process of the semiconductor device 10, it is necessary to ensure that the channel contact portion 1331 is in precise contact with the channel portion 1223, the connecting portion 160 is in precise contact with the channel contact portion 1331, and the bit line BL is in precise contact with the connecting portion 160, so as to ensure the stability of the semiconductor device 10. However, the two adjacent film layers stacked in the stacking direction may be offset due to the stress generated by the process accumulation, thereby generating an alignment deviation. For example, the channel contact portion 1331 and the channel portion 1223 may be offset due to stress, resulting in a deviation between part of the channel contact portion 1331 and the channel portion 1223, thereby affecting the electrical connection effect between the two. Similarly, refer to Figure 7BThere may be a deviation between the connection portion 160 and the channel contact portion 1331 due to stress generated by process accumulation. There may also be a deviation between the bit line BL and the connection portion 160 due to stress generated by process accumulation.

[0078] In one embodiment, in order to improve the deviation between the channel contact 1331 and the channel portion 1223, the position of the channel contact 1331 may be adjusted when the channel contact 1331 is manufactured, so as to reduce the deviation between the channel contact 1331 and the channel portion 1223. Therefore, in the process of manufacturing the channel contact 1331, the mask required for manufacturing the channel contact 1331 needs to be modified.

[0079] However, in the subsequent process of preparing the connecting portion 160, SADP (Self-aligned Double Patterning) technology will be used. At this time, the position of the connecting portion 160 will change with the change of the position of the channel contact portion 1331. Therefore, in the process of preparing the connecting portion 160, it is necessary to modify the mask required for preparing the connecting portion 160.

[0080] Similarly, in order to ensure accurate contact between the bit line BL and the connection portion 160 , it is also necessary to modify the mask required for preparing the bit line BL.

[0081] In summary, in one embodiment, in order to ensure the stability of the semiconductor device 10, it is necessary to modify the mask required for preparing the channel contact portion 1331, the mask required for preparing the connecting portion 160, and the mask required for preparing the bit line BL, which makes the preparation process of the semiconductor device 10 more complicated.

[0082] See also Figure 7C In the process of preparing the bit line BL, since the width of the bit line BL is small, after modifying the mask required for preparing the bit line BL, the bit line BL is easily broken.

[0083] Based on this, an embodiment of the present disclosure provides a method for preparing a semiconductor device 10 .

[0084] FIG. 8A to FIG. 8B A flowchart of a method for preparing a semiconductor device 10 provided in some embodiments of the present disclosure is provided. 9A to 9E Cross-sectional views corresponding to some steps in the method for preparing the semiconductor device 10 provided in some embodiments of the present disclosure.

[0085] See also Fig. 8A , the method for preparing the semiconductor device 10 includes the following steps S1 to S3.

[0086] S1. Forming a storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along a stacking direction of the stack structure, and each channel structure comprising a channel portion.

[0087] See also Fig.9A , the storage stack structure 12 can be formed on a substrate 11. Among them, the substrate 11 can be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate. The material of the substrate 11 can also be a compound semiconductor. For example, the substrate 11 can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate. The substrate 11 of the present disclosure can also be prepared using other semiconductor materials commonly used in the art.

[0088] In some embodiments, the plurality of channel structures 122 of the memory stack structure 12 are arranged in rows along the first direction X and in columns along the second direction Y. The plurality of channel portions 1223 at the top of the plurality of channel structures 122 are arranged in rows along the first direction X and in columns along the second direction Y.

[0089] Illustratively, step S1 may include the following steps S11 to S14.

[0090] S11, forming an initial stacked structure on a substrate, wherein the initial stacked structure may include a plurality of initial gate dielectric layers and gate replacement layers alternately stacked along a stacking direction Z.

[0091] Here, “alternatingly stacking” means that after an initial gate dielectric layer 1211 is formed on the substrate 11, a gate replacement layer is formed on the initial gate dielectric layer 1211, and then an initial gate dielectric layer 1211 is formed on the gate replacement layer, and so on….

[0092] In the initial stacked structure, the initial gate dielectric layer 1211 and the gate replacement layer can be formed by a thin film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present disclosure.

[0093] The thickness of the initial gate dielectric layer 1211 may be the same or different, the thickness of the multiple gate replacement layers may be the same or different, and the thickness of the initial gate dielectric layer 1211 and the gate replacement layer may be set according to specific process requirements. In practical applications, the gate replacement layer may be removed in a subsequent process and replaced by a conductive material to form a gate layer 1212, i.e., a word line WL (e.g., Figure 4 shown).

[0094] For example, the material of the initial gate dielectric layer 1211 may be silicon oxide, and the material of the gate replacement layer may be silicon nitride.

[0095] S12, etching the initial stacked structure to form a channel hole that penetrates the initial stacked structure in the stacking direction Z and extends to the substrate.

[0096] For example, in step S12 , the channel hole may be formed by a dry or wet etching process, and the formed channel hole penetrates the substrate 11 and exposes a portion of the substrate 11 in the stacking direction Z. In other examples, the communication hole may extend into the substrate 11 .

[0097] S13, forming a channel structure in the channel hole. The channel structure may include a charge blocking layer, a charge trapping layer, a tunneling layer, a channel layer and a supporting portion. The charge blocking layer, the charge trapping layer and the tunneling layer may be combined to form a functional layer.

[0098] In step S13, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially form a functional layer 1220 and a channel layer 1222 on the sidewall of the channel hole. The charge blocking layer 1221 is used to block the outflow of stored charges in the charge capture layer 1224, and the charge capture layer 1224 may pass through the tunneling layer 1225 through the tunneling effect under the action of voltage to achieve writing and erasing of memory data. For example, the material of the charge blocking layer 1221 may be silicon oxide, the material of the charge capture layer 1224 may be nitride, and the material of the tunneling layer 1225 may be oxide. The material of the support portion 1226 may include one or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), and a nitride oxide (e.g., silicon oxynitride). As an option, a chemical mechanical polishing (CMP) may be used to planarize the top surface of the support portion 1226 in the channel hole. The top surface of the channel hole inner support portion 1226 refers to the surface of the channel hole inner support portion 1226 facing away from the substrate 11 .

[0099] In this embodiment, the channel structure 122 further includes a channel portion 1223 , wherein the channel portion 1223 is located at an end of the channel structure 122 away from the substrate 11 , and the channel portion 1223 is electrically connected to the channel layer 1222 .

[0100] S14, replacing the gate replacement layer with a gate line layer.

[0101] The gate replacement layer in the initial stacked structure is removed to form a gate gap, and then a conductive material is filled in the gate gap to form a gate layer 1212. At this time, multiple gate layers 1212 and multiple initial gate dielectric layers 1211 are alternately stacked to form a stacked structure 121.

[0102] Figures 10A to 10C A top view of the structure corresponding to some steps of a method for preparing a semiconductor device 10 provided in some embodiments of the present disclosure.

[0103] S2. A plurality of strip-shaped conductive portions are formed on a surface of one side of the stacking structure along the stacking direction, the plurality of strip-shaped conductive portions extend along a first direction intersecting the stacking direction, and the plurality of strip-shaped conductive portions are arranged at intervals in a second direction. The second direction intersects the first direction, and the second direction intersects the stacking direction.

[0104] See also Fig. 9B In step S2 , a plurality of strip-shaped conductive portions 140 are formed on a surface of the stacked structure 121 away from the substrate 11 .

[0105] See also Fig. 10A Each strip-shaped conductive portion 140 extends along the first direction X, and a plurality of strip-shaped conductive portions 140 are arranged at intervals in the second direction Y.

[0106] For example, a plurality of strip-shaped conductive portions 140 may be arranged in parallel.

[0107] In some examples, each strip-shaped conductive portion 140 is connected to a row of channel portions 1223 (eg, Fig. 9B shown) contact.

[0108] Illustratively, the strip-shaped conductive part 140 includes a first conductive material. For example, the first conductive material may include metal tungsten and / or copper.

[0109] See also Figure 8B In some embodiments, before the above step S2, S20 may also be included.

[0110] S20, forming a first insulating layer on a surface of one side of the stacked structure along a stacking direction.

[0111] For example, the first insulating layer 170 may be formed on a side of the stacked structure 121 away from the substrate 11 by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0112] For example, the material of the first insulating layer 170 may include one or more of a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, and a zirconium oxide layer.

[0113] Please continue reading Figure 8BIn the case where step S20 is included before step S2, step S2 may include: the following steps S21 to S23.

[0114] S21 . Form a first mask layer on the first insulating layer, wherein the first mask layer includes a plurality of first openings.

[0115] For example, in step S21, a first photoresist layer is formed on a side of the first insulating layer 170 away from the substrate 11, and the first photoresist layer is exposed and developed to pattern the first photoresist layer. At this time, a plurality of first openings can be formed in the first photoresist layer. The patterned first photoresist layer can serve as a first mask layer having a plurality of first openings.

[0116] Each of the first openings extends along the first direction X, and a plurality of first openings are arranged at intervals in the Y direction.

[0117] For example, a plurality of first openings may be arranged in parallel.

[0118] S22 , forming a plurality of strip grooves in the first insulating layer by using the plurality of first openings of the first mask layer, wherein the strip grooves expose the channel portions.

[0119] In step S22, the first insulating layer 170 is etched based on the plurality of first openings to form a plurality of strip grooves. For example, the first insulating layer 170 can be etched by dry etching to form the strip grooves. The depth of the strip grooves is not less than the thickness of the first insulating layer 170, thereby exposing the channel portion 1223, so that the filler in the subsequent strip grooves can contact and be electrically connected to the channel portion 1223.

[0120] Each of the strip grooves extends along the first direction X, and a plurality of strip grooves are arranged at intervals in the Y direction.

[0121] For example, a plurality of strip-shaped grooves may be arranged in parallel.

[0122] S23, forming a plurality of strip-shaped conductive parts in the plurality of strip-shaped grooves.

[0123] In some embodiments, a first conductive material is filled in a plurality of strip-shaped grooves to form a plurality of strip-shaped conductive portions 140. For example, the filled first conductive material may include metal tungsten and copper.

[0124] In steps S21 to S23 , the strip grooves have a relatively large size, so the strip grooves are more likely to expose the channel portions 1223 , thereby reducing the difficulty of the manufacturing process.

[0125] In some embodiments, step S23 may include the following steps S231 to S232.

[0126] S231 , depositing a first conductive material, where the first conductive material fills the strip-shaped grooves and covers the first insulating layer.

[0127] For example, in step S231 , the first conductive material may be deposited by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0128] S232, removing the first conductive material deposited on the first insulating layer.

[0129] For example, in step S232, chemical mechanical polishing (CMP) can be used to remove the first conductive material on the first insulating layer. At the same time, since the first conductive material of the strip groove can also be removed, the surface of the strip conductive portion away from the channel portion 1223 can be planarized.

[0130] After executing step S2, step S3 may be executed.

[0131] S3. removing a portion of at least one strip-shaped conductive portion, so that the remaining portion of the strip-shaped conductive portion forms a plurality of channel contact portions spaced apart along the first direction, wherein the channel contact portions are in contact with the channel portion.

[0132] For example, dry etching can be used to etch each strip-shaped conductive portion 140 so that the portion remaining after etching forms a channel contact portion 1331, and then the channel contact portion 1331 is used to contact the channel portion 1223 to achieve electrical connection between the film layer where the channel contact portion 1331 is located and the film layer where the channel portion 1223 is located.

[0133] In step S232 , the surface of the strip-shaped conductive portion that is away from the channel portion 1223 is planarized, so that the connection portion 160 can be formed on the channel contact portion 1331 .

[0134] In the embodiment of the present disclosure, the area of ​​the strip-shaped conductive portion 140 is relatively large, which is conducive to achieving the aligned contact between the strip-shaped conductive portion 140 and a row of channel portions 1223 .

[0135] After the strip-shaped conductive portion 140 is formed, the strip-shaped conductive portion 140 may be etched to form a channel contact portion 1331 , and then the connecting portion 160 may be formed on the channel contact portion 1331 . Among them, when etching the strip conductive portion 140, the etched position of the strip conductive portion 140 can be adjusted according to the position of the channel portion 1223 and the position of the connecting portion 160, that is, the position of the portion of the strip conductive portion 140 removed in step S3 is adjusted, so that the width of the retained channel contact portion 1331 in the first direction X is adjusted, so that the channel contact portion 1331 retained in step S3 can be in contact with its corresponding channel portion 1223, and can also be in contact with its corresponding connecting portion 160, thereby reducing the offset between the channel contact portion 1331 and the channel portion 1223, and the offset between the channel contact portion 1331 and the connecting portion 160, thereby improving the reliability of the electrical connection between the channel contact portion 1331 and the channel portion 1223, and the reliability of the electrical connection between the channel contact portion 1331 and the connecting portion 160, thereby improving the stability of the semiconductor device 10.

[0136] In addition, in the embodiment of the present disclosure, in the above step S3, when removing a portion of at least one strip-shaped conductive portion 140, it is necessary to use a mask layer to etch the strip-shaped conductive portion 140 to form a channel contact portion 1331. In step S3, the position and size of the channel contact portion 1331 retained in step S3 can be determined according to the position of the channel portion 1223 and the position of the connecting portion 160. Therefore, in the process of preparing the semiconductor device 10, the structure of the mask required for preparing the channel contact portion 1331 can be modified, without modifying the structure of the mask required for preparing the connecting portion 160 and the structure of the mask required for the subsequent formation of the bit line BL, thereby reducing the difficulty of the manufacturing process of the semiconductor device 10.

[0137] Please continue reading Figure 8B In some examples, step S3 may include the following steps S31 to S32.

[0138] S31, forming a second mask layer, wherein the second mask layer covers the first mask layer and the plurality of strip-shaped conductive portions; the second mask layer includes a plurality of second openings.

[0139] See also Fig. 10B In some embodiments, a second photoresist layer is formed on the side of the first mask layer and the plurality of strip-shaped conductive portions 140 away from the substrate 11, and the second photoresist layer is exposed, developed, and patterned to form a plurality of second openings 150 in the second photoresist layer. Thus, the patterned second photoresist layer serves as a second mask layer having a plurality of second openings 150.

[0140] The plurality of second openings 150 are sequentially arranged in rows along the first direction X, and the plurality of rows of second openings 150 are sequentially arranged along the second direction Y, and can expose a portion of the strip-shaped conductive portion 140 .

[0141] S32, using the plurality of second openings of the second mask layer to remove a portion of at least one strip-shaped conductive portion to form a plurality of partition grooves, wherein the plurality of partition grooves separate the remaining portion of the strip-shaped conductive portion into a plurality of channel contact portions.

[0142] See also Fig. 10B In some embodiments, the strip-shaped conductive part 140 can be etched in the stacking direction by dry etching based on the plurality of second openings 150, thereby forming a plurality of partitions 151. The depth of the plurality of partitions 151 is greater than or equal to the thickness of the strip-shaped conductive part 140, thereby cutting off the strip-shaped conductive part 140 and separating the remaining portion of the strip-shaped conductive part 140 into a plurality of independent channel contacts 1331.

[0143] Among them, in step S32, the position of the second opening 150 and the width of the second opening 150 in the first direction X can be adjusted according to the position of the channel portion 1223 and the position of the connecting portion 160, thereby adjusting the width of the retained channel contact portion 1331 in the first direction X, so that the channel contact portion 1331 can be in contact with its corresponding channel portion 1223 and can also be in contact with its corresponding connecting portion 160, thereby reducing the offset between the channel contact portion 1331 and the channel portion 1223, as well as the offset between the channel contact portion 1331 and the connecting portion 160, thereby improving the reliability of the electrical connection between the channel contact portion 1331 and the channel portion 1223, as well as the reliability of the electrical connection between the channel contact portion 1331 and the connecting portion 160, thereby improving the stability of the semiconductor device 10. The channel portion 1223 corresponding to the channel contact portion 1331 is the channel portion 1223 that is in contact with and electrically connected to the channel contact portion 1331 , and the connection portion 160 corresponding to the channel contact portion 1331 is the connection portion 160 that is in contact with and electrically connected to the channel contact portion 1331 .

[0144] In addition, in the embodiment of the present disclosure, in the above steps S31 and S32, when removing a portion of at least one strip-shaped conductive portion 140, it is necessary to use the second mask layer to etch the strip-shaped conductive portion 140 to form a channel contact portion 1331. In step S3, the position and size of the channel contact portion 1331 retained in step S3 can be determined according to the position of the channel portion 1223 and the position of the connecting portion 160. Therefore, in the process of preparing the semiconductor device 10, the structure of the second mask layer can be modified without modifying the structure of the mask required for preparing the connecting portion 160 and the structure of the mask required for the subsequent formation of the bit line BL, thereby reducing the difficulty of the manufacturing process of the semiconductor device 10 and shortening the manufacturing cycle.

[0145] In some embodiments, after the above step S3, the following steps S41 and S42 may also be included.

[0146] S41. Fill the plurality of compartments with insulating material.

[0147] For example, a deposition process may be used to fill the insulating layer material, and the filled insulating material may include one or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), and a nitride oxide (e.g., silicon oxynitride). In this way, the insulating material is filled in the trench 151 to insulate the adjacent channel contacts 1331.

[0148] In some embodiments, step S41 may include the following steps S411 to S412.

[0149] S411, depositing insulating material, and filling the insulating material into a plurality of partitions.

[0150] By filling the isolation groove 151 with an insulating material, insulation between two adjacent channel contact portions 1331 is achieved.

[0151] S412 , removing the insulating material deposited on the channel contact portion.

[0152] For example, in step S412, chemical mechanical polishing can be used to remove the insulating material on the channel contact portion 1331. At the same time, since the insulating material protruding from the surface of the partition 151 can also be removed, the surface of the strip conductive portion 140 facing away from the channel portion 1223 can be flattened to facilitate subsequent operations.

[0153] After executing step S41, step S42 may be executed.

[0154] S42, removing the first mask layer and the second mask layer.

[0155] In some embodiments, in the process of planarizing the top surface of the insulating material by chemical mechanical polishing, the excess insulating material, the first mask layer and the second mask layer can be removed at the same time. In this case, step S42 can be completed in the same process as step S412. The excess insulating material removed in step S42 refers to the insulating material located on the second mask layer and the insulating material protruding from the channel contact portion 1331.

[0156] In some other embodiments, the first mask layer may be removed after step S232 , and the insulating material and the second mask layer may be removed after step S412 .

[0157] Please continue reading Fig. 10B , the plurality of second openings 150 are arranged in a plurality of rows, the plurality of second openings 150 in a row of second openings 150 are sequentially arranged along the first direction X, and the plurality of rows of second openings 150 are sequentially arranged along the second direction Y. The plurality of second openings 150 in a row of second openings 150 are arranged at intervals on the strip-shaped conductive portion 140 .

[0158] In some embodiments, the plurality of channel structures 122 of the memory stack structure 12 are arranged in rows at intervals along the first direction X, and are arranged in columns at intervals along the second direction Y. By forming a plurality of second openings 150 that are arranged in rows at intervals along the first direction X and are arranged in sequence along the second direction Y, after removing the portions of the plurality of strip-shaped conductive portions 140 corresponding to the plurality of second openings 150, the remaining portions of the plurality of strip-shaped conductive portions 140 (i.e., the plurality of channel contact portions 1331) can be arranged at intervals in the first direction X and arranged in sequence in the second direction Y, and it is ensured that the plurality of channel contact portions 1331 and the channel portions 1223 of the top surface of the plurality of channel structures 122 away from the substrate 11 are precisely covered.

[0159] Please continue reading Fig. 10B and Fig. 10C The distance between two adjacent second openings 150 in the first direction X is the spacing H1, and at least two spacing H1s are not equal.

[0160] For example, the trench spacing H1 is the width of the channel contact portion 1331 in the first direction X. The two trench spacings H1 are different, so that the widths H2 of the two channel contact portions 1331 in the first direction X can be different.

[0161] The embodiment of the present disclosure uses the spacing between grooves H1 between the plurality of second openings 150 arranged in a row at intervals in the first direction X to adjust the width of the channel contact portion 1331 in the first direction X, so as to compensate for the alignment deviation caused by the above-mentioned stress, thereby improving the accuracy of alignment between the channel contact portion 1331 and the channel portion 1223. For example, in a row of a plurality of second openings 150 arranged at intervals, the size of each spacing between grooves H1 can be designed in advance according to the alignment deviation between the corresponding channel portions 1223 and the connecting portion 160. By adjusting the spacing between grooves H1, the size of the channel contact portion 1331 is adjusted, thereby compensating for the alignment deviation of each channel contact portion 1331, so that the channel contact portion 1331 can be electrically connected to the corresponding channel portion 1223 and the connecting portion 160. Since the alignment deviations between the corresponding channel portions 1223 and the connecting portions 160 may be different, the size of each channel contact portion 1331 may be different, that is, the size of each spacing H1 between the grooves in the second mask may be different, thereby improving the flexibility of the second mask in correcting the position (or size) of the channel contact portion 1331.

[0162] Fig.11 A flow chart of another method for preparing a semiconductor device provided for some embodiments of the present disclosure; Fig.12 A top view of a semiconductor device provided for some embodiments of the present disclosure.

[0163] See also Fig.11 and Fig.12 The method for preparing the semiconductor device 10 further includes steps S5 to S8.

[0164] S5. Form a second insulating layer on a side of the plurality of channel contacts away from the stacked structure, and form connection holes on the second insulating layer.

[0165] See also Fig.9D In step S5 , the second insulating layer 180 is also located on the side of the first insulating layer 170 away from the stacked structure 121 .

[0166] In some embodiments, the second insulating layer 180 may be deposited on a side of the plurality of channel contacts 1331 away from the stacked structure 121 by using existing conventional thin film deposition processes, such as any one or more of CVD, PVD and ALD.

[0167] For example, the material of the second insulating layer 180 can be any suitable insulating material, such as oxide, nitride, etc.

[0168] The material of the second insulating layer 180 may be the same as or different from that of the first insulating layer 170 , and the thickness of the second insulating layer 180 may be the same as or different from that of the first insulating layer 170 .

[0169] In step S5 , a connection hole may be formed on the second insulating layer 180 by an etching process, wherein the depth of the connection hole is greater than or equal to the thickness of the second insulating layer 180 , thereby exposing the channel contact portion 1331 .

[0170] S6. A connection portion is formed in the connection hole, wherein the connection portion is in contact with the channel contact portion.

[0171] In step S6, the second conductive material may be filled in the connection hole to form a connection portion 160 (as shown in 9D). For example, the filled second conductive material may include metal tungsten and copper. Then, chemical mechanical polishing may be used to planarize the top surface of the conductive material and remove excess second conductive material.

[0172] S7. Form a third insulating layer on a side of the second insulating layer away from the stacked structure, and form a connecting groove on the third insulating layer.

[0173] In step S7, an existing conventional thin film deposition process, such as any one or more of CVD, PVD, and ALD, can be used to deposit and form a third insulating layer 171 on the side of the second insulating layer 180 away from the stacked structure 121. For example, the material of the third insulating layer 171 can be any suitable insulating material, such as oxide, nitride, etc. Among them, the material of the third insulating layer 171 can be the same as or different from the first insulating layer 170 and the second insulating layer 180; the thickness of the third insulating layer 171 can be the same as or different from the first insulating layer 170 and the second insulating layer 180. A connection groove is formed on the third insulating layer 171 by etching, and the groove depth of the connection groove is greater than or equal to the thickness of the third insulating layer 171, thereby exposing the connection portion 160.

[0174] The connecting groove is strip-shaped and extends along the second direction Y, and a plurality of strip-shaped grooves are arranged in sequence along the first direction X.

[0175] S8. Forming a conductive line in the connection groove.

[0176] See also Fig.12 In step S8, a third conductive material may be filled in the connection groove to form a conductive line 190. For example, the filled third conductive material may include metal tungsten and copper. As an option, chemical mechanical polishing may be used to planarize the top surface of the third conductive material, and excess third conductive material may be removed. The formed conductive line 190 contacts the connection portion 160 and realizes electrical connection.

[0177] The conductive line 190 may be the bit line BL provided in some of the above embodiments (eg Figure 3 shown).

[0178] Based on the semiconductor device manufacturing methods provided in some of the above embodiments, the embodiments of the present disclosure further provide a semiconductor device 10, which can be manufactured by the semiconductor device manufacturing methods described above.

[0179] See also Fig.9E , the semiconductor device 10 may include: a storage stack structure 12, and a plurality of spaced channel contacts 1331. The storage stack structure 12 includes a stack structure 121 and a plurality of channel structures 122, the plurality of channel structures 122 penetrate the stack structure 121 along the stacking direction of the stack structure 121, and each channel structure 122 includes a channel portion 1223. A plurality of spaced channel contacts 1331 are arranged on a side surface of the stack structure 121 along the stacking direction, and the channel contacts 1331 are in contact with the channel portion 1223. At least two channel contacts 1331 have different widths in a first direction, and the first direction intersects with the stacking direction.

[0180] Among them, the semiconductor device 10 provided in the embodiment of the present disclosure is manufactured by the preparation method of the semiconductor device 10 provided in some of the above embodiments. Therefore, the semiconductor device 10 provided in the embodiment of the present disclosure has all the beneficial effects of the preparation method of the semiconductor device 10 provided in some of the above embodiments, which will not be repeated here.

[0181] The multiple channel contacts 1331 formed in the embodiment of the present disclosure have different widths in the first direction X. When preparing the channel contacts 1331, the widths of at least part of the channel contacts 1331 in the first direction X can be adjusted according to the offset between the film layers (such as the channel portion 1223 or the connecting portion 160) adjacent to the channel contacts 1331. Then, the widths of different channel contacts 1331 in the first direction X are obtained to improve the coverage accuracy between the channel contacts 1331 and the film layers adjacent to them, improve the reliability of the electrical connection between the channel contacts 1331 and the channel portion 1223, and improve the reliability of the electrical connection between the channel contacts 1331 and the connecting portion 160, so as to improve the stability of the semiconductor device 10.

[0182] At the same time, in the embodiment of the present disclosure, when adjusting the mask size corresponding to the channel contact portion 1331, the offset of the subsequent connecting portion 160 is pre-added, so that the channel contact portion 1331 can be aligned with the channel portion 1223 while also being aligned with the connecting portion 160, thereby omitting the subsequent adjustment of the mask structure corresponding to the connecting portion 160, effectively reducing the process difficulty, shortening the production cycle and reducing the production cost.

[0183] Fig.13 Schematic diagram of the structure of the channel contact portion 1331 provided in some embodiments of the present disclosure. It should be noted that Fig.13 In FIG. 1 , only a portion of a row of channel contacts 1331 is illustrated.

[0184] In some embodiments, the channel contact portion 1331 includes two first surfaces 1332 arranged opposite to each other in the stacking direction Z and multiple side surfaces connected to the first surfaces 1332, wherein the multiple side surfaces include at least a first side surface 1333 extending along the first direction X and a second side surface 1334 extending along the second direction Y.

[0185] For example, the first side surface 1333 may be a plane, and the second side surface 1334 may be a plane.

[0186] See also Fig. 10B and Fig.13 , the channel contact portion 1331 can be obtained by etching the strip-shaped conductive portion 140, that is, the portion remaining after etching the strip-shaped conductive portion 140 constitutes the channel contact portion 1331. In combination with the structural features of the strip-shaped conductive portion 140, the channel contact portion 1331 formed based on the strip-shaped conductive portion 140 may include two first surfaces 1332 arranged opposite to each other in the stacking direction Z, a first side surface 1333 extending along the first direction X, and a second side surface 1334 extending along the second direction Y. In which, for example, the two first surfaces 1332 are respectively used to contact the channel portion 1223 and the connecting portion 160 arranged corresponding to the channel contact portion 1331.

[0187] In some embodiments, the number of the first side surfaces 1333 is two, and the two first side surfaces 1333 are arranged opposite to each other in the second direction Y. For example, the two first side surfaces 1333 are arranged in parallel.

[0188] The number of the second side surfaces 1334 is two, and the two second side surfaces 1334 are arranged opposite to each other in the first direction X. For example, the two second side surfaces 1334 are arranged in parallel.

[0189] Please continue reading Fig. 10B and Fig.13 According to the formation process of the channel contact portion 1331 and the structural features of the strip-shaped conductive portion 140 , the channel contact portion 1331 formed based on the strip-shaped conductive portion 140 may include two second side surfaces 1334 disposed opposite to each other in the first direction X, and two first side surfaces 1333 disposed opposite to each other in the second direction Y. In an exemplary embodiment, the two second side surfaces 1334 and the first side surfaces 1333 are used to enclose the two first surfaces 1332 to form a three-dimensional channel contact portion 1331 .

[0190] In some embodiments, the first side surfaces 1333 of the plurality of channel contacts 1331 arranged at intervals in the first direction X and located on the same side of the first surface 1332 in the second direction Y are coplanar.

[0191] By way of example, the first surface 1332 may include a first side edge and a first side edge that are oppositely disposed in the second direction Y. The first side surface 1333 may include a first side surface 1333a and a first side surface 1333b that are oppositely disposed in the second direction Y. The first side surface 1333a is connected to the first side edge of the first surface 1332; and the first side surface 1333b is connected to the second side edge of the first surface 1332. By way of example, in a row of multiple channel contacts 1331, the multiple first side edges 1333a of the multiple channel contacts 1331 are coplanar, and the multiple first side edges 1333b of the multiple channel contacts 1331 are coplanar.

[0192] In the embodiment of the present disclosure, since the first side surfaces 1333a of the plurality of channel contacts 1331 are coplanar and the first side surfaces 1333b are coplanar, the widths of the plurality of channel contacts 1331 in the second direction Y remain consistent, thereby reducing the possibility of alignment deviation between the channel contacts 1331 and the channel portion 1223 when forming the plurality of channel contacts 1331 in step S3 of the above embodiment, and improving the accuracy of alignment between the connection portion 160 and the channel contact 1331 in the subsequent film layer. The width of the channel contact 1331 in the second direction Y is equal to the distance between the two first side surfaces.

[0193] In some embodiments, a cross-section of the channel contact portion 1331 on a reference plane is rectangular or quasi-rectangular, wherein the reference plane is perpendicular to the stacking direction.

[0194] For example, a plane perpendicular to the stacking direction Z is used as a reference plane. The channel contact portion 1331 is projected onto the reference plane, and the projection outline of the channel contact portion 1331 on the reference plane is obtained to be rectangular or quasi-rectangular. That is, the cross-section of the channel contact portion 1331 on the reference plane is rectangular or quasi-rectangular. The rectangle can be either a square or a rectangle. The rectangle can be a standard rectangle, in which case the angle formed by two adjacent sides of the rectangle is a right angle. Two adjacent straight sides in a quasi-rectangle are perpendicular to each other, and the intersection of the two straight sides is in the shape of an arc.

[0195] The embodiment of the present disclosure effectively increases the contact surface of the channel contact portion 1331 by setting the cross-section of the channel contact portion 1331 on the reference plane to be rectangular or quasi-rectangular, which is beneficial to the alignment and coverage when the connecting portion 160 is subsequently formed, and improves the accuracy of the alignment between the connecting portion 160 and the channel contact portion 1331.

[0196] In some embodiments, a cross-sectional area of ​​the channel portion 1223 on the reference plane is smaller than a cross-sectional area of ​​the channel contact portion 1331 on the reference plane.

[0197] For example, when projecting onto the reference plane along a direction perpendicular to the reference plane, the orthographic projection of the channel portion 1223 on the reference plane is within the range of the orthographic projection of the channel contact portion 1331 on the reference plane.

[0198] With such arrangement, when the channel contact portion 1331 contacts the channel portion 1223 , the contact surface of the channel contact portion 1331 is larger than the contact surface of the channel portion 1223 , which is beneficial for achieving precise coverage of the channel portion 1223 by the channel contact portion 1331 and improving the alignment accuracy between the channel contact portion 1331 and the channel portion 1223 .

[0199] In some embodiments, the semiconductor device 10 may further include: a plurality of connection portions 160, the plurality of connection portions 160 being arranged on a side of the channel contact portion 1331 away from the stacked structure 121, one connection portion 160 being in contact with one channel contact portion 1331, and an area of ​​a cross section of the connection portion 160 on a reference plane being smaller than an area of ​​a cross section of the channel contact portion 1331 on the reference plane.

[0200] For example, when a projection is made onto the reference plane along a direction perpendicular to the reference plane, the orthographic projection of the connection portion 160 on the reference plane is within the range of the orthographic projection of the channel contact portion 1331 on the reference plane.

[0201] With such a configuration, when the connecting portion 160 contacts the channel contact portion 1331, the contact surface of the channel contact portion 1331 is larger than the contact surface of the connecting portion 160, which is conducive to setting the connecting portion 160 on the channel contact portion 1331, improving the alignment accuracy between the connecting portion 160 and the channel contact portion 1331, and further improving the electrical connection effect between the connecting portion 160 and the channel contact portion 1331.

[0202] In some embodiments, the semiconductor device 10 may further include a plurality of conductive wires 190, which are disposed on a side of the plurality of connection portions 160 away from the plurality of channel contacts 1331, and one conductive wire 190 is in contact with at least one connection portion 160. For example, the plurality of conductive wires 190 may be used as a plurality of bit lines in the semiconductor device 10. In this manner, the conductive wires 190 may be electrically connected to the connection portions 160, and further, the entire semiconductor device 10 may be electrically connected to other devices through the connection between the conductive wires 190 and the peripheral circuit.

[0203] The semiconductor device 10 provided in some of the above embodiments may be a three-dimensional memory 911 , or may be a part of the three-dimensional memory 911 . For example, the semiconductor device 10 may be a memory stack structure 12 .

[0204] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along a stacking direction of the stack structure, each channel structure comprising a channel portion; A plurality of strip-shaped conductive portions are formed on a surface of one side of the stacked structure along the stacking direction, the plurality of strip-shaped conductive portions extend along a first direction intersecting the stacking direction, and the plurality of strip-shaped conductive portions are arranged at intervals in a second direction, the second direction intersects the first direction, and the second direction intersects the stacking direction; A portion of at least one strip-shaped conductive portion is removed so that the remaining portion of the strip-shaped conductive portion forms a plurality of channel contact portions arranged at intervals along the first direction, and the channel contact portions are in contact with the channel portion.

2. The preparation method according to claim 1, characterized in that: Before forming a plurality of strip-shaped conductive parts on a surface of one side of the stacked structure along the stacking direction, the method further comprises: Forming a first insulating layer on a surface of one side of the stacked structure along the stacking direction; The method of forming a plurality of strip-shaped conductive parts on a surface of one side of the stacked structure along the stacking direction comprises: forming a first mask layer on the first insulating layer, wherein the first mask layer comprises a plurality of first openings; Using the plurality of first openings of the first mask layer, a plurality of strip grooves are formed in the first insulating layer, wherein the strip grooves expose the channel portions; The plurality of strip-shaped conductive portions are formed in the plurality of strip-shaped grooves.

3. The preparation method according to claim 2, characterized in that: The removing of a portion of at least one strip-shaped conductive portion so that the remaining portion of the strip-shaped conductive portion forms a plurality of channel contact portions spaced apart along the first direction comprises: forming a second mask layer, wherein the second mask layer covers the first mask layer and the plurality of strip-shaped conductive portions; the second mask layer includes a plurality of second openings; A portion of at least one strip-shaped conductive portion is removed by using the plurality of second openings of the second mask layer to form a plurality of partition grooves, wherein the plurality of partition grooves separate the remaining portion of the strip-shaped conductive portion into a plurality of channel contact portions.

4. The preparation method according to claim 3, characterized in that: The plurality of second openings are arranged in a plurality of rows, the plurality of second openings in a row of second openings are arranged sequentially along the first direction, and the plurality of rows of second openings are arranged sequentially along the second direction; Wherein, a plurality of second openings in a row of second openings are arranged at intervals on the strip-shaped conductive portion.

5. The preparation method according to claim 3, characterized in that: The distance between two adjacent second openings in the first direction is a spacing between the grooves, and at least two spacing between the grooves are not equal.

6. The preparation method according to claim 3, characterized in that: Also includes: Filling the plurality of compartments with insulating material; The first mask layer and the second mask layer are removed.

7. The preparation method according to any one of claims 1 to 6, characterized in that: Also includes: forming a second insulating layer on a side of the plurality of channel contacts away from the stacked structure, and forming a connection hole on the second insulating layer; forming a connection portion in the connection hole, the connection portion being in contact with the channel contact portion; forming a third insulating layer on a side of the second insulating layer away from the stacked structure, and forming a connecting groove on the third insulating layer; A conductive line is formed in the connecting groove.

8. A semiconductor device, characterized in that: include: A storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along a stacking direction of the stack structure, each channel structure comprising a channel portion; A plurality of spaced-apart channel contact portions are disposed on a side surface of the stacked structure along the stacking direction, wherein the channel contact portions are in contact with the channel portion, wherein at least two of the channel contact portions have different widths in a first direction, and the first direction intersects with the stacking direction.

9. The semiconductor device according to claim 8, characterized in that The channel contact portion includes two first surfaces arranged opposite to each other in the stacking direction and a plurality of side surfaces connected to the first surfaces, wherein the plurality of side surfaces include at least a first side surface extending along the first direction and a second side surface extending along the second direction.

10. The semiconductor device according to claim 9, characterized in that The number of the first side surfaces is two, and the two first side surfaces are arranged opposite to each other in the second direction; The number of the second side surfaces is two, and the two second side surfaces are arranged opposite to each other in the first direction.

11. The semiconductor device according to claim 9, characterized in that The first side surfaces of the plurality of channel contacts arranged at intervals in the first direction and located on the same side of the first surface in the second direction are coplanar.

12. The semiconductor device according to claim 9, characterized in that The cross section of the channel contact portion on a reference plane is rectangular or quasi-rectangular, wherein the reference plane is perpendicular to the stacking direction.

13. The semiconductor device according to claim 12, characterized in that An area of ​​a cross section of the channel portion on the reference plane is smaller than an area of ​​a cross section of the channel contact portion on the reference plane.

14. The semiconductor device according to any one of claims 8 to 13, characterized in that: Also includes: A plurality of connection parts are arranged on a side of the channel contact part away from the stacked structure, one connection part contacts one channel contact part, and the cross-sectional area of ​​the connection part on the reference plane is smaller than the cross-sectional area of ​​the channel contact part on the reference plane.

15. The semiconductor device according to claim 14, characterized in that Also includes: A plurality of conductive lines are arranged on a side of the plurality of connection portions away from the plurality of channel contact portions, and one conductive line contacts at least one of the connection portions.

16. The semiconductor device according to claim 15, characterized in that Also includes: The peripheral device is electrically connected to the conductive line.

17. A storage system, characterized in that: include: A semiconductor device as claimed in any one of claims 8 to 16; The controller is coupled to the semiconductor device to control the semiconductor device to store data.

18. An electronic device, characterized in that: Comprising the storage system as claimed in claim 17.

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