Semiconductor device and manufacturing method thereof
By forming an interlayer dielectric layer on the first plate of the high-voltage capacitor and etching to form a deep groove, integrating the first and second plates of the silicon capacitor, the problem of high integration cost between high-voltage capacitors and silicon capacitors in the prior art is solved, and saving process steps and improving product competitiveness is achieved.
Patent Information
- Application Number
- CN202411958080.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-25
AI Technical Summary
The prior art is difficult to integrate high-voltage capacitors and silicon capacitors at low cost in the same process, resulting in many process steps and high costs, affecting product competitiveness.
By forming an interlayer dielectric layer on the first electrode plate of the high-voltage capacitor and etching to form a deep groove, the first electrode plate of the silicon capacitor is formed on the side wall and bottom of the deep groove, and is connected with the first electrode plate of the high-voltage capacitor, the second electrode plate of the silicon capacitor fills the deep groove, realizing the integration of the high-voltage capacitor and the silicon capacitor.
This method saves process steps, reduces production costs, improves product competitiveness, and avoids the metal layer and conductive vias required to separately draw out the first electrode of the high voltage capacitor, reduces parasitic resistance and increases integration.
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Figure CN119894009A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] During chip design and manufacturing, the process of designing multiple high-voltage functional devices on a single chip can improve product competitiveness.
[0003] High voltage capacitors (HVCAP, voltage is 1000V ~ 6000V) and silicon capacitors (SICAP) are two types of capacitor devices with independent structures and functions. High voltage capacitors can be integrated on functional semiconductor chips, or they can be packaged together with functional semiconductor chips as capacitor isolators. Silicon capacitors (SICAP) use semiconductor deep trench technology. Compared with parallel plate capacitors such as MOS capacitors and MIM capacitors, they can greatly improve capacitance density and capacitance, and can save a lot of chip area. Under the same layout area, the actual area of silicon capacitors is the surface area of the entire deep trench.
[0004] High voltage capacitors are used as capacitive isolators to isolate different voltage domains, including automotive isolation devices that allow safe transmission of electrical signals between different voltage domains. Silicon capacitors have important applications in new energy vehicle battery management systems, drive systems, etc. due to their high stability, high reliability, high density, low thickness, low equivalent series inductance (ESL), and low equivalent series resistance (ESR).
[0005] Integrating high-voltage capacitors and silicon capacitors in the same process at low cost to improve product competitiveness is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention
[0006] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which integrates a high-voltage capacitor and a silicon capacitor in the same process, thereby saving process steps, saving manufacturing costs, and improving product competitiveness.
[0007] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps:
[0008] forming a first plate of a high voltage capacitor;
[0009] Forming at least one interlayer dielectric layer on the first electrode plate of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor;
[0010] Etching the interlayer dielectric layer to form a deep groove;
[0011] A first electrode plate of a silicon capacitor is formed on the sidewall and bottom of the deep trench, the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor, and the first electrode plate of the silicon capacitor extends from the sidewall of the deep trench to the interlayer dielectric layer on the top layer as an extraction electrode of the first electrode plate of the silicon capacitor; a dielectric layer of a silicon capacitor is formed on the sidewall and bottom of the deep trench, the dielectric layer of the silicon capacitor covers the first electrode plate of the silicon capacitor; a second electrode plate of the silicon capacitor is formed in the deep trench, the second electrode plate of the silicon capacitor fills the deep trench; and
[0012] A second electrode plate of the high voltage capacitor is formed on the top interlayer dielectric layer.
[0013] Optionally, the step of forming a first electrode plate of a high voltage capacitor includes:
[0014] Providing a substrate, and forming a bottom interlayer dielectric layer on the substrate;
[0015] forming a metal layer, wherein the metal layer covers a portion of the bottom interlayer dielectric layer;
[0016] forming a first interlayer dielectric layer, the first interlayer dielectric layer covering the metal layer and the bottom interlayer dielectric layer; forming a conductive through hole in the first interlayer dielectric layer connected to the metal layer;
[0017] A first electrode plate of the high-voltage capacitor is formed, wherein the first electrode plate of the high-voltage capacitor covers a portion of the first interlayer dielectric layer, and the first electrode plate of the high-voltage capacitor is connected to the first metal layer through the conductive through hole.
[0018] Optionally, in a direction perpendicular to the substrate, the first electrode plate of the high-voltage capacitor covers a portion of the metal layer.
[0019] Optionally, all of the interlayer dielectric layers are etched to form deep grooves exposing the metal layer, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor through the metal layer.
[0020] Optionally, the method of forming at least one interlayer dielectric layer on the first electrode plate of the high-voltage capacitor as the dielectric layer of the high-voltage capacitor includes:
[0021] forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first electrode plate of the high-voltage capacitor and the first interlayer dielectric layer;
[0022] A third interlayer dielectric layer and a fourth interlayer dielectric layer are sequentially formed on the second interlayer dielectric layer.
[0023] Optionally, the material of the bottom interlayer dielectric layer, the first interlayer dielectric layer and the second interlayer dielectric layer is the same, and the material includes ethyl silicate, borophosphosilicate glass or a low dielectric constant material; the material of the third interlayer dielectric layer includes silicon oxynitride, and the material of the fourth interlayer dielectric layer includes silicon nitride.
[0024] Optionally, the method of etching the interlayer dielectric layer to form a deep trench includes:
[0025] forming a photoresist layer on the top interlayer dielectric layer;
[0026] Exposing and developing the photoresist layer to form a patterned photoresist layer;
[0027] Using the patterned photoresist layer as a mask, etching all interlayer dielectric layers until the metal layer is exposed; and
[0028] The patterned photoresist layer is removed.
[0029] Optionally, the lead-out terminal of the first plate of the high-voltage capacitor, the lead-out terminal of the first plate of the silicon capacitor, and the lead-out terminal of the second plate of the silicon capacitor are formed simultaneously with the formation of the second plate of the high-voltage capacitor;
[0030] The method of forming a second plate of a high voltage capacitor on a top interlayer dielectric layer comprises:
[0031] forming a conductive material layer, wherein the conductive material layer covers the top interlayer dielectric layer;
[0032] The conductive material layer is etched to expose a portion of the top interlayer dielectric layer, and the conductive material layer directly above the first electrode plate of the high-voltage capacitor is retained as the second electrode plate of the high-voltage capacitor, the conductive material layer on the lead-out electrode is retained as the first electrode plate of the high-voltage capacitor and the first lead-out end of the first electrode plate of the silicon capacitor, and the conductive material layer on the second electrode plate of the silicon capacitor is retained as the second lead-out end of the second electrode plate of the silicon capacitor.
[0033] Optionally, the material of the first plate and the second plate of the high-voltage capacitor includes copper, tungsten, aluminum, ruthenium or cobalt; the material of the first plate of the silicon capacitor includes titanium nitride, the material of the second plate of the silicon capacitor includes tungsten, and the dielectric layer of the silicon capacitor includes a silicon nitride layer or a stack consisting of silicon oxide-silicon nitride-silicon oxide.
[0034] In order to solve the above technical problem, according to a second aspect of the present invention, a semiconductor device is further provided, which is manufactured by the above-mentioned method for manufacturing a semiconductor device, and the semiconductor device comprises:
[0035] A first plate of a high voltage capacitor;
[0036] At least one interlayer dielectric layer is located on the first electrode plate of the high-voltage capacitor and serves as the dielectric layer of the high-voltage capacitor; a deep groove penetrating the interlayer dielectric layer is formed in the interlayer dielectric layer;
[0037] A first electrode plate of the silicon capacitor is located on the sidewall and bottom of the deep trench, the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor, and the first electrode plate of the silicon capacitor extends from the sidewall of the deep trench to the top interlayer dielectric layer as an extraction electrode of the first electrode plate of the silicon capacitor;
[0038] A dielectric layer of the silicon capacitor, located on the sidewall and bottom of the deep trench and covering the first electrode plate of the silicon capacitor;
[0039] a second electrode plate of the silicon capacitor, located in the deep trench and filling the deep trench; and
[0040] The second plate of the high voltage capacitor is located on the top interlayer dielectric layer.
[0041] In summary, in the semiconductor device and its manufacturing method provided by the present invention, firstly, a first plate of a high-voltage capacitor is formed, then at least one interlayer dielectric layer is formed on the first plate as the dielectric layer of the high-voltage capacitor, then the interlayer dielectric layer is etched to form a deep groove, then the first plate of a silicon capacitor is formed on the sidewall and bottom of the deep groove, the first plate of the silicon capacitor is connected to the first plate of the high-voltage capacitor, and the first plate of the silicon capacitor extends from the sidewall of the deep groove to the interlayer dielectric layer on the top layer as the lead-out electrode of the first plate of the silicon capacitor; a dielectric layer of a silicon capacitor is formed on the sidewall and bottom of the deep groove, the dielectric layer of the silicon capacitor covers the first plate of the silicon capacitor; a second plate of a silicon capacitor is formed in the deep groove, the second plate of the silicon capacitor fills the deep groove, and then a second plate of a high-voltage capacitor is formed on the interlayer dielectric layer on the top layer. The present invention integrates the production of high-voltage capacitors and silicon capacitors in one process, saves process steps, reduces production costs, and improves product competitiveness.
[0042] At the same time, the first electrode plate of the silicon capacitor extends from the side wall of the deep groove to the top interlayer dielectric layer as the lead-out electrode of the first electrode plate of the silicon capacitor, and can lead out the first electrode plate of the silicon capacitor and the first electrode plate of the high-voltage capacitor at the same time, saving the metal layer and conductive through-hole steps required for leading out the first electrode of the high-voltage capacitor separately, saving process steps, and reducing production costs.
[0043] Furthermore, the first plate and the second plate of the silicon capacitor are both made of conductive materials, and ion implantation is not required, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves can be accommodated in the interlayer dielectric layer, further increasing the integration.
[0044] In addition, the dielectric layer of the silicon capacitor uses ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown in weak locations caused by dielectric defects and dielectric uniformity during operation. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.
[0046] Figures 2 to 9 It is a schematic structural diagram of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.
[0047] Description of reference numerals:
[0048] 100-substrate; 101-metal layer; 110-bottom interlayer dielectric layer; 111-first interlayer dielectric layer; 112-second interlayer dielectric layer; 113-third interlayer dielectric layer; 114-fourth interlayer dielectric layer; 120-patterned first photoresist layer; 121-deep groove; 130-patterned second photoresist layer; 140-patterned third photoresist layer; 151-first passivation layer; 152-second passivation layer; 210-first plate of high-voltage capacitor; 212-first lead-out terminal; 220-second plate of high-voltage capacitor; 221-third conductive material layer; 310-first plate of silicon capacitor; 311-first conductive material layer; 312-lead-out electrode; 320-dielectric layer of silicon capacitor; 321-insulating material layer 321; 330-second plate of silicon capacitor; 331-second conductive material layer 331; 332-second lead-out terminal. DETAILED DESCRIPTION
[0049] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0050] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0051] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 As shown, the method for manufacturing a semiconductor device comprises the following steps:
[0052] S1: forming the first plate of the high voltage capacitor;
[0053] S2: forming at least one interlayer dielectric layer on the first electrode plate of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor;
[0054] S3: etching the interlayer dielectric layer to form a deep groove;
[0055] S4: forming a first electrode plate of a silicon capacitor on the sidewall and bottom of the deep trench, the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor, and the first electrode plate of the silicon capacitor extends from the sidewall of the deep trench to the interlayer dielectric layer on the top layer as an extraction electrode of the first electrode plate of the silicon capacitor; forming a dielectric layer of a silicon capacitor on the sidewall and bottom of the deep trench, the dielectric layer of the silicon capacitor covers the first electrode plate of the silicon capacitor; forming a second electrode plate of the silicon capacitor in the deep trench, the second electrode plate of the silicon capacitor fills the deep trench; and
[0056] S5: forming a second electrode plate of the high-voltage capacitor on the top interlayer dielectric layer.
[0057] Figures 2 to 9 FIG. 1 is a schematic diagram of the structure of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 , Figures 2 to 9 The method for manufacturing a semiconductor device provided by an embodiment of the present invention is described in detail.
[0058] In step S1, refer to Figure 2 As shown, a first plate 210 of a high voltage capacitor is formed.
[0059] In one embodiment of the present invention, the steps of forming the first electrode plate 210 of the high voltage capacitor include:
[0060] First, step S11 is performed to provide a substrate 100 , and to form a bottom interlayer dielectric layer 110 on the substrate 100 .
[0061] In this embodiment, the material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc., or silicon on insulator, germanium on insulator; or it can also be other materials, such as III-V compounds such as gallium arsenide. In one embodiment, the substrate 100 is a silicon substrate. The material of the bottom interlayer dielectric layer 110 can be tetraethyl ortho silicate (TEOS), boro-phospho-silicate glass (BPSG), or other suitable dielectric materials, such as low dielectric constant materials (low-k dielectric materials) or any combination of these materials. The bottom interlayer dielectric layer 110 can be formed by any suitable process known to those skilled in the art, such as atomic layer deposition process (ALD), chemical vapor deposition process (CVD), physical vapor deposition process (PVD), etc.
[0062] Next, step S12 is performed to form a metal layer 101 on the bottom interlayer dielectric layer 110, wherein the metal layer 101 covers a portion of the bottom interlayer dielectric layer 110. The material of the metal layer 101 includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt.
[0063] Then, step S13 is performed to form a first interlayer dielectric layer 111 on the metal layer 101, wherein the first interlayer dielectric layer 111 covers the metal layer 101 and the bottom interlayer dielectric layer 110. The material and the forming method of the first interlayer dielectric layer 111 may be the same as the material and the forming method of the bottom interlayer dielectric layer 110, but are certainly not limited thereto. Afterwards, the first interlayer dielectric layer 111 is etched to form a through hole exposing the metal layer 101, and a conductive material is filled in the through hole to form a conductive through hole.
[0064] Next, step S14 is performed to form the first electrode plate 210 of the high-voltage capacitor on the first interlayer dielectric layer 111, wherein the first electrode plate 210 of the high-voltage capacitor covers a portion of the first interlayer dielectric layer 111, and the first electrode plate 210 of the high-voltage capacitor is connected to the metal layer 101 through the conductive through hole.
[0065] In one embodiment, in a direction perpendicular to the substrate 100, the first electrode 210 of the high-voltage capacitor covers a portion of the metal layer 101, that is, the first electrode 210 of the high-voltage capacitor has only a partial overlap with the metal layer 101, and the first electrode 210 of the high-voltage capacitor and the dielectric layer of the subsequently formed high-voltage capacitor and the second electrode of the high-voltage capacitor constitute a high-voltage capacitor, and the first metal layer 101 is used to connect the first electrode 210 of the high-voltage capacitor to an external circuit and to connect to the first electrode plate of the subsequently formed silicon capacitor.
[0066] In another embodiment of the present invention, the first electrode 210 of the high-voltage capacitor can be formed directly on the underlying interlayer dielectric layer 110 without forming the metal layer 101, and the first electrode of the subsequent silicon capacitor can be directly connected to the first electrode 210 of the high-voltage capacitor, which is not limited by the present invention.
[0067] In step S2, please continue to refer to Figure 2 As shown, at least one interlayer dielectric layer is formed on the first electrode plate 210 of the high-voltage capacitor as the dielectric layer of the high-voltage capacitor.
[0068] In this embodiment, an interlayer dielectric layer, such as a second interlayer dielectric layer 112, may be formed on the first electrode plate 210 of the high-voltage capacitor. Of course, this is not limited thereto, and two or more interlayer dielectric layers may be formed. The second interlayer dielectric layer 112 may be made of the same material and manufactured by the same method as the bottom interlayer dielectric layer 110 and the first interlayer dielectric layer 111. Figures 2 to 9 There is no distinction between these interlayer dielectric layers.
[0069] In one embodiment, a third interlayer dielectric layer 113 and a fourth interlayer dielectric layer 114 may be formed on the second interlayer dielectric layer 112, wherein the material of the third interlayer dielectric layer 113 may include a silicon oxynitride layer, and the material of the fourth interlayer dielectric layer 114 may include a silicon nitride layer, so as to improve the withstand voltage capability of the high-voltage capacitor.
[0070] In this embodiment, the material of the first plate 210 of the high-voltage capacitor is the same as the material of the metal layer 101, and the material of the dielectric layer of the high-voltage capacitor is determined by the material of the interlayer dielectric layer of each layer. Exemplarily, the material of the first plate 210 of the high-voltage capacitor includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt, and the material of the dielectric layer of the high-voltage capacitor can be ethyl silicate, borophosphosilicate glass, or other suitable dielectric materials, such as low-k dielectric materials or any combination of these materials.
[0071] In one embodiment of the present invention, a metal interconnect structure can be formed when forming the first plate 210 of the high-voltage capacitor and at least one interlayer dielectric layer. Exemplarily, the substrate 100 may include a first region and a second region, the high-voltage capacitor and the subsequently formed silicon capacitor are located in the first region, and a semiconductor structure may be formed in the second region, the semiconductor structure is, for example, an active device, such as a metal oxide semiconductor transistor device. The metal interconnect structure includes multiple interlayer dielectric layers, and a metal layer and a conductive via are formed in each interlayer dielectric layer, and the metal layer and the conductive via lead out the corresponding electrodes of the semiconductor structure (for example, the gate, source and drain of the metal oxide semiconductor transistor are led out respectively). When the metal interconnect structure is formed in the second region, the first plate 210 of the high-voltage capacitor and each interlayer dielectric layer can be formed in the first region, thereby saving process steps and reducing manufacturing costs. Of course, the first plate 210 of the high-voltage capacitor and at least one interlayer dielectric layer can also be formed separately, and the present invention is not limited to this.
[0072] In step S3, please refer to Figure 3 As shown, the interlayer dielectric layer is etched to form a deep trench 121 .
[0073] In one embodiment of the present invention, a photoresist layer is formed on the top interlayer dielectric layer (i.e., the fourth interlayer dielectric layer 114) (in order to distinguish it from the subsequent photoresist layers, it is referred to as the first photoresist layer in this embodiment), the first photoresist layer is exposed and developed to form a patterned first photoresist layer 120, all the interlayer dielectric layers are etched using the patterned first photoresist layer 120 as a mask to form deep grooves 121, and then the patterned first photoresist layer 120 is removed. In one embodiment, all the interlayer dielectric layers are etched until the metal layer 101 is exposed, that is, the fourth interlayer dielectric layer 114, the third interlayer dielectric layer 113, the second interlayer dielectric layer 112 and the first interlayer dielectric layer 111 (i.e., all the interlayer dielectric layers located on the metal layer 101) are etched to form deep grooves 121 that expose the metal layer 101.
[0074] In step S4, please refer to Figures 4 to 6As shown, a first electrode plate 310 of a silicon capacitor is formed on the sidewall and bottom of the deep groove 121, the first electrode plate 310 of the silicon capacitor is connected to the first electrode plate 210 of the high-voltage capacitor, and the first electrode plate 310 of the silicon capacitor extends from the sidewall of the deep groove 121 to the top interlayer dielectric layer as an extraction electrode 312 of the first electrode plate 310 of the silicon capacitor; a dielectric layer 320 of a silicon capacitor is formed on the sidewall and bottom of the deep groove 121, the dielectric layer 320 of the silicon capacitor covers the first electrode plate 310 of the silicon capacitor; a second electrode plate 330 of a silicon capacitor is formed in the deep groove 121, and the second electrode plate 330 of the silicon capacitor fills the deep groove 121.
[0075] In this embodiment, please refer to Figure 4 As shown, first, a first conductive material layer 311 is formed, and the first conductive material layer 311 covers the side wall and the bottom of the deep groove 121, and covers the top surface of the fourth interlayer dielectric layer 114 (that is, the top surface of the top interlayer dielectric layer); then, an insulating material layer 321 is formed, and the insulating material layer 321 covers the side wall and the bottom of the deep groove 121, and covers the top surface of the fourth interlayer dielectric layer 114, that is, the insulating material layer 321 covers the first conductive material layer 311; then, a second conductive material layer 331 is formed, and the second conductive material layer 331 fills the deep groove 121 and covers the fourth interlayer dielectric layer 114 (specifically covers the insulating material layer 321 on the fourth interlayer dielectric layer 114).
[0076] Then please refer to Figure 4 and Figure 5 As shown, planarization, such as chemical mechanical polishing, is performed until the first conductive material layer 311 is exposed, the insulating material layer 321 on the surface of the fourth interlayer dielectric layer 114 is removed, and only the insulating material layer 321 on the sidewall and bottom of the deep groove 121 is retained as the dielectric layer 320 of the silicon capacitor. At the same time, the second conductive material layer 331 on the surface of the fourth interlayer dielectric layer 114 is also removed, and only the second conductive material layer 331 in the deep groove 121 is retained as the second electrode 330 of the silicon capacitor.
[0077] Then, please refer to Figure 6As shown, a second photoresist layer is formed, the second photoresist layer is exposed and developed to form a patterned second photoresist layer 130, and then the first conductive material layer 311 is etched with the patterned second photoresist layer 130 until a portion of the fourth interlayer dielectric layer 114 is exposed (i.e., a portion of the top interlayer dielectric layer is exposed), a first electrode 310 of a silicon capacitor is formed on the sidewall and bottom of the deep groove 121, and an extraction electrode 312 connected to the first electrode 310 of the silicon capacitor is formed on the fourth interlayer dielectric layer 114. In this embodiment, the first electrode 310 of the silicon capacitor is connected to the first electrode 210 of the high-voltage capacitor through the metal layer 101, so the extraction electrode 312 serves as a common extraction electrode of the first electrode 310 of the silicon capacitor and the first electrode 210 of the high-voltage capacitor. Afterwards, the patterned second photoresist layer 130 is removed.
[0078] In this embodiment, the first electrode 310 of the silicon capacitor extends from the side wall of the deep groove 121 to the top interlayer dielectric layer as the lead-out electrode 312 of the first electrode 310 of the silicon capacitor, and the first electrode 310 of the silicon capacitor and the first electrode 210 of the high-voltage capacitor can be led out at the same time, saving the metal layer and the conductive through hole steps required for leading out the first electrode of the high-voltage capacitor separately, saving the manufacturing process, and reducing the manufacturing cost.
[0079] In this embodiment, the etching amount needs to be controlled when etching the first conductive material layer 311. Excess etching will cause the thickness of the fourth interlayer dielectric layer 114 (i.e., the thickness of the dielectric layer of the high-voltage capacitor) to change, thereby affecting the withstand voltage performance of the high-voltage capacitor.
[0080] In one embodiment of the present invention, the material of the first conductive material layer 311 includes but is not limited to titanium nitride, the material of the second conductive material layer 331 includes but is not limited to tungsten, and the insulating material layer 321 includes a silicon nitride layer or a stack composed of silicon oxide-silicon nitride-silicon oxide, that is, the material of the insulating material layer 321 includes but is not limited to silicon oxide-silicon nitride-silicon oxide (ONO) or silicon nitride, that is, in the silicon capacitor, the material of the first plate 310 of the silicon capacitor includes but is not limited to titanium nitride, the material of the second plate 330 of the silicon capacitor includes but is not limited to tungsten, and the material of the dielectric layer 320 of the silicon capacitor includes but is not limited to ONO or silicon nitride. Of course, the materials of each layer in the silicon capacitor are not limited thereto, and can also be any other suitable materials known to those skilled in the art. The first conductive material layer 311, the insulating material layer 321 and the second conductive material layer 331 can be formed by deposition processes such as atomic layer deposition process, chemical vapor deposition process, and physical vapor deposition process.
[0081] In the embodiment of the present invention, the first plate 310 and the second plate 330 of the silicon capacitor are both made of conductive materials, and ion implantation is not required, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove 121, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves 121 can be accommodated in the interlayer dielectric layer, further increasing the integration.
[0082] In addition, the dielectric layer 320 of the silicon capacitor uses ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown of weak positions caused by dielectric defects and dielectric uniformity during operation.
[0083] In step S5, please refer to Figure 8 As shown, a second electrode plate 220 of the high voltage capacitor is formed on the top interlayer dielectric layer.
[0084] For example, first, please refer to Figure 7 As shown, a conductive material layer is formed (in order to distinguish it from the first conductive material layer 311 and the second conductive material layer 331, it is referred to as the third conductive material layer 221 in this embodiment), and the third conductive material layer 221 covers the top interlayer dielectric layer, specifically covers the fourth interlayer dielectric layer 114, and of course also covers the lead-out electrode 312 at the same time.
[0085] Then, please refer to Figure 8 As shown, the third conductive material layer 221 is etched until the interlayer dielectric layer of the top layer is exposed. Specifically, a third photoresist layer is formed on the third conductive layer 221, and the third photoresist layer is exposed and developed to form a patterned third photoresist layer 140. The patterned third photoresist layer 140 is used as a mask to etch the third conductive material layer 221 until a portion of the interlayer dielectric layer of the top layer is exposed, and a portion of the third conductive material layer 221 is retained. The third conductive material layer located directly above the first electrode 210 of the high-voltage capacitor is retained as the second electrode 220 of the high-voltage capacitor, the third conductive material layer located on the lead-out electrode 312 is retained as the first electrode 210 of the high-voltage capacitor and the first lead-out terminal 212 of the first electrode 310 of the silicon capacitor, and the third conductive material layer located on the second electrode 330 of the silicon capacitor is retained as the second lead-out terminal 332 of the second electrode 330 of the silicon capacitor.
[0086] In one embodiment of the present invention, the material of the third conductive material layer 221 includes but is not limited to copper, tungsten, aluminum, ruthenium or cobalt, and may be any other suitable material.
[0087] In addition, in this embodiment, when etching the third conductive material layer 221 , it is necessary to control the size of the remaining third conductive material layer 221 to prevent the first electrode 310 of the silicon capacitor from being short-circuited with the second electrode 330 of the silicon capacitor.
[0088] Please refer to Fig. 9 As shown, after forming the second electrode plate 220 of the high-voltage capacitor, it also includes: forming a passivation layer, the passivation layer covers the exposed top interlayer dielectric layer and exposes the second electrode plate 220 and the lead-out terminal of the high-voltage capacitor. In one embodiment of the present invention, please refer to Fig. 9 As shown, the passivation layer includes a first passivation layer 151 and a second passivation layer 152. The material of the first passivation layer 151 includes silicon oxynitride, and the material of the second passivation layer 152 includes PI (polyimide). In other embodiments, only one passivation layer may be formed, and the passivation layer may be silicon oxynitride or PI.
[0089] In the method for manufacturing a semiconductor device provided by the present invention, a first electrode plate 210 of a high-voltage capacitor is first formed, and then at least one interlayer dielectric layer is formed on the first electrode plate 210 as a dielectric layer of the high-voltage capacitor, and then all the interlayer dielectric layers are etched to form a deep groove 121, and then a first electrode plate 310 of a silicon capacitor is formed on the sidewall and bottom of the deep groove 121, the first electrode plate 310 of the silicon capacitor is connected to the first electrode plate 210 of the high-voltage capacitor, and the first electrode plate 310 of the silicon capacitor extends from the sidewall of the deep groove 121 to the interlayer dielectric layer on the top layer as an extraction electrode 312 of the first electrode plate 310 of the silicon capacitor; a dielectric layer 320 of the silicon capacitor is formed on the sidewall and bottom of the deep groove 121, and the dielectric layer 320 of the silicon capacitor covers the first electrode plate 310 of the silicon capacitor; a second electrode plate 330 of the silicon capacitor is formed in the deep groove 121, and the second electrode plate 330 of the silicon capacitor fills the deep groove 121, and then the second electrode plate 220 of the high-voltage capacitor is formed on the interlayer dielectric layer on the top layer. The present invention integrates the production of high-voltage capacitors and silicon capacitors into one process, thereby saving process steps, reducing production costs, and improving product competitiveness.
[0090] Correspondingly, the present invention also provides a semiconductor device manufactured by the semiconductor device manufacturing method as described above.
[0091] Please refer to Fig. 9 As shown, the semiconductor device comprises:
[0092] A first electrode plate 210 of a high voltage capacitor;
[0093] At least one interlayer dielectric layer is located on the first electrode plate 210 of the high-voltage capacitor and serves as the dielectric layer of the high-voltage capacitor; a deep groove 121 penetrating the interlayer dielectric layer is formed in the interlayer dielectric layer;
[0094] The first electrode plate 310 of the silicon capacitor is located on the sidewall and bottom of the deep trench 121, the first electrode plate 310 of the silicon capacitor is connected to the first electrode plate 210 of the high-voltage capacitor, and the first electrode plate 310 of the silicon capacitor extends from the sidewall of the deep trench 121 to the top interlayer dielectric layer as an extraction electrode 312 of the first electrode plate 310 of the silicon capacitor;
[0095] The dielectric layer 320 of the silicon capacitor is located on the sidewall and bottom of the deep trench 121 and covers the first electrode plate 310 of the silicon capacitor;
[0096] The second electrode plate 330 of the silicon capacitor is located in the deep trench 121 and fills the deep trench 121; and
[0097] The second electrode plate 220 of the high voltage capacitor is located on the top interlayer dielectric layer.
[0098] In one embodiment of the present invention, the material of the first plate 310 of the silicon capacitor includes but is not limited to titanium nitride, and the material of the second plate 330 of the silicon capacitor includes but is not limited to tungsten. The first plate 310 and the second plate 320 of the silicon capacitor do not need to be ion implanted, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves can be accommodated in the interlayer dielectric layer, further increasing the integration.
[0099] In one embodiment of the present invention, the material of the dielectric layer 320 of the silicon capacitor includes ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown of weak positions caused by dielectric defects and dielectric uniformity during operation.
[0100] In summary, in the semiconductor device and its manufacturing method provided by the present invention, firstly, a first plate of a high-voltage capacitor is formed, then at least one interlayer dielectric layer is formed on the first plate as the dielectric layer of the high-voltage capacitor, then the interlayer dielectric layer is etched to form a deep groove, then a first conductive layer is formed on the sidewall and bottom of the deep groove as the first plate of the silicon capacitor, the first plate of the silicon capacitor is connected to the first plate of the high-voltage capacitor, and the first plate of the silicon capacitor extends from the sidewall of the deep groove to the interlayer dielectric layer on the top layer as the lead-out electrode of the first plate of the silicon capacitor, an insulating layer is formed on the sidewall and bottom of the deep groove, the insulating layer covers the first conductive layer as the dielectric layer of the silicon capacitor, a second conductive layer is formed in the deep groove, the second conductive layer fills the deep groove as the second plate of the silicon capacitor, and then a third conductive layer is formed on the interlayer dielectric layer on the top layer as the second plate of the high-voltage capacitor. The present invention integrates the production of high-voltage capacitors and silicon capacitors in one process, saves process steps, reduces production costs, and improves product competitiveness.
[0101] At the same time, the first electrode of the silicon capacitor extends from the side wall of the deep groove to the top interlayer dielectric layer as the lead-out electrode of the first electrode of the silicon capacitor, and the first electrode of the silicon capacitor and the first electrode of the high-voltage capacitor can be led out at the same time, saving the metal layer and the conductive through hole required for leading out the first electrode of the high-voltage capacitor separately, saving the manufacturing process and reducing the manufacturing cost.
[0102] Furthermore, the first plate and the second plate of the silicon capacitor are both made of conductive materials, and ion implantation is not required, thus getting rid of the limitation of the ion implantation process. The deposition process can evenly deposit the conductive material on the inner wall of the entire deep groove, thereby improving the uniformity of the first plate and reducing the parasitic resistance. At the same time, since there is no need to perform the ion implantation process, more deep grooves can be accommodated in the interlayer dielectric layer, further increasing the integration.
[0103] In addition, the dielectric layer of the silicon capacitor uses ONO or silicon nitride, which can significantly increase the breakdown voltage of the silicon capacitor and avoid breakdown in weak locations caused by dielectric defects and dielectric uniformity during operation.
[0104] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: forming a first plate of a high voltage capacitor; Forming at least one interlayer dielectric layer on the first electrode plate of the high-voltage capacitor as a dielectric layer of the high-voltage capacitor; Etching the interlayer dielectric layer to form a deep groove; A first electrode plate of a silicon capacitor is formed on the sidewall and bottom of the deep trench, the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor, and the first electrode plate of the silicon capacitor extends from the sidewall of the deep trench to the top interlayer dielectric layer as an extraction electrode of the first electrode plate of the silicon capacitor; forming a dielectric layer of a silicon capacitor on the sidewall and the bottom of the deep trench, wherein the dielectric layer of the silicon capacitor covers the first electrode plate of the silicon capacitor; forming a second electrode plate of the silicon capacitor in the deep trench, wherein the second electrode plate of the silicon capacitor fills the deep trench; as well as A second electrode plate of the high voltage capacitor is formed on the top interlayer dielectric layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming a first plate of a high voltage capacitor include: Providing a substrate, and forming a bottom interlayer dielectric layer on the substrate; forming a metal layer, wherein the metal layer covers a portion of the bottom interlayer dielectric layer; forming a first interlayer dielectric layer, the first interlayer dielectric layer covering the metal layer and the bottom interlayer dielectric layer; forming a conductive through hole in the first interlayer dielectric layer connected to the metal layer; A first electrode plate of the high-voltage capacitor is formed, wherein the first electrode plate of the high-voltage capacitor covers a portion of the first interlayer dielectric layer, and the first electrode plate of the high-voltage capacitor is connected to the first metal layer through the conductive through hole.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: In a direction perpendicular to the substrate, the first electrode plate of the high-voltage capacitor covers a portion of the metal layer.
4. The method for manufacturing a semiconductor device according to claim 2, wherein: All the interlayer dielectric layers are etched to form deep grooves exposing the metal layer, and the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor through the metal layer.
5. The method for manufacturing a semiconductor device according to claim 2, wherein: The method of forming at least one interlayer dielectric layer on the first electrode plate of the high-voltage capacitor as the dielectric layer of the high-voltage capacitor comprises: forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first electrode plate of the high-voltage capacitor and the first interlayer dielectric layer; A third interlayer dielectric layer and a fourth interlayer dielectric layer are sequentially formed on the second interlayer dielectric layer.
6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The bottom interlayer dielectric layer, the first interlayer dielectric layer and the second interlayer dielectric layer are made of the same material, which includes ethyl silicate, borophosphosilicate glass or a low dielectric constant material; the third interlayer dielectric layer includes silicon oxynitride, and the fourth interlayer dielectric layer includes silicon nitride.
7. The method for manufacturing a semiconductor device according to claim 2, wherein: The method of etching the interlayer dielectric layer to form a deep trench comprises: forming a photoresist layer on the top interlayer dielectric layer; Exposing and developing the photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching all interlayer dielectric layers until the metal layer is exposed; and The patterned photoresist layer is removed.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The second electrode plate of the high-voltage capacitor is formed while forming the lead-out end of the first electrode plate of the high-voltage capacitor, the lead-out end of the first electrode plate of the silicon capacitor, and the lead-out end of the second electrode plate of the silicon capacitor; The method of forming a second plate of a high voltage capacitor on a top interlayer dielectric layer comprises: forming a conductive material layer, wherein the conductive material layer covers the top interlayer dielectric layer; The conductive material layer is etched to expose a portion of the top interlayer dielectric layer, and the conductive material layer directly above the first electrode plate of the high-voltage capacitor is retained as the second electrode plate of the high-voltage capacitor, the conductive material layer on the lead-out electrode is retained as the first electrode plate of the high-voltage capacitor and the first lead-out end of the first electrode plate of the silicon capacitor, and the conductive material layer on the second electrode plate of the silicon capacitor is retained as the second lead-out end of the second electrode plate of the silicon capacitor.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The materials of the first plate and the second plate of the high-voltage capacitor include copper, tungsten, aluminum, ruthenium or cobalt; the material of the first plate of the silicon capacitor includes titanium nitride, the material of the second plate of the silicon capacitor includes tungsten, and the dielectric layer of the silicon capacitor includes a silicon nitride layer or a stack composed of silicon oxide-silicon nitride-silicon oxide.
10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device comprises: A first plate of a high voltage capacitor; At least one interlayer dielectric layer is located on the first electrode plate of the high-voltage capacitor and serves as the dielectric layer of the high-voltage capacitor; a deep groove penetrating the interlayer dielectric layer is formed in the interlayer dielectric layer; A first electrode plate of the silicon capacitor is located on the sidewall and bottom of the deep trench, the first electrode plate of the silicon capacitor is connected to the first electrode plate of the high-voltage capacitor, and the first electrode plate of the silicon capacitor extends from the sidewall of the deep trench to the top interlayer dielectric layer as an extraction electrode of the first electrode plate of the silicon capacitor; A dielectric layer of the silicon capacitor, located on the sidewall and bottom of the deep trench and covering the first electrode plate of the silicon capacitor; a second electrode plate of the silicon capacitor, located in the deep trench and filling the deep trench; and The second plate of the high voltage capacitor is located on the top interlayer dielectric layer.