Semiconductor device and manufacturing method thereof
By performing pre-amorphic injection on the substrate of the semiconductor device to form an amorphous layer and removing some side walls, the problems of complex and high cost in the prior art are solved, and the effect of improving the interface resistance of the metal silicide and improving mobility is achieved, while simplifying the process steps and reducing costs.
Patent Information
- Application Number
- CN202311342812.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-17
- Publication Date
- 2025-04-25
AI Technical Summary
The prior art In the process of improving the interface resistance of metal silicides and increasing the mobility of MOS devices, the process steps are complex and costly, which are difficult to simplify.
By performing pre-amorphic injection on the substrate of the semiconductor device, an amorphous layer is formed and part of the side walls are removed, thereby exposing more gate area when the metal silicide is subsequently formed, simplifying process steps and reducing costs.
While ensuring improved roughness and uniformity of metal silicides and reducing interface resistance, it also improves device mobility, simplifies process steps and reduces process costs.
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Figure CN119894016A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] In the existing MOS transistor process, in order to improve the interface resistance of the gate, source region and drain region of the transistor, metal silicide is usually formed on the surface of the gate, source region and drain region. At present, most of the metal silicides are formed by self-aligned metal silicide process. Specifically, after the source region and the drain region are formed, a metal layer composed of cobalt, titanium or nickel is formed on the source region, the drain region and the gate, and then through one or more steps of rapid annealing (RTA), the metal layer reacts with the silicon in the gate, source region and drain region to form a metal silicide with low resistivity.
[0003] As device size develops towards a smaller direction, the requirements for the interface resistance of metal silicide are getting higher and higher. There are many factors that affect the interface resistance performance of metal silicide. Taking nickel silicide as an example, the thickness of the film, the temperature of RTA, the roughness and uniformity of the film will all affect the interface resistance. In order to further reduce the interface resistance of metal silicide, pre-amorphization implantation (PAI) is usually used before the self-aligned silicide process, that is, silicon, carbon, germanium or antimony plasma is applied with appropriate energy and dose, and implanted into the semiconductor substrate to destroy the lattice structure of the semiconductor substrate, thereby forming an amorphous region, thereby effectively improving the roughness and uniformity of the metal silicide film.
[0004] On the other hand, mobility is an important indicator of MOS device performance. In order to improve mobility, the industry has introduced stress memory technology. In the prior art, stress memory technology includes depositing a stress layer on the semiconductor device, followed by a high-temperature annealing process to memorize the stress on the semiconductor device, and then removing the stress layer. Stress is used to change the lattice structure of the semiconductor substrate, thereby improving the mobility of electrons and improving the overall performance of the device.
[0005] In order to better generate stress effect, stress proximity technology (SPT) was introduced, that is, by reducing the thickness of the gate sidewalls on both sides of the gate and then depositing the stress layer, the distance between the stress layer and the gate is reduced, thereby increasing the stress effect of the stress layer on the gate and further improving the performance of the semiconductor device.
[0006] In the prior art, in order to improve the roughness and uniformity of the metal silicide film and improve the mobility of the device, it is necessary to add steps such as pre-amorphization injection, removal of part of the gate sidewalls on both sides of the gate, deposition of the stress layer, high temperature annealing process and removal of the stress layer, which increases the process cost. Therefore, on the basis of ensuring the above beneficial effects, how to simplify the process and reduce the process cost is a technical problem that those skilled in the art need to solve urgently. Summary of the invention
[0007] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which simplifies the process steps and reduces the process cost while ensuring that the roughness and uniformity of the metal silicide film are improved and the mobility of the device is improved.
[0008] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps:
[0009] Providing a substrate, wherein a gate is formed on the substrate, sidewalls are formed on the sidewalls of the gate, and source regions and drain regions are formed in the substrate on both sides of the gate;
[0010] Performing a pre-amorphization implantation on the substrate to form an amorphous layer on the upper surfaces of the gate, the source region and the drain region, and removing a portion of the sidewalls by the pre-amorphization implantation;
[0011] forming a metal silicide on the gate, the source region, and the drain region; and
[0012] A stress layer is formed, wherein the stress layer covers the metal silicide, the sidewalls and the substrate.
[0013] Optionally, the ion energy implanted in the pre-amorphization implantation is 2 KeV to 16 KeV.
[0014] Optionally, the ion dose implanted in the pre-amorphization implantation is 1E13atom / cm 2 ~1E16atom / cm 2 .
[0015] Optionally, the ions implanted in the pre-amorphization implantation include one or more of silicon, nitrogen, fluorine, xenon, neon, argon, krypton, carbon, germanium or antimony ions.
[0016] Optionally, the pre-amorphization implantation implants ions at an inclined angle.
[0017] Optionally, the angle between the direction of ion implantation in the pre-amorphization implantation and the direction perpendicular to the substrate is 15° to 45°.
[0018] In order to solve the above technical problem, according to a second aspect of the present invention, a semiconductor device is provided, comprising:
[0019] substrate;
[0020] A gate located on the substrate, a sidewall located on the sidewall of the gate, and a source region and a drain region located in the substrate on both sides of the gate;
[0021] A metal silicide located on the source region and the drain region;
[0022] The projection of the sidewall on the substrate is in contact with the projection of the metal silicide on the substrate.
[0023] Optionally, the metal silicide contains doping elements, and the doping elements are ions implanted in the pre-amorphization implantation.
[0024] Optionally, the doping element includes one or more of silicon, nitrogen, fluorine, xenon, neon, argon, krypton, carbon, germanium or antimony.
[0025] Optionally, the metal silicide further includes the metal silicide on the gate; and the top surface height of the sidewall spacer is lower than the top surface height of the metal silicide on the gate.
[0026] To summarize, in the semiconductor device and the manufacturing method thereof provided by the present invention, a substrate is first provided, a gate is formed on the substrate, a sidewall is formed on the sidewall of the gate, and a source region and a drain region are formed in the substrate on both sides of the gate; then, the substrate is pre-amorphized and implanted to form an amorphous layer on the upper surface of the gate, the source region and the drain region, and at the same time, a portion of the sidewall is removed by the pre-amorphization implantation; then, a metal silicide is formed on the gate, the source region and the drain region; and a stress layer is formed, the stress layer covering the metal silicide, the sidewall and the substrate. In the present invention, by performing pre-amorphization injection, not only an amorphous layer is formed, but also part of the side wall is removed, exposing a larger area of the gate. When metal is subsequently deposited to form metal silicide, a larger area of the gate can be covered by metal, thereby forming a thicker metal silicide; and after the metal silicide is formed, it is not necessary to etch the side wall before forming the stress layer, thereby simplifying the process steps and reducing the process cost while ensuring that the roughness and uniformity of the metal silicide are improved, the interface resistance of the metal silicide is reduced, and the mobility of the device is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0028] Figure 1 It is a flow chart of a method for manufacturing a semiconductor device provided by one embodiment of the present invention.
[0029] Figures 2 to 5 It is a schematic structural diagram of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.
[0030] Figure 6 It is a schematic diagram of a slice of a semiconductor device formed by performing pre-amorphization implantation without removing the sidewalls.
[0031] Figure 7 It is a schematic diagram of a slice of a semiconductor device formed by removing part of the sidewall through pre-amorphization implantation.
[0032] Description of reference numerals:
[0033] 10 - substrate; 11 - gate; 12 - gate dielectric layer; 13 - sidewall; 13a - oxide layer; 13b - nitride layer; 14 - source region; 15 - drain region; 16 - amorphous layer; 17 - metal silicide; 18 - stress layer. DETAILED DESCRIPTION
[0034] In view of the above problems, the inventors have found through research that in the process of forming metal silicide, by increasing the energy and dosage of the ions injected in the pre-amorphization injection, the sidewalls can be etched. Similarly, by changing the ion injection in the pre-amorphization injection to an inclined angle injection, the sidewalls can also be etched. That is, in the pre-amorphization injection process, not only can an amorphous layer be formed, but also the sidewalls can be removed.
[0035] After further research, the inventors provided a semiconductor device and a method for manufacturing the same. By performing pre-amorphization injection, not only an amorphous layer is formed, but also part of the side wall is removed, exposing a larger area of the gate. When metal is subsequently deposited to form metal silicide, a larger area of the gate can be covered by metal, thereby forming a thicker metal silicide; and after the metal silicide is formed, there is no need to etch the side wall before forming the stress layer, thereby simplifying the process steps and reducing the process cost while ensuring that the roughness and uniformity of the metal silicide are improved, the interface resistance of the metal silicide is reduced, and the mobility of the device is improved.
[0036] The manufacturing method of the semiconductor device includes: providing a substrate, a gate is formed on the substrate, a sidewall is formed on the sidewall of the gate, and a source region and a drain region are formed in the substrate on both sides of the gate; performing pre-amorphization injection on the substrate to form an amorphous layer in the upper surfaces of the gate, the source region and the drain region, and removing part of the sidewall by the pre-amorphization injection; forming a metal silicide on the gate, the source region and the drain region; and forming a stress layer, the stress layer covering the metal silicide, the sidewall and the substrate.
[0037] The semiconductor device is manufactured by using the semiconductor device manufacturing method described above.
[0038] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0039] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.
[0040] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for manufacturing a semiconductor device provided in this embodiment includes the following steps:
[0041] Step S1: providing a substrate, wherein a gate is formed on the substrate, sidewalls are formed on the sidewalls of the gate, and source regions and drain regions are formed in the substrate on both sides of the gate;
[0042] Step S2: performing pre-amorphization implantation on the substrate to form an amorphous layer on the upper surfaces of the gate, the source region and the drain region, and removing part of the sidewall spacer by the pre-amorphization implantation;
[0043] Step S3: forming metal silicide on the gate, the source region and the drain region;
[0044] Step S4: forming a stress layer, wherein the stress layer covers the metal silicide, the sidewall spacer and the substrate.
[0045] Figures 2 to 5 FIG. 1 is a schematic diagram of the structure of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 and Figures 2 to 5 The method for manufacturing a semiconductor device provided by an embodiment of the present invention is described in detail.
[0046] In step S1, refer to Figure 2 As shown, a substrate 10 is provided, a gate 11 is formed on the substrate 10 , a sidewall 13 is formed on the sidewall of the gate 11 , and a source region 14 and a drain region 15 are formed in the substrate 10 on both sides of the gate 11 .
[0047] The material of the substrate 10 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, etc., or may be silicon on insulator, germanium on insulator; or may be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 10 is silicon.
[0048] A gate 11 is formed on the substrate 10. The material of the gate 11 may be polysilicon and may be formed by chemical vapor deposition. A gate dielectric layer 12 may be formed between the gate 11 and the substrate 10. The gate dielectric layer 12 may be made of common dielectric materials, such as one or a combination of oxides, nitrides, and oxynitrides. The gate dielectric layer 12 may be formed by thermal oxidation or chemical vapor deposition. Exemplarily, a gate dielectric material layer and a gate material layer are sequentially formed on the substrate 10, and then the gate material layer and the gate dielectric material layer are etched until the substrate 10 is exposed, so as to form the gate 11 and the gate dielectric layer 12 located below the gate 11.
[0049] A sidewall 13 is formed on the sidewall of the gate 11. In this embodiment, the sidewall 13 may include an oxide layer 13a and a nitride layer 13b located outside the oxide layer 13a, the oxide layer 13a is made of silicon oxide, and the nitride layer 13b is made of silicon nitride. The oxide layer 13a and the nitride layer 13b may be formed by chemical vapor deposition. Exemplarily, an oxide material layer and a nitride material layer are sequentially formed on the substrate 10, the oxide material layer covers the top and sidewalls of the gate 11, the sidewalls of the gate dielectric layer 12 and the upper surface of the substrate 10, the nitride material layer covers the oxide material layer, and then the nitride material layer and the oxide material layer are sequentially etched to form the nitride layer 13b and the oxide layer 13a.
[0050] A source region 14 and a drain region 15 are formed in the substrate 10 on both sides of the gate 11. Exemplarily, source and drain implantation of dopant ions is performed in the substrate 10 on both sides of the gate 11 to form the source region 14 and the drain region 15, and source and drain implantation of N-type dopant ions is performed for NMOS devices, and source and drain implantation of P-type dopant ions is performed for PMOS devices.
[0051] The substrate 10 also has various isolation elements and various doping regions formed therein to form necessary structures of the semiconductor device. The isolation element is, for example, a shallow trench isolation structure, and the doping region is, for example, an N-well or a P-well. The above structures can be determined according to the actual semiconductor device manufacturing process, and the present invention does not limit this.
[0052] In step S2, please refer to Figure 3 As shown, the substrate 10 is pre-amorphized and implanted to form an amorphous layer 16 on the upper surfaces of the gate 11 , the source region 14 and the drain region 15 , and a portion of the sidewall spacer 13 is removed by the pre-amorphization implantation.
[0053] The ions implanted in the pre-amorphization implantation include one or more of silicon, nitrogen, fluorine, xenon, neon, argon, krypton, carbon, germanium or antimony ions.
[0054] The substrate 10 is pre-amorphized by implantation, and an amorphous layer 16 is formed on the upper surfaces of the gate 11, the source region 14, and the drain region 15. The amorphous layer 16 can effectively inhibit the lateral growth of the metal silicide formed subsequently, control the ratio of the lateral growth and the vertical growth of the metal silicide, thereby improving the roughness and uniformity of the metal silicide and reducing the interface resistance of the metal silicide.
[0055] In this embodiment, the pre-amorphization implantation can remove part of the sidewall 13 while forming the amorphous layer 16, thereby reducing the distance between the stress layer formed subsequently and the active area, thereby increasing the stress effect of the stress layer on the channel. When the stress layer is subsequently formed, it is not necessary to etch the sidewall 13, thereby simplifying the process steps. In addition, removing part of the sidewall 13 can expose more area of the gate 11, so that when metal is subsequently deposited to form metal silicide, more area of the gate 11 can be covered by metal, thereby forming a thicker metal silicide.
[0056] In the first embodiment of the present invention, the ion energy injected in the pre-amorphization injection can be increased to enable the pre-amorphization injection to achieve the purpose of removing part of the sidewall 13. Exemplarily, the ion energy injected in the pre-amorphization injection is 2Kev to 16Kev, for example, the ion energy injected in the pre-amorphization injection is 8Kev. Of course, it is not limited to this, and the ion energy can also be higher.
[0057] In the second embodiment of the present invention, the ion dose injected in the pre-amorphization injection can be increased to achieve the purpose of removing part of the sidewall 13. For example, the ion dose injected in the pre-amorphization injection is 1E13atom / cm 2 ~1E16 atom / cm 2 For example, the ion dose injected in the pre-amorphization injection is 1E15atom / cm 2 Of course, this is not the only option, and the ion dose can be higher.
[0058] In the third embodiment of the present invention, the pre-amorphization injection can also be changed to change the angle of ion injection in the pre-amorphization injection so as to achieve the purpose of removing part of the sidewall 13, that is, the pre-amorphization injection injects ions at an inclined angle. Exemplarily, the angle between the direction of ion injection in the pre-amorphization injection and the direction perpendicular to the substrate 10 is 15° to 45°, for example, the angle is 30°. Of course, in the pre-amorphization injection, the inclined direction of ion injection can be changed as time goes by, for example, first using Figure 3 Ion implantation is performed in the direction indicated by arrow a, and after a period of time, ion implantation is performed again in the direction indicated by arrow b.
[0059] The above embodiments can be executed separately, or any two or three of them can be selected for execution, and the present invention does not limit this. When the first embodiment and the second embodiment are selected for execution simultaneously, when the energy of the injected ions increases more, the ion dose can be increased less; when the energy of the injected ions increases less, the ion dose can be increased more, and the selection can be made according to the actual situation.
[0060] exist Figure 3 , only a part of the thickness of the amorphous layer 16 is shown in the upper surface of the gate 11, the source region 14 and the drain region 15. In this embodiment, under the condition of increasing the ion energy injected in the pre-amorphization injection or increasing the ion dose injected in the pre-amorphization injection, the amorphous layer 16 may be completely formed in the region where the source region 14 and the drain region 15 are located.
[0061] In step S3, please refer to Figure 4 As shown, a metal silicide 17 is formed on the gate 11 , the source region 14 and the drain region 15 .
[0062] In this embodiment, the method for forming the metal silicide 17 may include the following steps.
[0063] First, a metal layer (not shown) is formed on the substrate 10, and the metal layer at least covers the gate 11, the source region 14 and the drain region 15. The material of the metal layer may include nickel, platinum, cobalt, titanium or their alloys. In addition, different metals consume different amounts of silicon in the formation of silicide. Taking cobalt and nickel as examples, cobalt consumes a large amount of silicon, while nickel consumes 20% less silicon than cobalt. Therefore, the thickness of the deposited metal layer can be determined based on the silicon available for consumption by the gate 11, the source region 14 and the drain region 15 and the resistance of the metal silicide to be formed. The method for forming the metal layer may adopt a common method in the art, such as physical vapor deposition or evaporation.
[0064] Then, the substrate 10 formed with the metal layer is annealed, so that the metal in the metal layer diffuses with the silicon in the gate 11, the source region 14, and the drain region 15, and reacts with the silicon in the gate 11, the source region 14, and the drain region 15 to form a metal silicide. In this process, the silicon oxide or silicon nitride on the surface of the substrate 10 does not react with the metal layer, so that the remaining unreacted metal layer can be removed by selective etching later.
[0065] Next, the remaining unreacted metal layer is removed. Exemplarily, the metal on the surface of the substrate 10 that has not reacted with silicon is removed by selective wet etching. Then, the substrate 10 may be annealed again to convert the high-resistivity metal silicide formed in the previous annealing into a low-resistivity metal silicide.
[0066] In step S4, please refer to Figure 5 As shown, a stress layer 18 is formed, and the stress layer 18 covers the metal silicide 17 , the spacer 13 and the substrate 10 .
[0067] In this embodiment, the material of the stress layer 18 includes nitride, such as silicon nitride. The stress layer 18 can be formed by plasma chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD) or high density plasma deposition (HDP).
[0068] After forming the stress layer 18, the method for manufacturing the semiconductor device may further include other process steps, such as performing a high temperature annealing process. In this step, the stress layer 18 exerts stress on the substrate 10 and the gate 11 to improve the performance of the semiconductor device. The stress layer 18 may then be removed.
[0069] Figure 6 FIG. 1 is a schematic diagram of a semiconductor device slice formed by pre-amorphization implantation without removing the sidewalls. Figure 6 As shown, low ion energy and low ion dose are used for pre-amorphization implantation, and the sidewalls are not etched in the subsequent process. The height of the sidewalls 13 is not much different from the height of the metal silicide 17 on the gate 11, and the thickness of the sidewalls 13 is not significantly improved; wherein the sidewalls 13a still cover most of the gate. Figure 7 This is a schematic diagram of a semiconductor device slice formed by removing part of the sidewall through pre-amorphization implantation. Figure 7 As shown, by increasing the ion energy and ion dose injected in the pre-amorphization injection, a portion of the side wall 13 is removed by the pre-amorphization injection while forming an amorphous layer, and there is no need to etch the side wall 13 in subsequent processes. The height of the side wall 13 is much lower than the height of the metal silicide 17 on the gate 11, and the thickness of the side wall 13 is also reduced; wherein the side wall 13a exposes more parts of the gate. Figure 7 The side wall 13 is thinned, one of the effects of which is that the Figure 6 More gate area is exposed in the process, so that when metal is subsequently deposited to form metal silicide, more gate area can be covered by metal, thereby forming a thicker metal silicide; for example Figure 7 The metal silicide ratio at the gate Figure 6 The thickness of the metal silicide in the Figure 6 and Figure 7 It can be seen that by adopting the method for manufacturing a semiconductor device of the present invention, not only an amorphous layer is formed by performing pre-amorphization implantation, but also a part of the sidewall 13 can be removed, so there is no need to etch the sidewall 13 subsequently.
[0070] In the present invention, before forming the metal silicide 17, the substrate 10 is pre-amorphized and implanted to form an amorphous layer 16 on the gate 11, the source region 14 and the drain region 15, thereby improving the roughness and uniformity of the metal silicide 17 formed subsequently and reducing the interface resistance of the metal silicide 17. Before forming the metal silicide 17, a portion of the sidewall 13 is removed to expose a larger area of the gate 11. When metal is subsequently deposited to form the metal silicide 17, a larger area of the gate 11 can be covered by metal, thereby forming a thicker metal silicide 17. After forming the metal silicide 17, the stress layer 18 is formed on the substrate 10, so that stress memory is formed on the semiconductor device, thereby improving the mobility of electrons and improving the overall performance of the device. When the pre-amorphization injection is performed, not only the amorphous layer 16 is formed, but also part of the side wall 13 is removed, thereby reducing the distance between the stress layer 18 and the gate 11. Therefore, before forming the stress layer 18, there is no need to etch and remove part of the side wall 13. This simplifies the process steps and reduces the process cost while ensuring that the roughness and uniformity of the metal silicide are improved, the interface resistance of the metal silicide is reduced, and the mobility of the device is improved.
[0071] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above. Figure 5 As shown, the semiconductor device comprises:
[0072] Substrate 10;
[0073] A gate 11 located on the substrate 10, a sidewall 13 located on the sidewall of the gate 11, and a source region 14 and a drain region 15 located in the substrate 10 on both sides of the gate 11;
[0074] A metal silicide located on the source region 14 and the drain region 15;
[0075] The projection of the sidewall 13 on the substrate 10 is in contact with the projection of the metal silicide on the substrate 10 .
[0076] In this embodiment, the metal silicide also includes the metal silicide on the gate 11 .
[0077] Please refer to Figures 2 to 5As shown, in this embodiment, part of the side wall 13 is removed during the process of forming the amorphous layer 16, so that the projection of the side wall 13 away from the gate 11 on the substrate 10 is in contact with the amorphous layer 16 formed in the source region 14 and the drain region 15, and the projection of the other side of the side wall 13 on the substrate 10 is also in contact with the projection of the amorphous layer 16 formed in the gate 11 on the substrate 10, so that the projection of the metal silicide 17 on the source region 14 and the drain region 15 formed in the end on the substrate 10 is in contact with the projection of the side wall 13 on the substrate 10.
[0078] In this embodiment, since part of the side wall 13 is removed during the process of forming the amorphous layer 16, the top surface height of the side wall 13 is lower than the top surface height of the metal silicide 17 on the gate 11, that is, the height of the side wall 13 is lower than the total height of the gate 11 and the metal silicide 17.
[0079] Furthermore, the metal silicide 17 contains doping elements, which are ions implanted in the pre-amorphization implantation. The doping elements include one or more of silicon, nitrogen, fluorine, xenon, neon, argon, krypton, carbon, germanium or antimony.
[0080] Furthermore, a gate dielectric layer 12 is formed between the gate 11 and the substrate 10 , and the sidewall spacer 13 is located on the sidewalls of the gate 11 and the gate dielectric layer 12 .
[0081] The sidewall spacer 13 includes an oxide layer 13 a and a nitride layer 13 b located outside the oxide layer 13 a .
[0082] To summarize, in the semiconductor device and the manufacturing method thereof provided by the present invention, a substrate is first provided, a gate is formed on the substrate, a sidewall is formed on the sidewall of the gate, and a source region and a drain region are formed in the substrate on both sides of the gate; then, the substrate is pre-amorphized and implanted to form an amorphous layer on the upper surface of the gate, the source region and the drain region, and at the same time, a portion of the sidewall is removed by the pre-amorphization implantation; then, a metal silicide is formed on the gate, the source region and the drain region; and a stress layer is formed, the stress layer covering the metal silicide, the sidewall and the substrate. In the present invention, by performing pre-amorphization injection, not only an amorphous layer is formed, but also part of the side wall is removed, exposing a larger area of the gate. When metal is subsequently deposited to form metal silicide, a larger area of the gate can be covered by metal, thereby forming a thicker metal silicide; and after the metal silicide is formed, it is not necessary to etch the side wall before forming the stress layer, thereby simplifying the process steps and reducing the process cost while ensuring that the roughness and uniformity of the metal silicide are improved, the interface resistance of the metal silicide is reduced, and the mobility of the device is improved.
[0083] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein a gate is formed on the substrate, sidewalls are formed on the sidewalls of the gate, and source regions and drain regions are formed in the substrate on both sides of the gate; Performing a pre-amorphization implantation on the substrate to form an amorphous layer on the upper surfaces of the gate, the source region and the drain region, and removing a portion of the sidewalls by the pre-amorphization implantation; forming a metal silicide on the gate, the source region, and the drain region; as well as A stress layer is formed, wherein the stress layer covers the metal silicide, the sidewalls and the substrate.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The ion energy injected in the pre-amorphization injection is 2Kev to 16Kev.
3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that: The ion dose injected in the pre-amorphization injection is 1E13atom / cm 2 ~1E16 atom / cm 2 .
4. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that: The ions implanted in the pre-amorphization implantation include one or more of silicon, nitrogen, fluorine, xenon, neon, argon, krypton, carbon, germanium or antimony ions.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The pre-amorphization implantation implants ions at an oblique angle.
6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The angle between the ion implantation direction in the pre-amorphization implantation and the direction perpendicular to the substrate is 15° to 45°.
7. A semiconductor device, characterized in that: include: substrate; A gate located on the substrate, a sidewall located on the sidewall of the gate, and a source region and a drain region located in the substrate on both sides of the gate; A metal silicide located on the source region and the drain region; The projection of the sidewall on the substrate is in contact with the projection of the metal silicide on the substrate.
8. The semiconductor device according to claim 7, characterized in that The metal silicide contains doping elements, and the doping elements are ions implanted in the pre-amorphization implantation.
9. The semiconductor device according to claim 8, characterized in that The doping element includes one or more of silicon, nitrogen, fluorine, xenon, neon, argon, krypton, carbon, germanium or antimony.
10. The semiconductor device according to any one of claims 7 to 9, characterized in that: The metal silicide also includes the metal silicide on the gate; the top surface height of the sidewall spacer is lower than the top surface height of the metal silicide on the gate.