Method for improving threshold voltage of Split Gate Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and semiconductor device

Abstract

The invention discloses a method for improving the threshold voltage of a Split Gate Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises the following steps of: S1, carrying out high-density plasma deposition and planarization treatment in a semiconductor substrate, and photoetching a trench gate; s2, performing high-density plasma oxidation to form a gate oxide layer; and S3, after the polycrystalline silicon grid electrode is deposited to # imgabs 0 # and planarized to # imgabs 1 #, back etching is carried out. According to the grid electrode manufacturing method, on the basis of an existing manufacturing method, the original method of depositing to 12k and then planarizing to 6k is adjusted to the method of depositing to 6k and then planarizing to 4k, the shape of a photomask is changed, and the changed deposition method avoids the situation that the uniformity difference between the center and the edge of a wafer is too large due to the fact that planarizing time is too long; the consistency of the performance of the center and the edge of the wafer is improved, the performance of the device can be more uniform, and the product quality is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving a Split Gate Power MOSFET threshold voltage and a semiconductor device. Background Art

[0002] The acceptability test and threshold voltage test values ​​of the wafer center and edge in existing products vary greatly. Research has shown that this is because the gate polysilicon flattening time is too long in the process flow, which increases the difference between the wafer edge and center.

[0003] In order to maximize the uniformity of the wafer edge and center, it is necessary to improve the existing technology, reduce product costs, improve product competitiveness, and make it more in line with usage requirements.

[0004] In view of this, the existing technology should be improved to solve the above-mentioned technical problems existing in the existing technology. Summary of the invention

[0005] In order to solve the existing technical problems, the present invention proposes a method for improving the threshold voltage of Split Gate Power MOSFET and a semiconductor device. On the basis of the existing manufacturing method, the original method of depositing to 12k and then flattening to 6k is adjusted to depositing to 6k and then flattening to 4k, and the shape of the mask is changed, thereby avoiding excessive uniformity differences between the center and edge of the wafer caused by too long flattening time, making the performance of the device more uniform, and thereby improving product quality.

[0006] According to one aspect of the present invention, a method for improving a Split Gate Power MOSFET threshold voltage is provided, comprising the following steps:

[0007] S1. Perform high-density plasma deposition and planarization treatment in the semiconductor substrate, and trench gate lithography;

[0008] S2, forming a gate oxide layer after high-density plasma oxidation;

[0009] S3, polysilicon gate is deposited to Flattening to Then back engrave.

[0010] According to an embodiment of the present invention, the mask used in the photolithography has at least one channel region pattern.

[0011] According to an embodiment of the present invention, the channel region pattern is trapezoidal.

[0012] According to one embodiment of the present invention, the step S2 further includes high-density plasma wet immersion.

[0013] According to one embodiment of the present invention, the high-density plasma oxidation adopts dry oxygen oxidation and wet oxygen oxidation.

[0014] According to an embodiment of the present invention, the etching back includes dry etching and wet etching.

[0015] According to an embodiment of the present invention, the planarization process is performed by chemical mechanical polishing.

[0016] According to an embodiment of the present invention, the polysilicon includes doped polysilicon.

[0017] According to an embodiment of the present invention, the polysilicon deposition includes depositing polysilicon on the bottom, sidewalls and epitaxial surface of the trench.

[0018] According to another aspect of the present invention, a semiconductor device for Split Gate Power MOSFET is provided, which is manufactured by using any one of the above methods for improving the threshold voltage of Split Gate Power MOSFET.

[0019] Due to the adoption of the above technical scheme, the present invention has the following advantages compared with the prior art: on the basis of the existing manufacturing method, the original method of depositing to 12k and then flattening to 6k is adjusted to depositing to 6k and then flattening to 4k, and the shape of the mask is changed. The changed deposition method avoids the excessive difference in uniformity between the center and edge of the wafer caused by too long flattening time, improves the consistency of the performance of the center and edge of the wafer, can make the performance of the device more uniform, and thus improve product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings required for use in the embodiment will be briefly introduced below. Obviously, the drawings described below are only some implementation cases of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic flow chart of a method for improving a Split Gate Power MOSFET threshold voltage according to an exemplary embodiment of the present invention is shown;

[0022] Figure 2 A process flow chart of a method for improving a Split Gate Power MOSFET threshold voltage according to an exemplary embodiment of the present invention is shown;

[0023] Figure 3A schematic diagram of a gate manufacturing method in the prior art is shown. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0025] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0026] like Figure 1 As shown, the present invention provides a method for improving the threshold voltage of Split Gate Power MOSFET, which may specifically include the following steps:

[0027] S1. Perform high-density plasma deposition and planarization treatment in the semiconductor substrate, and trench gate lithography;

[0028] S2, forming a gate oxide layer after high-density plasma oxidation;

[0029] S3, polysilicon gate is deposited to Flattening to Then back engrave.

[0030] like Figure 2 As shown, the mask used in the photolithography in step S1 has at least one channel region pattern. In some embodiments, the channel region pattern is trapezoidal.

[0031] Step S2 also includes high-density plasma soaking.

[0032] In some embodiments, the surface may be cleaned by high density plasma wet immersion in a chemical solution consisting of phosphoric acid and hydrogen peroxide (DPP) and 1% hydrofluoric acid, or other cleaning processes may be used.

[0033] The high-density plasma oxidation adopts dry oxygen oxidation and wet oxygen oxidation.

[0034] The oxide film generated by dry oxygen oxidation has a dense structure, good uniformity and repeatability, strong masking ability, good passivation effect, but a slow growth rate; the oxide film generated by wet oxygen oxidation has a loose structure, surface defects, high water content, poor masking ability for impurities, but a fast growth rate. In actual production, the oxidation method can be determined according to the required structure.

[0035] The etching back includes dry etching and wet etching.

[0036] The etchant of dry etching is plasma, which uses plasma to react with the surface film to form volatile substances, or directly bombards the surface of the film to corrode it. The characteristic of dry etching is that it can achieve various special-shaped etching, thereby ensuring the fidelity of small patterns after transfer.

[0037] Wet etching is an etching method that removes the etched material through a chemical reaction between a chemical etching solution and the etched material. Wet etching has the characteristics of strong adaptability and good surface uniformity, and is suitable for almost all metal stripping plastics and other materials.

[0038] The planarization process is performed by chemical mechanical polishing to make the surface of the product flat.

[0039] Chemical mechanical polishing has the following advantages: (1) It can achieve global flattening; (2) It can flatten a variety of silicon wafer surfaces with little limitation; (3) It can flatten multi-layer materials; (4) It can reduce severe surface undulations and make the interlayer dielectric and metal layers flat, which can achieve smaller design graphics and more layers of metal interconnection, thereby improving circuit reliability, speed and yield; (5) It solves the problem that copper wiring is difficult to etch good graphics; (6) By thinning the surface material, surface defects can be removed to make the surface flatter; (7) Chemical mechanical polishing is a wet grinding method and does not use hazardous gases commonly used in dry etching; (8) Chemical mechanical polishing can achieve equipment automation, mass production, high reliability and key parameter control.

[0040] The polysilicon includes doped polysilicon, and the doping treatment includes ion doping, which needs to at least meet the requirements of high-purity doping, thereby improving the performance of the semiconductor device. The doping is achieved by ion implantation, P (phosphorus) is a preferred doping element, and the raw material for ion implantation is PH3.

[0041] In the prior art, in the manufacturing process of integrated circuits, for the isolation between various independent devices made on a substrate, such as different memory cells and different transistors, a method of forming STI (Shallow Trench Isolation) is often used. A commonly used method for making STI includes the following process: first forming a pad oxide layer and a silicon nitride layer on a substrate; then etching the silicon nitride layer, the pad oxide layer and the substrate in a selected area in sequence to form an isolation trench; then depositing an isolation dielectric on the substrate and performing CMP (Chemical Mechanical Polishing) to flatten it, so that the isolation dielectric and the silicon nitride layer filled in the isolation trench are substantially flush.

[0042] like Figure 3 As shown, after the existing product is ground, the flatness of the top surface obtained after grinding is still insufficient, the difference between the center and the edge of the wafer is large, and a concave morphology is easily generated.

[0043] In the method for improving the threshold voltage of Split Gate Power MOSFET according to an embodiment of the present invention, the gate manufacturing method of the present application adjusts the original method of depositing to 12k and then flattening to 6k to depositing to 6k and then flattening to 4k on the basis of the existing manufacturing method, which greatly shortens the flattening time required by the existing process, and helps to improve the surface flatness of the formed groove structure. Furthermore, the shape of the mask is changed to avoid excessive uniformity differences between the center and edge of the wafer caused by too long flattening time, which can make the performance of the device more uniform, thereby improving product quality, improving the yield rate, and better meeting production needs.

[0044] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for improving the threshold voltage of a Split Gate Power MOSFET, characterized in that: The following steps are involved: S1. Perform high-density plasma deposition and planarization treatment in the semiconductor substrate, and trench gate lithography; S2, forming a gate oxide layer after high-density plasma oxidation; S3, polysilicon gate is deposited to Flattening to Then back engrave.

2. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 1, characterized in that: The mask used in the photolithography has at least one channel region pattern.

3. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 2, characterized in that: The channel region pattern is trapezoidal.

4. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 1, characterized in that: The step S2 also includes high-density plasma soaking.

5. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 1, characterized in that: The high-density plasma oxidation adopts dry oxygen oxidation and wet oxygen oxidation.

6. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 1, characterized in that: The etching back includes dry etching and wet etching.

7. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 1, characterized in that: The planarization process is performed by chemical mechanical polishing.

8. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 1, characterized in that: The polysilicon includes doped polysilicon.

9. The method for improving the threshold voltage of Split Gate Power MOSFET according to claim 1, characterized in that: The polysilicon deposition includes depositing polysilicon on the bottom, sidewall and epitaxial surface of the trench.

10. A semiconductor device, characterized in that: The method according to any one of claims 1 to 9 is used for preparation.

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