Isolation of p-GAN HEMT using gate ring

Abstract

The invention relates to isolation of a P-GAN HEMT using a gate ring. A process of forming a high electron mobility transistor (HEMT) includes forming a semiconductor heterostructure, the semiconductor heterostructure including a channel layer of the HEMT; forming a GaN gate layer on the channel layer; and patterning the gate layer to form a first gate finger, a second gate finger and a gate arc connecting the first gate finger and the second gate finger. The treatment process includes forming an isolation mask covering an active region and a gate arc of the semiconductor heterostructure, and performing ion bombardment treatment on a non-active region of the semiconductor heterostructure exposed by the isolation mask.

Description

Technical Field

[0001] The present disclosure relates to field effect high electron mobility transistors (HEMTs) and processes for manufacturing the same. Background Art

[0002] HEMT devices are known in which a conducting channel is based on the formation of a layer of a two-dimensional electron gas (2DEG) with high mobility at a heterojunction (i.e., at an interface between semiconductor materials with different band gaps). For example, HEMT devices are known based on a heterojunction between an aluminum and GaN (AlGaN) layer and a GaN (GaN) layer.

[0003] HEMT devices based on AlGaN / GaN heterojunctions or heterostructures have several advantages that make them particularly suitable and widely used in different applications. For example, the high breakdown threshold of HEMT devices is used for high-performance power switches; the high electron mobility in the conductive channel allows for high-frequency amplifiers; and the high electron concentration in the 2DEG allows for low on-state resistance (R ON ).

[0004] AlGaN / GaN HEMTs can typically be in depletion mode (normally on). However, for practical applications, enhancement mode (normally off) devices are used to facilitate safe operation and drive circuit simplification. Several methods have been proposed to achieve normally-off HEMTs, namely, recessed gate, fluorine plasma doping under the gate, or p-GaN gate. In the case of p-GaN gate devices, isolation implants can be used to form the inactive regions of the HEMT heterostructure. However, the ion-implanted isolation regions may not form a sharp interface with the active region of the GaN HEMT. Lateral ion penetration may create defects and lead to the formation of parasitic channels on the sides of the HEMT.

[0005] All topics discussed in the background section are not necessarily prior art, and should not be assumed to be prior art simply because the topic is discussed in the background section. As such, any recognition of a problem existing in the prior art discussed in the background section or associated with such topic should not be considered prior art unless explicitly stated to be prior art. Rather, the discussion of any topic in the background section should be considered as part of the inventor's solution to a particular problem, which may itself be inventive. Summary of the invention

[0006] Embodiments of the present disclosure provide a HEMT and a corresponding manufacturing method that overcomes the disadvantages of other HEMTs and formation processes. During processing of the HEMT, a pGaN gate is formed and patterned on a semiconductor heterostructure including a channel layer. The pGaN gate includes a straight first gate finger, a straight second gate finger, and a semicircular gate arc connecting the first gate finger and the second gate finger.

[0007] An isolation mask is formed over the heterostructure, the isolation mask completely covering the pGaN gate, with the edge of the isolation mask being very close to the edge of the gate arc. An isolation implant process is then performed in the presence of the mask to implant ions into the portions of the heterostructure exposed by the mask. The implant process inactivates the exposed portions of the heterostructure in the HEMT device.

[0008] Due to the placement of the isolation mask and the shape of the pGaN gate, the heterostructure beneath the gate fingers is subject to little or no lateral penetration of the isolation implant species. The result is improved performance of the HEMT and reduced formation of parasitic channels at the sides of the HEMT.

[0009] In one embodiment, a method includes forming a semiconductor heterostructure including a channel layer of a HEMT. The method includes forming a gate layer of GaN on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The method includes forming an isolation mask covering an active region and the gate arc of the semiconductor heterostructure, and performing an ion bombardment process on a non-active region of the semiconductor heterostructure exposed by the isolation mask.

[0010] In one embodiment, a device includes a semiconductor heterostructure including an active region and an inactive region and having a channel layer of a HEMT. The device includes a gate layer located on the channel layer and including a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The device includes a source region located between the first gate finger and the second gate finger and in contact with the channel layer therebetween. The channel layer has a higher concentration of an isolation dopant substance in the inactive region than in the active region. The entire gate arc is located directly above the active region.

[0011] In one embodiment, a method includes forming a semiconductor heterostructure and forming a gate layer of GaN on a channel layer, the semiconductor heterostructure including a channel layer of AlGaN of a high electron mobility transistor (HEMT). The method includes patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first gate finger and the second gate finger. The method includes forming an isolation mask covering an active area and the gate arc of the semiconductor heterostructure, and having a substantially straight edge adjacent to the gate arc and at least 500nm away from the first gate finger and the second gate finger. The method includes limiting a non-active area of ​​the semiconductor heterostructure to a lateral outside of the isolation mask by performing an ion bombardment process in the presence of the isolation mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A-1J Cross-sectional and top views of an integrated circuit including various stages of forming a HEMT in the integrated circuit according to one embodiment.

[0013] Figure 2 is a top view of an integrated circuit including a HEMT according to one embodiment.

[0014] Figure 3 is a top view of an integrated circuit including a HEMT according to one embodiment.

[0015] Figure 4 is a flow chart of a method of forming a HEMT according to one embodiment.

[0016] Figure 5 is a flow chart of a method of forming a HEMT according to one embodiment. DETAILED DESCRIPTION

[0017] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, one skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details, or may be practiced using other methods, components, materials, etc. In other instances, well-known systems, components, and circuit systems associated with integrated circuits are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0018] Unless the context requires otherwise, throughout the specification and the claims that follow, the word "include" and variations such as "comprises" and "comprising" are to be interpreted in an open, inclusive sense, i.e., "including but not limited to." Additionally, the terms "first," "second," and similar sequential indicators are to be interpreted as interchangeable unless the context clearly dictates otherwise.

[0019] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in multiple places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0020] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally used in its broadest sense, i.e., meaning "and / or" unless the content clearly dictates otherwise.

[0021] Figure 1A is a cross-sectional view of an integrated circuit 100 at an intermediate stage in forming a HEMT device according to one embodiment. Figure 1A In one embodiment, the integrated circuit 100 includes a substrate 102. The substrate 102 may include a semiconductor material. In one embodiment, the substrate 102 includes silicon. However, the substrate 102 may include other types of semiconductor materials. In some embodiments, the substrate 102 may include one or more layers of dielectric material. The substrate 102 may include other materials suitable for forming a HEMT.

[0022] Although Figure 1A The substrate 102 is shown as a single layer, but in practice, the substrate 102 may include multiple layers. For example, the substrate 102 may include a silicon base layer, an aluminum nitride and silicon layer, and a buffer layer on the aluminum nitride layer, as will be described in more detail below. The substrate 102 may also include silicon carbide, sapphire, aluminum nitride, or other suitable materials.

[0023] In one embodiment, integrated circuit 100 includes semiconductor heterostructure 103 formed on substrate 102. Although heterostructure 103 is shown as being formed on substrate 102, in practice, heterostructure 103 may include a portion of substrate 102 including aluminum nitride and a buffer layer.

[0024] The heterostructure 103 may be formed by an epitaxial growth process. The epitaxial growth process epitaxially grows the semiconductor heterostructure 103 from the substrate 102. The individual layers of the heterostructure 103 may be formed by adjusting the parameters of the epitaxial growth process in situ. For example, the epitaxial growth process may include flowing one or more gases or other materials into a deposition chamber where the integrated circuit 100 (which at this stage is a portion of a semiconductor wafer) is located. The temperature, pressure, and materials may be adjusted throughout the epitaxial growth process to form the multiple layers of the heterostructure 103. In some cases, when one layer of the heterostructure 103 is completed, a purge process may be performed to purge any excess gases or byproducts from the deposition chamber before starting the growth of the next layer.

[0025] In one embodiment, the substrate epitaxial growth process forms a semiconductor layer of aluminum nitride as part of the substrate 102. The aluminum nitride layer can be formed as a precursor to forming multiple GaN layers. Aluminum nitride can be selected as the first layer because gallium may damage the base layer of the substrate 102, especially when the base layer includes silicon. Therefore, the epitaxial growth process first forms the aluminum nitride layer so that the GaN layer can be formed subsequently.

[0026] The buffer layer may include a superlattice of multiple layers formed on the aluminum nitride layer during the first epitaxial growth process. In an example where the substrate 102 includes an aluminum nitride layer and a subsequent GaN layer is to be formed, the first layer of the superlattice may include an AlGaN layer in which the percentage of aluminum is high and the percentage of gallium is low to enable epitaxial growth from the aluminum nitride layer. Subsequent layers of the superlattice include AlGaN in which the concentration of gallium increases and the concentration of aluminum decreases. Finally, the top layer of the superlattice may include GaN without any aluminum. The superlattice may include up to 200 layers. The superlattice may include other materials and structures without departing from the scope of the present disclosure. The superlattice may also include AlGaN and AlN.

[0027] After forming the superlattice, a layer 104 is formed on the substrate 102. In particular, the layer 104 may be formed on the superlattice of the substrate 102. In an example where the superlattice is a transition structure including multiple layers that gradually transition from aluminum nitride to GaN, the layer 104 may include GaN. In one embodiment, the layer 104 of GaN includes a p-type or n-type dopant. In one embodiment, the layer 104 of GaN is doped with carbon atoms, which may produce n-type or p-type doping (depending on the concentration of carbon). In another embodiment, the layer 104 of GaN is doped with magnesium atoms. The total thickness of the layer 104 may be about 1 μm. The total thickness of the superlattice may also be about 2 μm. The composition of the superlattice and the GaN layer 104 may help to form a HEMT device that can operate at very high voltages. For example, the composition of the superlattice and the GaN layer 104 may help the HEMT device operate at more than 600V between the terminals of the HEMT device. Other materials, thicknesses, and operating voltages may be used without departing from the scope of the present disclosure.

[0028] In one embodiment, layer 104 may include multiple layers. In one embodiment, layer 104 may include an intrinsically doped channel layer GaN that does not include any doping.

[0029] In one embodiment, layer 104 may include multiple layers. For example, layer 104 may include a layer GaN doped with a p-type dopant as described above. Layer 104 may also include a back barrier layer of GaN and a p-doped region of GaN.

[0030] In one example, the back barrier layer may be doped with magnesium atoms. The thickness of the back barrier layer may be between 50 nm and 300 nm. Other materials and thicknesses may be used for the back barrier layer without departing from the scope of the present disclosure. In addition, in some embodiments, the back barrier layer may not exist.

[0031] In one embodiment, heterostructure 103 includes barrier layer 106 and channel layer 104. The interface between barrier layer 106 and layer 104 corresponds to a layer in which a two-dimensional electron gas (2DEG) is formed during operation of the transistor. Free electrons flow through the channel region based on the bias between the source and drain regions and the control voltage applied to the gate electrode, as will be explained in more detail below.

[0032] In one embodiment, the barrier layer 106 includes AlGaN. The percentage of aluminum can be between 1% and 50%, but other compositions can be used without departing from the scope of the present disclosure. The thickness of the AlGaN layer can be between 1nm and 30nm. Other compositions and thicknesses can be used for the AlGaN layer without departing from the scope of the present disclosure.

[0033] In one embodiment, barrier layer 106 may include a thin aluminum nitride layer between the GaN layer and the AlGaN layer.Barrier layer 106 may have a variety of compositions without departing from the scope of the present disclosure.

[0034] The semiconductor heterostructure 103 includes a gate layer 108, as well as a channel layer 104 and a barrier layer 106. The gate layer 108 may include GaN heavily doped with a P-type dopant. Therefore, the gate layer 108 may be referred to as a p-GaN layer. The heavy doping of the gate layer 108 results in a high conductivity of the gate layer 108. This enables the semiconductor material of the gate layer 108 to act as a conductive gate layer to some extent. The thickness of the gate layer 108 may be between 50nm and 150nm. Other thicknesses and materials may be used without departing from the scope of the present disclosure.

[0035] exist Figure 1B , the gate layer 108 has been patterned to expose a portion of the barrier layer 106. The gate layer 108 may be patterned according to a photolithography process, in which a mask is formed in a desired pattern on the gate layer 108. An etching process may then be performed to remove the gate layer 108 at locations exposed by the mask, thereby producing a patterned gate layer 108.

[0036] Figure 1C According to one embodiment Figure 1B 1. A top view of integrated circuit 100 at a processing stage is shown in FIG. Figure 1C The top view of FIG. 1 illustrates the gate layer 108 after patterning, a straight first gate finger 110 extending in the X direction, and a straight second gate finger 112 extending in the X direction parallel to the straight first gate finger 110. The gate layer 108 includes Figure 1C The gate layer 108 includes a gate arc 114 connecting the first gate finger 110 and the second gate finger 112 at the top. Figure 1C The gate layer 108 further includes an outer edge 118 . Figure 1C Also shown is a cutout Figure 1B The cutting line of the cross section corresponds to the cutting line 1B. Figure 1C The view of 104 illustrates the exposed portion of the barrier layer 106 not covered by the gate layer 108. The patterned gate layer 108 may also be referred to as a gate ring.

[0037] Figure 1D is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 1D In FIG. 1 , a dielectric layer 124 has been formed on the gate layer 108 and on the exposed portion of the barrier layer 106. The dielectric layer may include aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, silicon nitride, silicon oxide, or other suitable dielectric materials.

[0038] exist Figure 1D , a mask 126 has been formed on the dielectric layer 124. The mask 126 corresponds to an isolation mask, which will be used to separate the active region of the heterostructure 103 from the inactive region of the heterostructure 103. More specifically, the isolation mask is used to perform an isolation implantation process, during which ions are implanted into the portion of the heterostructure 103 that is not covered by the isolation mask 126. The implantation process causes the exposed portion of the heterostructure 103 to become the inactive region of the heterostructure 103, while the unexposed portion of the heterostructure 103 corresponds to the active region of the heterostructure 103.

[0039] The mask 126 may correspond to a hard mask including a dielectric material, a conductive material, a ceramic material, or other material through which ions will not pass during a subsequent ion implantation process. The mask 126 may be patterned using a photolithography process.

[0040] like Figure 1D As can be seen in FIG. 1 , mask 126 includes edge 128. Edge 128 is positioned beyond edge 118 of gate layer 108 in the X direction. The lateral distance between edge 128 and edge 118 helps ensure that any lateral implantation of ions during the ion implantation process will not extend under first and second fingers 110 / 112. In one embodiment, the lateral distance between edge 128 of mask 126 and edge 118 of gate layer 108 is less than 5 μm. Other sizes, materials, and shapes may be used for mask 126 without departing from the scope of the present disclosure.

[0041] Figure 1E According to one embodiment Figure 1D 1. A top view of integrated circuit 100 at a processing stage is shown in FIG. Figure 1E The top view of FIG. 1 illustrates the location of edge 128 of mask 126 . Figure 1D The location of the gate layer 108 below the mask 126 is also illustrated in dashed lines. The edge 128 of the mask 126 is straight and extends in a direction transverse to, and substantially perpendicular to, the first and second gate fingers 110 and 112. In addition, the edge 128 extends beyond the edge 118 of the gate layer 108 so that the entire gate arcs 114 and 116 are covered by the mask 126.

[0042] Figure 1F1 is a cross-sectional view of integrated circuit 100 during an ion implantation process according to one embodiment. The ion implantation process may correspond to an isolation implantation process. During the implantation process, ions (atoms or compounds having a net charge) bombard integrated circuit 100. The ions do not pass through mask 126. The ions penetrate into layers 104 and 106 at the areas exposed by mask 126. The penetration of the ions into layers 104 and 106 severely damages the semiconductor lattice of the semiconductor material of the heterostructure. This causes the exposed portion of the heterostructure to become an inactive area. The portion of heterostructure 103 covered by mask 126 is still an active area of ​​heterostructure 103. The active area of ​​heterostructure 103 is part of the HEMT to be formed.

[0043] In one embodiment, the ions disrupt the lattice of layers 104 and 106 at the exposed areas. In one embodiment, the ions may include nitrogen, argon, and boron ions. In one embodiment, the ions include nitrogen molecules carrying a net charge. For the isolation implant process, other types of particles may be used without departing from the scope of the present disclosure.

[0044] Figure 1G According to one embodiment Figure 1F 1 is a cross-sectional view of the integrated circuit 100 after the ion implantation process. The mask 126 has been removed. Figure 1G An active region 140 of the heterostructure 103 and an inactive region 142 of the heterostructure 103 are illustrated. Figure 1G Also illustrated is a boundary 144 between the inactive region 142 and the active region 140 .

[0045] In practice, there is likely to be some lateral implantation of ions into areas not covered by the mask 106. However, the position of the mask relative to the shape and position of the gate layer 108 helps ensure that there will not be a significant amount of lateral implantation into the area of ​​the heterostructure 103 directly beneath the gate fingers 110 and 112. The non-active region 142 is different from the active region 140 due to the higher concentration of nitrogen in the non-active region 142 compared to the active region 140. The non-active region 142 is different from the active region 140 due to the semiconductor layer of the heterostructure 103 being damaged or the lattice being disrupted in the non-active region 142.

[0046] Figure 1G Boundary 144 is illustrated as being located at a position corresponding to edge 128 of mask 126. However, in practice, there will be some lateral implantation of ions beneath mask 126. Boundary 144 may correspond to a position at which the concentration of implanted ions has a particular value.

[0047] Figure 1H According to an embodiment Figure 1G A top view of the integrated circuit 100 is shown. Figure 1HA boundary 144 between the active region 140 and the inactive region 142 is illustrated.

[0048] Fig. 1I is a top view of integrated circuit 100 after further forming components of HEMT 101 according to one embodiment. Figure 1G , according to one embodiment, source region 154 and drain region 160 have been formed. A photolithography process may be performed to form a trench that extends partially into barrier layer 106. Source / drain metal may then be deposited and patterned to form source region 154 and drain region 160. The source / drain metal may include titanium, tantalum, aluminum, titanium nitride, or other suitable conductive materials. The source / drain metal may be deposited by PVD, ALD, CVD, or other suitable deposition processes.

[0049] exist Fig. 1I , a gate electrode 150 has been formed on the gate layer 108. The gate electrode 150 is made of a gate metal. The gate metal may include titanium nitride, titanium, aluminum, tungsten, and may be deposited by PVD, ALD, CVD or other suitable deposition processes. The gate metal may include other materials and configurations without departing from the scope of the present disclosure. For example, although the gate metal is shown as a single gate metal, in practice, there may be multiple gate metals.

[0050] To keep it simple, Fig. 1I The top view of FIG. 1 does not illustrate other components that may be present in HEMT 101. For example, field plates, metal lines, and other components such as Figure 1J as shown in .

[0051] The HEMT 101 may include various other layers, including passivation layers and other dielectric layers to isolate and protect the source / drain metals and the gate electrode 150. The HEMT may be operated by applying a control voltage to the gate electrode 150 and applying a bias to the source region 154 and the drain region 160. Depending on the control and bias voltages, the HEMT may be turned on or off. When the HEMT is turned on, the current of the electron gas may flow through the channel layer 106 and under the bottom of the gate layer 108 between the drain region 160 and the source region 154.

[0052] exist Fig. 1I , the source region 154 has a rounded end and has been formed laterally between the first gate finger 110, the second gate finger 112 and the gate arc 114 / 116. The drain region 160 extends further in the X direction than the source region 154. In particular, the drain region 160 extends into the non-active region 142, while the source region 154 is completely located in the active region 140. In addition, the drain region 160 has a straight end extending in the Y direction at an early stage, while the source region 154 has a rounded end.

[0053] Compared to other possible solutions, Fig. 1I The HEMT 101 structure provides several advantages. For example, the threshold voltage of the HEMT 101 can be increased. For example, the threshold voltage can be about 1V. In addition, the drain current can have a much steeper rise after reaching the threshold voltage. In addition, Fig. 1I The HEMT 101 provides lower drain leakage in the off state. The on-resistance (effective resistance between the source and the drain in the saturation region) of the HEMT 101 does not increase relative to other solutions.

[0054] Figure 1J According to one embodiment, the cut line 1J is cut Fig. 1I 1 is a cross-sectional view of an integrated circuit 100 . Figure 1J The cross-sectional view shows Fig. 1I Additional components not shown in FIG. Figure 1J Dielectric layer 170 and dielectric layer 124 are illustrated. Figure 1J Dielectric layer 172 and dielectric layer 170 are illustrated. Figure 1J A field plate 174 is shown which may be used to apply a selected electric field to the channel region in addition to the gate voltage. Figure 1J Metal lines 176 on dielectric layer 172 are also illustrated.

[0055] Figure 1J The source region 154 and the drain region 160 are shown formed in trenches through the dielectric layers 170 and 124 and the barrier layer 106. Thus, the source region 154 and the drain region 160 are in contact with the channel layer 106. Figure 1J , source region 154 and drain region 160 terminate at the top surface of layer 104. However, source region 154 and drain region 160 may terminate within channel layer 106 or within layer 104. Various other configurations of HEMT 101 may be used without departing from the scope of the present disclosure. Fig. 1I and 1J Not shown, but gate contacts, source contacts, and drain contacts may be present to electrically connect source region 154, drain region 160, and gate 150, as well as other conductive structures formed thereon.

[0056] Figure 2 is a top view of an integrated circuit 100 including a HEMT 101 according to one embodiment. Figure 2 It is illustrated that the HEMT 101 may include multiple gate layers 108, multiple source regions 154, and multiple drain regions 160. The HEMT may include a number of source regions 154, drain regions 160, and gate rings 108. A field plate 174 is also shown adjacent to the gate ring 108.

[0057] Figure 3is a top view of an integrated circuit 100 including a HEMT 101 according to one embodiment. Figure 3 HEMT 101 with Fig. 1I The HEMT of is substantially similar except that the active region 140 has a boundary 144 which is not a straight line. Instead, the boundary has a linear portion extending laterally from the gate fingers 110 and 112 in the Y direction, and a semicircular arc portion having substantially the same shape as the edge 118 of the gate arcs 114 and 116.

[0058] Figure 3 The boundary 144 between the active region 140 and the inactive region 142 in the embodiment of the present invention can be formed by forming a semicircular protrusion having a desired pattern similar to that of the boundary 144. Figure 1D The subsequent isolation bombardment process will produce an active region 140 and an inactive region 142 that share a boundary 144, such as Figure 3 as shown in .

[0059] In one embodiment, HEMT 101 may be used Fig. 1I The retracted gate ring 108 shown in FIG. 1 is formed without the isolation implant process. In other words, in one embodiment, the mask 126 is not formed in the isolation bombardment process performed. As a result, there is no non-active area in which the crystal structure is destroyed by the isolation bombardment process.

[0060] Figure 4 is a flow chart of a method 400 of forming a HEMT according to one embodiment. The method 400 may use Figure 1A-Figure 3 The method 400 includes forming a semiconductor heterostructure including a channel layer of a HEMT at 402. At 404, the method 400 includes forming a gate layer of GaN on the channel layer. At 406, the method 400 includes patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. At 408, the method 400 includes forming an isolation mask covering an active area of ​​the semiconductor heterostructure and the gate arc. At 410, the method 400 includes performing an ion bombardment process on a non-active area of ​​the semiconductor heterostructure exposed by the isolation mask.

[0061] Figure 5 is a flow chart of a method 500 of forming a HEMT according to one embodiment. The method 500 may be used with respect to Figure 1A-Figure 3The process, structure, and system described herein. At 502, the method 500 includes forming a semiconductor heterostructure including a channel layer of AlGaN of a HEMT. At 504, the method 500 includes forming a gate layer of GaN on the channel layer. At 506, the method 500 includes patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first gate finger and the second gate finger. At 508, the method 500 includes forming an isolation mask covering an active region and the gate arc of the semiconductor heterostructure and having a substantially straight edge adjacent to the gate arc and at least 500 nm from the first gate finger and the second gate finger. At 510, the method 500 includes defining a non-active region of the semiconductor heterostructure laterally outside of the isolation mask by performing an ion bombardment process in the presence of the isolation mask.

[0062] In one embodiment, a method includes forming a semiconductor heterostructure, the semiconductor heterostructure including a channel layer of a HEMT. The method includes forming a gate layer of GaN on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The method includes forming an isolation mask covering an active area and a gate arc of the semiconductor heterostructure, and performing an ion bombardment treatment on a non-active area of ​​the semiconductor heterostructure exposed by the isolation mask.

[0063] In one embodiment, the method includes forming a source region between the first gate finger and the second gate finger and contacting the channel layer in the active region.

[0064] In one embodiment, the source region does not contact the channel layer outside the active area.

[0065] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and the isolation mask has a substantially straight edge extending beyond the first gate finger, the second gate finger and the gate arc in a second direction transverse to the first direction.

[0066] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and the edge of the isolation mask has a first portion having an arc shape in the shape of an outer edge of the gate arc adjacent to the gate arc.

[0067] In one embodiment, the edge of the isolation mask has a second portion that is straight and extends in a second direction transverse to the first direction and is connected to the first portion.

[0068] In one embodiment, the method includes removing the isolation mask after performing the ion bombardment process, and forming the source region after removing the isolation mask.

[0069] In one embodiment, the method includes forming a drain region in contact with the channel region in the same process as forming the source region.

[0070] In one embodiment, the ion bombardment treatment includes implanting nitrogen ions in the inactive region.

[0071] In one embodiment, the method includes doping the gate layer with a p-type dopant.

[0072] In one embodiment, the channel region comprises AlGaN.

[0073] In one embodiment, the source region contacts a portion of the channel layer outside the active area.

[0074] In one embodiment, a device includes a semiconductor heterostructure including an active region and an inactive region and having a channel layer of a HEMT. The device includes a gate layer of GaN, the gate layer being on the channel layer and including a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The device includes a source region located between the first gate finger and the second gate finger and contacting the channel layer therebetween. The channel layer has a higher concentration of an isolation dopant substance in the inactive region than in the active region. The entire gate arc is located directly above the active region.

[0075] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and the boundary between the active area and the inactive area has a substantially straight edge that extends beyond the first gate finger, the second gate finger and the gate arc in a second direction transverse to the first direction.

[0076] In one embodiment, the first gate finger and the second gate finger extend in a first direction, and wherein a boundary between the active region and the inactive region has a first portion adjacent to the gate arc, the first portion being in an arc shape in the shape of an outer edge of the gate arc.

[0077] In one embodiment, the boundary between the active region and the inactive region has a second portion that is straight, extends in a second direction transverse to the first direction, and is connected to the first portion.

[0078] In one embodiment, the device includes a drain region of the HEMT in contact with the channel region in the inactive region and the active region.

[0079] In one embodiment, the drain region has substantially straight edges, wherein the source region has semi-circular edges.

[0080] In one embodiment, a method includes forming a semiconductor heterostructure and forming a gate layer of GaN on a channel layer, the semiconductor heterostructure including a channel layer of AlGaN of a high electron mobility transistor (HEMT). The method includes patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first gate finger and the second gate finger. The method includes forming an isolation mask covering an active area and the gate arc of the semiconductor heterostructure, and having a substantially straight edge adjacent to the gate arc and at least 500nm away from the first gate finger and the second gate finger. The method includes limiting a non-active area of ​​the semiconductor heterostructure to a lateral outside of the isolation mask by performing an ion bombardment process in the presence of the isolation mask.

[0081] In one embodiment, the ion bombardment process implants nitrogen atoms in the inactive regions of the semiconductor heterostructure.

[0082] In one embodiment, the method includes: removing the isolation mask; forming a source region of the HEMT located between the first gate finger and the second gate finger and contacting the channel layer only at the active area; and forming a drain region of the HEMT contacting the channel layer at the active area and the inactive area.

[0083] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments according to the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms given by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A method comprising: forming a semiconductor heterostructure including a channel layer of a high electron mobility transistor (HEMT); forming a GaN gate layer on the channel layer; Patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger; forming an isolation mask covering an active region and a gate arc of the semiconductor heterostructure; as well as An ion bombardment process is performed on the inactive area of ​​the semiconductor heterostructure exposed by the isolation mask. 2 . The method of claim 1 , comprising forming a source region between the first gate finger and the second gate finger and in contact with the channel layer in the active region. The method of claim 2 , wherein the source region contacts a portion of the channel layer outside the active region.

4. The method of claim 2, wherein the first gate finger and the second gate finger extend in a first direction, wherein the isolation mask has a substantially straight edge that extends beyond the first gate finger, the second gate finger, and the gate arc in a second direction transverse to the first direction.

5. The method of claim 2, wherein the first gate finger and the second gate finger extend in a first direction, wherein the edge of the isolation mask has a first portion adjacent to the gate arc, the first portion being in an arc shape in the shape of an outer edge of the gate arc. 6 . The method of claim 5 , wherein the edge of the isolation mask has a second portion that is straight, extends in a second direction transverse to the first direction, and is connected to the first portion.

7. The method of claim 2, comprising: removing the isolation mask after performing the ion bombardment process; as well as The source region is formed after removing the isolation mask.

8. The method of claim 7, comprising forming the drain region in contact with the channel region in the same process as forming the source region.

9. The method of claim 1, wherein the ion bombardment treatment comprises implanting nitrogen ions in the inactive region.

10. The method of claim 1 including doping the gate layer with a p-type dopant. The method of claim 1 , wherein the channel region comprises AlGaN.

12. A device comprising: A semiconductor heterostructure including an active region and an inactive region and having a channel layer of a high electron mobility transistor (HEMT); A GaN gate layer, located on the channel layer and comprising a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger; A source region is located between the first gate finger and the second gate finger and contacts a channel layer therebetween, wherein the channel layer has a higher concentration of an isolation dopant substance in the inactive region than in the active region, wherein the entire gate arc is located directly above the active region.

13. The device of claim 12, wherein the first gate finger and the second gate finger extend in a first direction, wherein a boundary between the active region and the inactive region has a substantially straight edge that extends beyond the first gate finger, the second gate finger, and the gate arc in a second direction transverse to the first direction.

14. The device of claim 12, wherein the first gate finger and the second gate finger extend in a first direction, wherein a boundary between the active region and the inactive region has a first portion adjacent to the gate arc, the first portion being in an arc shape in the shape of an outer edge of the gate arc.

15. The device of claim 14, wherein the boundary between the active region and the inactive region has a second portion that is straight, extends in a second direction transverse to the first direction, and is connected to the first portion.

16. The device of claim 12, comprising a drain region of the HEMT in contact with the channel region in the inactive region and the active region.

17. The device of claim 16, wherein the drain region has substantially straight edges, and wherein the source region has semi-circular edges.

18. A method comprising: forming a semiconductor heterostructure including a channel layer of AlGaN of a high electron mobility transistor (HEMT); forming a GaN gate layer on the channel layer; Patterning the gate layer to form a first gate finger extending in a first direction, a second gate finger extending in the first direction, and a gate arc connecting the first gate finger and the second gate finger; forming an isolation mask covering the active region and the gate arc of the semiconductor heterostructure and having a substantially straight edge adjacent to the gate arc and at least 500 nm away from the first gate finger and the second gate finger; as well as By performing an ion bombardment process in the presence of the isolation mask, an inactive region of the semiconductor heterostructure is defined laterally outside the isolation mask.

19. The method of claim 18, wherein the ion bombardment process implants nitrogen atoms in the inactive region of the semiconductor heterostructure.

20. The method of claim 19, comprising: removing the isolation mask; forming a source region of the HEMT located between the first gate finger and the second gate finger and contacting the channel layer only at the active region; as well as A drain region of the HEMT is formed in contact with the channel layer at the active region and the inactive region.

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