Shield gate groove type MOSFET device and preparation method thereof

Abstract

The invention provides a shield gate trench type MOSFET device and a preparation method thereof, and the method comprises the steps: forming a first trench unit in an epitaxial layer, forming a first high-k dielectric layer and a first polysilicon layer in the first trench unit, forming a second polysilicon layer above the first polysilicon layer, and enabling the second polysilicon layer to be in direct contact connection with the first polysilicon layer, the first polycrystalline silicon layer and the epitaxial layer are in direct contact to form a Schottky barrier diode, a trench gate structure is formed at the second polycrystalline silicon layer, finally, the Schottky barrier diode is connected with a body diode area of the MOS device in parallel, minority carriers in the reverse recovery process are rapidly extracted through the Schottky barrier diode, and the recovery efficiency of the MOS device is improved. The reverse recovery current and the reverse recovery time are reduced, the reverse recovery loss of the device is reduced, the modulation effect of the first high-k dielectric layer on the electric field is utilized, the electric field near the bottom of the first polycrystalline silicon layer is reduced, the breakdown voltage of the device is improved, the leakage of the drain / source electrode of the device is improved, and finally the performance of the device is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a shielded gate trench type MOSFET device and a preparation method thereof. Background Art

[0002] Traditional shielded gate trench MOS devices (SGT MOS) optimize the electric field distribution by introducing a shielding gate in the trench, thereby improving the on-resistance, switching speed and reliability of the device. This technology is widely used in medium and low voltage fields, such as motor drive, power management, synchronous rectification, energy storage control and other fields. Traditional shielded gate trench MOS devices optimize the trade-off relationship between breakdown voltage and on-resistance based on the two-dimensional charge coupling principle, so that their on-resistance can be lower than the silicon limit theory of ordinary trench MOSFET. At the same time, due to the electric field shielding effect of the shielding gate, the electric field coupling between the gate and the drain is shielded, the gate-drain capacitance is reduced, the switching speed is increased, the dynamic loss of the device is reduced, and the energy efficiency of the system is improved.

[0003] When the shielded gate trench MOS device of the prior art operates in reverse conduction, that is, when the gate-source voltage Vgs is less than the threshold voltage Vth and the drain-source voltage Vds is less than 0, its reverse current flows from the source to the drain through the body diode. At this time, there is a phenomenon of minority carrier injection in the current of the body diode, and these minority carriers reverse recover when the body diode is reverse biased again, resulting in a large reverse recovery current and a long reverse recovery time.

[0004] Therefore, how to optimize the reverse recovery characteristics of the conventional shielded gate trench MOS device to reduce the reverse recovery loss of the shielded gate trench MOS device has become a technical problem to be solved urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a shielded gate trench MOSFET device and a preparation method thereof, which are used to optimize the reverse recovery characteristics of the traditional shielded gate trench MOS device and thereby reduce the reverse recovery loss of the shielded gate trench MOS device.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a shielded gate trench MOSFET device, the preparation method comprising the following steps:

[0008] Providing a semiconductor substrate having an epitaxial layer, and forming a plurality of first trench units in the epitaxial layer;

[0009] forming a first high-k dielectric layer on the inner wall of the first trench unit and the surface of the epitaxial layer;

[0010] Etching and removing the first high-k dielectric layer at the bottom of the first trench unit, and filling the first polysilicon layer in the first trench unit;

[0011] Etching the first high-k dielectric layer and the first polysilicon layer in the first trench unit to a first preset position;

[0012] forming a first gate dielectric layer on the surfaces of the first high-k dielectric layer and the first polysilicon layer, etching the first gate dielectric layer to form a second trench unit, wherein the first polysilicon layer is exposed at the bottom of the second trench unit;

[0013] Filling a second polysilicon layer in the second trench unit, and etching the second polysilicon layer in the second trench unit and the first gate dielectric layer to a second preset position;

[0014] Forming a trench gate structure on the surfaces of the first gate dielectric layer and the second polysilicon layer, performing ion implantation on the upper surface of the epitaxial layer on the side of the first trench unit to form a body region, and performing ion implantation on the upper surface of the body region to form a source region;

[0015] forming an interlayer dielectric layer on the source region, and etching the interlayer dielectric layer, the source region and the body region to form a plurality of first contact holes penetrating the interlayer dielectric layer and the source region and exposing the body region;

[0016] A metal is deposited on the interlayer dielectric layer to form a front metal layer, and the front metal layer fills the first contact hole.

[0017] Optionally, after forming the front metal layer, the method further includes forming a passivation layer, etching the passivation layer to form a metal lead, and forming a drain electrode, wherein the passivation layer is located on the surface of the front metal layer, and the drain electrode is electrically connected to the back side of the semiconductor substrate.

[0018] Optionally, the first high-k dielectric layer and the first polysilicon layer have flush surfaces, the first high-k dielectric layer includes a first high-k sub-dielectric layer and a second high-k sub-dielectric layer, and the first high-k sub-dielectric layer and the second high-k sub-dielectric layer are symmetrically distributed about the first polysilicon layer.

[0019] Optionally, a ratio of a lateral width of the first polysilicon layer to a lateral width of the first high-k dielectric layer is 0.2-5, and a ratio of a lateral width of the first polysilicon layer to a lateral width of the second polysilicon layer is 0.2-5.

[0020] Optionally, the first gate dielectric layer and the second polysilicon layer have flush surfaces, the first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer, and the first sub-gate dielectric layer and the second sub-gate dielectric layer are symmetrically distributed about the second polysilicon layer.

[0021] Optionally, a ratio of a lateral width of the second polysilicon layer to a lateral width of the first sub-gate dielectric layer is 0.2-5.

[0022] Optionally, a ratio of a longitudinal height of the first high-k dielectric layer to a longitudinal height of the second polysilicon layer is 0.25-4.

[0023] In addition, the present invention also provides a shielded gate trench MOSFET device, the shielded gate trench MOSFET device at least comprising:

[0024] A semiconductor substrate having an epitaxial layer;

[0025] A first trench unit is located in the epitaxial layer;

[0026] A first high-k dielectric layer is located on an inner wall of the first trench unit, the first high-k dielectric layer includes a first high-k sub-dielectric layer and a second high-k sub-dielectric layer, and a height of the first high-k dielectric layer is lower than a height of the first trench unit;

[0027] A first polysilicon layer, located between the first high-k dielectric layer and the second high-k dielectric layer and filling the first trench unit, and having a flush surface with the first high-k dielectric layer;

[0028] a first gate dielectric layer, wherein the first gate dielectric layer is located in the first trench unit and on the first polysilicon layer, a second trench unit is formed in the first gate dielectric layer, and the first polysilicon layer is exposed at the bottom of the second trench unit;

[0029] A second polysilicon layer, filling the second trench unit and being arranged in contact with the first polysilicon layer, and having a surface flush with the first gate dielectric layer;

[0030] a trench gate structure, wherein the trench gate structure is located on the second polysilicon layer and the first gate dielectric layer, and an upper surface of the trench gate structure is flush with the source region;

[0031] a body region, located on an upper surface of the epitaxial layer and adjacent to the first trench unit, wherein a lower surface of the body region is higher than the second polysilicon layer;

[0032] a source region, located on an upper surface of the body region;

[0033] an interlayer dielectric layer, located on an upper surface of the source region, and having a first contact hole exposing the body region;

[0034] A front metal layer is located on the interlayer dielectric layer and fills the first contact hole.

[0035] Optionally, the trench gate structure includes a second gate dielectric layer and a third polysilicon gate, wherein the third polysilicon gate is isolated from the source region, the body region and the second polysilicon layer by the second gate dielectric layer, and the second gate dielectric layer covers the upper surface of the third polysilicon gate and is flush with the source region.

[0036] Optionally, the shielded gate trench MOSFET device includes a P-type MOSFET device or an N-type MOSFET device.

[0037] As described above, the shielded gate trench MOSFET device and its preparation method of the present invention at least include: forming a first trench unit on a substrate having an epitaxial layer, forming a first high-k dielectric layer and a first polysilicon layer in the first trench unit, and forming a second polysilicon layer surrounded by a first gate dielectric layer above the first polysilicon layer, the second polysilicon layer is directly in contact with the first polysilicon layer, the first high-k dielectric layer is symmetrically distributed about the first polysilicon layer, and the first polysilicon layer is in direct contact with the epitaxial layer to form a Schottky barrier diode, and then forming a trench gate structure above the second polysilicon layer, so that the Schottky barrier diode and the body diode of the device are finally The regions are connected in parallel, and the Schottky barrier diode is used to quickly extract the minority carriers in the reverse recovery process, thereby reducing the reverse recovery current and the reverse recovery time, thereby reducing the reverse recovery loss of the device. At the same time, the modulation effect of the first high-k dielectric layer on the electric field is used to reduce the electric field near the bottom of the first polysilicon layer, thereby increasing the device breakdown voltage, improving the device drain / source leakage, and improving the device performance. Furthermore, the MOS device proposed in the present application and the traditional MOS device can be arranged in an alternating manner to form a MOS device with another structure, so that the MOS device with another structure can be optimized in a compromise between reverse recovery optimization and source / drain leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Shown is a schematic flow chart of a method for preparing a shielded gate trench MOSFET device of the present invention.

[0039] Figure 2It is a schematic structural diagram of the present invention after forming a first trench unit in the epitaxial layer.

[0040] Figure 3 It is a schematic structural diagram of the present invention after a first high-k dielectric layer is formed on the sidewall of the first trench unit and the surface of the epitaxial layer.

[0041] Figure 4 It is a schematic diagram of the structure after the first trench unit is filled with the first polysilicon layer in the present invention.

[0042] Figure 5 It is a schematic diagram of the structure after the first high-k dielectric layer and the first polysilicon layer are etched to the first preset position.

[0043] Figure 6 It is a schematic diagram of the structure after forming the first gate dielectric layer and the second trench unit in the present invention.

[0044] Figure 7 It is a schematic diagram of the structure after the second polysilicon layer is filled in the second trench unit and etched to the second preset position in the present invention.

[0045] Figure 8 It is a schematic diagram of the structure after the trench gate structure, body region and source region are formed in the present invention.

[0046] Fig. 9 It is a schematic diagram of the structure after the interlayer dielectric layer and the first contact hole are formed in the present invention.

[0047] Fig.10 It is a schematic diagram showing the structure of forming a front metal layer in the present invention.

[0048] Fig.11 Shown is a schematic structural diagram of a shielded gate trench MOSFET device in the present invention.

[0049] Description of Reference Numerals

[0050] 10. semiconductor substrate; 11. epitaxial layer; 12. first trench unit; 13. first high-k dielectric layer; 131. first high-k sub-dielectric layer; 132. second high-k sub-dielectric layer; 14. first polysilicon layer; 151. first sub-gate dielectric layer; 152. second sub-gate dielectric layer; 16. second polysilicon layer; 171. second gate dielectric layer; 172. third polysilicon layer; 18. body region; 19. source region; 20. interlayer dielectric layer; 211. first contact hole; 22. front metal layer; 23. passivation layer; 24. drain; S1~S9, steps. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0053] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0054] See also Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] Example 1

[0056] This embodiment provides a method for preparing a shielded gate trench MOSFET device. Figure 1 , shown as a process flow chart of the preparation method, comprising the following steps:

[0057] S1: providing a semiconductor substrate 10 having an epitaxial layer 11, and forming a plurality of first trench units 12 in the epitaxial layer 11;

[0058] S2: forming a first high-k dielectric layer 13 on the inner wall of the first trench unit 12 and the surface of the epitaxial layer 11;

[0059] S3: etching and removing the first high-k dielectric layer 13 at the bottom of the first trench unit 12, and filling the first polysilicon layer 14 in the first trench unit 12;

[0060] S4: etching the first high-k dielectric layer 13 and the first polysilicon layer 14 in the first trench unit 12 to a first preset position;

[0061] S5: forming a first gate dielectric layer on the surfaces of the first high-k dielectric layer 13 and the first polysilicon layer 14, etching the first gate dielectric layer to form a second trench unit, wherein the first polysilicon layer 14 is exposed at the bottom of the second trench unit;

[0062] S6: filling the second polysilicon layer 16 in the second trench unit, and etching the second polysilicon layer 16 in the second trench unit and the first gate dielectric layer to a second preset position;

[0063] S7: forming a trench gate structure on the surfaces of the first gate dielectric layer and the second polysilicon layer 16, performing ion implantation on the upper surface of the epitaxial layer 11 on the side of the first trench unit 12 to form a body region 18, and performing ion implantation on the upper surface of the body region 18 to form a source region 19;

[0064] S8: forming an interlayer dielectric layer 20 on the source region 19, and etching the interlayer dielectric layer 20, the source region 19 and the body region 18 to form a plurality of first contact holes 211 penetrating the interlayer dielectric layer 20 and the source region 19 and exposing the body region 18;

[0065] S9 : depositing metal on the interlayer dielectric layer 20 to form a front metal layer 22 , and the front metal layer 22 fills the first contact hole 211 .

[0066] Specifically, since the shielded gate trench MOSFET device structure can be an N-type device or a P-type device, in this embodiment, an N-type device is taken as an example for detailed description, that is, the first conductivity type is N-type. When the shielded gate trench MOSFET device structure is a P-type device, the first conductivity type becomes P-type, and the second conductivity type is opposite to the first conductivity type, that is, only the corresponding N-type and P-type need to be swapped.

[0067] The method for preparing the shielded gate trench MOSFET device of this embodiment is described in detail below with reference to the specific drawings.

[0068] like Figure 2 As shown, step S1 is performed to provide a semiconductor substrate 10 having an epitaxial layer 11 , and to form a plurality of first trench units 12 in the epitaxial layer 11 .

[0069] Specifically, Figure 2 , which is a schematic diagram of a cross-sectional structure of the semiconductor substrate 10 , wherein the semiconductor substrate 10 is a semiconductor substrate 10 doped with a first conductivity type, and an epitaxial layer 11 doped with a first conductivity type is formed on the front surface of the semiconductor substrate 10 .

[0070] Optionally, in this embodiment, the semiconductor substrate 10 may be an N+-doped silicon substrate, a germanium silicon substrate, a silicon carbide substrate, etc., and the epitaxial layer 11 may be a single crystal silicon epitaxial layer 11 of the first conductivity type. Before performing subsequent processes, the semiconductor substrate 10 may be cleaned first, for example, by sequentially using an organic solvent such as acetone and deionized water to remove pollutants on the surface of the semiconductor substrate 10, and then drying, or first using a dilute acid solution to remove the natural oxide layer on the surface of the semiconductor substrate 10, then using deionized water for cleaning, and finally drying, or using the aforementioned cleaning methods for multiple cleanings.

[0071] Further, such as Figure 2 As shown, a plurality of first trench units 12 are formed in the epitaxial layer 11. Specifically, a hard mask layer structure including silicon oxide-silicon nitride-silicon oxide stacked from bottom to top is first formed on the epitaxial layer 11, and the hard mask layer structure is used to define the regional position of the first trench unit 12 to be prepared through a photolithography process, thereby etching the required first trench unit 12. After the first trench unit 12 is formed, the residual hard mask layer structure is removed by including but not limited to an etching process. The specific implementation of the photolithography and etching process can be implemented by conventional means known to those skilled in the art, and is not specifically limited here.

[0072] like Figure 3 As shown, step S2 is performed to form a first high-k dielectric layer 13 on the inner wall of the first trench unit 12 and the surface of the epitaxial layer 11 .

[0073] Specifically, the first high-k dielectric layer 13 is formed by generally using a furnace tube and a CVD process to grow a certain thickness of the first high-k dielectric layer 13 on the surface of the epitaxial layer 11 and the inner wall of the first trench unit 12. Optionally, the material of the first high-k dielectric layer 13 in this embodiment includes one of Si3N4, Al2O3, HfO2, ZrO2, La2O3, TiO2 and Ti2O3.

[0074] like Figure 4 As shown, step S3 is performed to etch and remove the first high-k dielectric layer 13 at the bottom of the first trench unit 12 , and fill the first trench unit 12 with a first polysilicon layer 14 .

[0075] Specifically, the first high-k dielectric layer 13 can be etched to remove the first high-k dielectric layer 13 located at the bottom of the first trench unit 12 and expose the first conductive type single crystal silicon epitaxial layer 11, and then the first polycrystalline silicon layer 14 is deposited in the first trench unit 12 so that the first polycrystalline silicon layer 14 and the first high-k dielectric layer 13 have a flush surface.

[0076] like Figure 5 As shown, step S4 is performed to etch the first high-k dielectric layer 13 and the first polysilicon layer 14 in the first trench unit 12 to a first preset position.

[0077] Specifically, the first polysilicon layer 14 and the first high-k dielectric layer 13 are anisotropically etched so that the first high-k dielectric layer 13 and the first polysilicon layer 14 located in the first trench unit 12 have a first preset height, and then the first polysilicon layer 14 and the first high-k dielectric layer 13 are planarized, or the CMP process is directly used to make the first high-k dielectric layer 13 and the first polysilicon layer 14 located in the first trench unit 12 have the same height. Both of the above processing methods can make the first high-k dielectric layer 13 and the first polysilicon layer 14 have a flush surface, wherein, in this embodiment, the first high-k dielectric layer 13 includes a first high-k sub-dielectric layer 131 and a second high-k sub-dielectric layer 132, and the first high-k sub-dielectric layer 131 and the second high-k sub-dielectric layer 132 are symmetrically distributed about the first polysilicon layer 14. The planarization process may include mechanical grinding or CMP, which is not excessively limited here.

[0078] In the shielded gate trench MOSFET device mentioned in this embodiment, the direction from the source to the drain 24 is defined as the longitudinal direction, and the direction perpendicular to the longitudinal direction is defined as the lateral direction.

[0079] As an example, the ratio of the lateral width of the first polysilicon layer 14 to the lateral width of the first high-k sub-dielectric layer 131 is 0.2 to 5. For example, the ratio of the lateral width of the first polysilicon layer 14 to the lateral width of the first high-k sub-dielectric layer 131 is 0.2, 2.2, 4.4 or 5, which is not specifically limited here.

[0080] like Figure 6 As shown, step S5 is performed to form a first gate dielectric layer on the surfaces of the first high-k dielectric layer 13 and the first polysilicon layer 14, and the first gate dielectric layer is etched to form a second trench unit, and the bottom of the second trench unit exposes the first polysilicon layer 14.

[0081] Specifically, Figure 6, which is a schematic diagram of a cross-sectional structure after forming a first gate dielectric layer, wherein the method for forming the first gate dielectric layer includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0082] In addition, in order to ensure that the sidewalls and bottom of the formed second trench unit are clean and pollution-free, the second trench unit is usually formed by etching the first gate dielectric layer, the bottom of the second trench unit exposes the first polysilicon layer 14, and then the metal impurities in the second trench unit are cleaned and removed.

[0083] like Figure 7 As shown, step S6 is performed to fill the second polysilicon layer 16 in the second trench unit, and the second polysilicon layer 16 in the second trench unit and the first gate dielectric layer are etched to a second preset position.

[0084] The second polysilicon layer 16 fills the second trench unit and is in direct contact with the first polysilicon layer 14. The second polysilicon layer 16 and the first gate dielectric layer are anisotropically etched so that the first gate dielectric layer and the second polysilicon layer 16 in the second trench unit have a second preset height, and then the first gate dielectric layer and the second polysilicon layer 16 are planarized, or the CMP process is directly used to make the first gate dielectric layer and the second polysilicon layer 16 in the second trench unit have equal heights. Both of the above two processing methods can make the first gate dielectric layer and the second polysilicon layer 16 have a flush surface. In this embodiment, the first gate dielectric layer includes a first sub-gate dielectric layer 151 and a second sub-gate dielectric layer 152, and the first sub-gate dielectric layer 151 and the second sub-gate dielectric layer 152 are symmetrically distributed about the second polysilicon layer 16.

[0085] As an example, the ratio of the lateral width of the first polysilicon layer 14 to the lateral width of the second polysilicon layer 16 is 0.2 to 5. For example, the ratio of the lateral width of the first polysilicon layer 14 to the lateral width of the second polysilicon layer 16 is 0.2, 2.2, 4.4 or 5, which is not specifically limited here.

[0086] As an example, the ratio of the lateral width of the second polysilicon layer 16 to the lateral width of the first sub-gate dielectric layer 151 is 0.2 to 5. For example, the ratio of the lateral width of the second polysilicon layer 16 to the lateral width of the first sub-gate dielectric layer 151 is 0.2, 2.2, 4.4 or 5, which is not specifically limited here.

[0087] As an example, the ratio of the longitudinal height of the first high-k dielectric layer 13 to the longitudinal height of the second polysilicon layer 16 is 0.25 to 4. For example, the ratio of the longitudinal height of the first high-k dielectric layer 13 to the longitudinal height of the second polysilicon layer 16 is 0.25, 2, 3 or 4, and no specific limitation is given here.

[0088] like Figure 8 As shown, step S7 is executed to form a trench gate structure on the surface of the first gate dielectric layer and the second polysilicon layer 16, ion implantation is performed on the upper surface of the epitaxial layer 11 on the side of the first trench unit 12 to form a body region 18, and ion implantation is performed on the upper surface of the body region 18 to form a source region 19.

[0089] Specifically, a trench gate structure is formed on the surface of the first gate dielectric layer and the second polysilicon layer 16 in the first trench unit 12, and the trench gate structure includes a second gate dielectric layer 171 and a third polysilicon gate, wherein the third polysilicon gate is isolated from the second polysilicon layer 16 by the second gate dielectric layer 171, and the second gate dielectric layer 171 covers the upper surface of the third polysilicon gate and is flush with the source region 19.

[0090] Specifically, forming a trench gate structure is a conventional technical means well known to those skilled in the art, which will not be described in detail here.

[0091] Specifically, the body region 18 includes a body region 18 of the second conductivity type, and a method for forming the body region 18 of the second conductivity type includes ion implantation and high temperature annealing. For example, ion implantation can be used to implant second conductivity type impurities into the top of the first conductivity type doped epitaxial layer 11 on the side of the first trench unit 12, and a high temperature annealing process is performed to invert the top of the first conductivity type doped epitaxial layer 11 into the second conductivity type body region 18. The body region 18 is isolated from the third polysilicon gate by the second gate dielectric layer 171.

[0092] Specifically, the source region 19 includes a first conductive type source region 19, and the method for forming the first conductive type source region 19 includes ion implantation and high temperature annealing. For example, the first conductive type impurity can be implanted into the top of the ion implantation pair, and a high temperature annealing process is performed to make the top of the second conductive type body region 18 inverted into the first conductive type source region 19 again, and the finally formed first conductive type source region 19 has a flush surface with the second gate dielectric layer 171. The source region 19 is isolated from the third polysilicon gate by the second gate dielectric layer 171.

[0093] like Fig. 9As shown, step S8 is performed to form an interlayer dielectric layer 20 on the source region 19, and the interlayer dielectric layer 20, the source region 19 and the body region 18 are etched to form a plurality of first contact holes 211 that penetrate the interlayer dielectric layer 20 and the source region 19 and expose the body region 18.

[0094] Specifically, an interlayer dielectric layer 20 is formed on the source region 19 by a PECVD process. Optionally, the interlayer dielectric layer 20 includes one or a stacked combination of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer. Preferably, in this embodiment, the interlayer dielectric layer 20 includes a silicon oxide layer located on the source region 19 and a silicon phosphate glass layer located on the fifth silicon oxide layer.

[0095] Further, an electrode contact hole is etched in the interlayer dielectric layer 20 to form a first contact hole 211 that penetrates the interlayer dielectric layer 20 and the source region 19 and exposes the body region 18 at the bottom. It should be noted that in the actual process, a second contact hole (not shown in the figure) that exposes the trench gate structure is also formed, but the first contact hole 211 and the second contact hole do not necessarily appear in the same cross section at the same time. Fig. 9 It is only used as a simplified structural diagram.

[0096] Specifically, a photoresist masking layer is formed on the interlayer dielectric layer 20, and the photoresist masking layer is exposed using a mask to define a first contact hole 211 area in the developed photoresist masking layer; a dry etching process is performed through the interlayer dielectric layer 20 and the source region 19 to form a first contact hole 211, and the bottom of the first contact hole 211 exposes the body region 18.

[0097] like Fig.10 As shown, step S9 is performed to deposit metal on the interlayer dielectric layer 20 to form a front metal layer 22 , and the front metal layer 22 fills the first contact hole 211 .

[0098] Specifically, in order to ensure that the body region 18 in the first contact hole 211 has a good metal connection with the outside, the present embodiment uses metal to fill the first contact hole 211, and thins it to form a metal connection column. In order to avoid metallization of the third polysilicon layer 172, a chemical vapor deposition process can be used to form a barrier layer covering the inner wall of the first contact hole 211. Preferably, the material of the barrier layer includes Ti / TiN, and the material of the metal includes tungsten. Further, as Fig.10 As shown, the front metal layer 22 is formed on the surface of the interlayer dielectric layer 20 and is connected to the metal connection column in the first contact hole 211 .

[0099] As an example, Fig.11As shown, after forming the front metal layer 22, it also includes the steps of forming a passivation layer 23, etching the passivation layer 23 to form a metal lead and forming a drain 24, wherein the passivation layer 23 is located on the surface of the front metal layer 22, and the drain 24 is electrically connected to the back side of the semiconductor substrate 10.

[0100] Optionally, the passivation layer 23 can be a single-layer or multi-layer stacked structure. For example, the passivation layer 23 can include only a silicon nitride layer, or it can include a silicon nitride layer and a polymer layer located on the silicon nitride layer. Preferably, in this embodiment, the passivation layer 23 includes a silicon nitride layer and a polyimide layer. The silicon nitride layer can be formed by a chemical vapor deposition process, and the polyimide layer can be formed by a spin coating process, so that the passivation layer 23 can better protect the underlying structure.

[0101] Specifically, a drain 24 is formed in the MOS device, wherein the drain 24 is located on the back side of the semiconductor substrate 10.

[0102] The method for preparing a shielded gate trench MOSFET device of the present invention at least comprises: forming a first trench unit 12 on a substrate having an epitaxial layer 11, forming a first high-k dielectric layer 13 and a first polysilicon layer 14 in the first trench unit 12, and forming a second polysilicon layer 16 surrounded by a first gate dielectric layer above the first polysilicon layer 14, wherein the second polysilicon layer 16 is directly in contact with the first polysilicon layer 14, the first high-k dielectric layer 13 is symmetrically distributed about the first polysilicon layer 14, and the first polysilicon layer 14 is directly in contact with the epitaxial layer 11. A Schottky barrier diode is formed, and then a trench gate structure is formed above the second polysilicon layer 16, so that the Schottky barrier diode is finally connected in parallel with the body diode region of the MOS device. The Schottky barrier diode is used to quickly extract minority carriers in the reverse recovery process, thereby reducing the reverse recovery current and reverse recovery time, thereby reducing the reverse recovery loss of the device. At the same time, the first high-k dielectric layer 13 is used to modulate the electric field, thereby reducing the electric field near the bottom of the first polysilicon layer 14, thereby increasing the device breakdown voltage, improving the device drain / source leakage, and improving the device performance.

[0103] Example 2

[0104] This embodiment also provides a shielded gate trench MOSFET device, which is manufactured by the manufacturing method described in the first embodiment or other suitable similar methods. The manufacturing method, material and structure of the shielded gate trench MOSFET device can all be referred to in the first embodiment. Specifically, since the shielded gate trench MOSFET device structure can be an N-type device or a P-type device, in this embodiment, an N-type device is used as an example for detailed description, see Fig.11, which is a schematic diagram of the structure of the shielded gate trench MOSFET device, wherein the shielded gate trench MOSFET device includes:

[0105] A semiconductor substrate 10 having an epitaxial layer 11;

[0106] A first trench unit 12 is located in the epitaxial layer 11;

[0107] A first high-k dielectric layer 13, located on the inner wall of the first trench unit 12, the first high-k dielectric layer 13 includes a first high-k sub-dielectric layer 131 and a second high-k sub-dielectric layer 132, and the height of the first high-k dielectric layer 13 is lower than the height of the first trench unit 12;

[0108] A first polysilicon layer 14 is located between the first high-k dielectric layer 131 and the second high-k dielectric layer 132 and fills the first trench unit 12 , and has a flush surface with the first high-k dielectric layer 13 ;

[0109] a first gate dielectric layer, wherein the first gate dielectric layer is located in the first trench unit 12 and on the first polysilicon layer 14, a second trench unit is formed in the first gate dielectric layer, and the first polysilicon layer 14 is exposed at the bottom of the second trench unit;

[0110] A second polysilicon layer 16, filling the second trench unit and being in contact with the first polysilicon layer 14, and having a flush surface with the first gate dielectric layer;

[0111] A trench gate structure, wherein the trench gate structure is located on the second polysilicon layer 16 and the first gate dielectric layer, and the upper surface of the trench gate structure is flush with the source region 19;

[0112] a body region 18 , located on the upper surface of the epitaxial layer 11 and adjacent to the first trench unit 12 , wherein the lower surface of the body region 18 is higher than the second polysilicon layer 16 ;

[0113] A source region 19, located on the upper surface of the body region 18;

[0114] An interlayer dielectric layer 20 is located on the upper surface of the source region 19, and the interlayer dielectric layer 20 has a first contact hole 211 exposing the body region 18;

[0115] The front metal layer 22 is located on the interlayer dielectric layer 20 and fills the first contact hole 211 .

[0116] As an example, the trench gate structure includes a second gate dielectric layer 171 and a third polysilicon gate, wherein the third polysilicon gate is isolated from the source region 19, the body region 18 and the second polysilicon layer 16 by the second gate dielectric layer 171, and the second gate dielectric layer 171 covers the upper surface of the third polysilicon gate and is flush with the source region 19.

[0117] In the structure of the shielded gate trench MOSFET device in the present embodiment 2, a Schottky barrier diode is formed by forming a first polysilicon layer 14 in direct contact with the first conductive type epitaxial layer 11 in the first trench, and finally the Schottky barrier diode is connected in parallel with the body diode region of the MOS device. The Schottky barrier diode is used to quickly extract minority carriers in the reverse recovery process, thereby reducing the reverse recovery current and reverse recovery time, thereby reducing the reverse recovery loss of the device. At the same time, the first high-k dielectric layer 13 symmetrically distributed on both sides of the first polysilicon layer 14 has a modulation effect on the electric field, thereby reducing the electric field near the first polysilicon layer 14, increasing the device breakdown voltage, and improving the device drain / source leakage.

[0118] In summary, the shielded gate trench MOSFET device and its preparation method of the present invention form a first trench unit on a substrate having an epitaxial layer, form a first high-k dielectric layer and a first polysilicon layer in the first trench unit, and form a second polysilicon layer surrounded by a first gate dielectric layer above the first polysilicon layer, the second polysilicon layer is directly contacted and connected to the first polysilicon layer, the first high-k dielectric layer is symmetrically distributed about the first polysilicon layer, and the first polysilicon layer is directly contacted with the epitaxial layer to form a Schottky barrier diode, and then a trench gate structure is formed above the second polysilicon layer, so that the Schottky barrier diode is finally connected in parallel with the body diode region of the MOS device, and the Schottky barrier diode is used to quickly extract minority carriers in the reverse recovery process, thereby reducing the reverse recovery current and reverse recovery time, thereby reducing the reverse recovery loss of the device, and at the same time, the modulation effect of the first high-k dielectric layer on the electric field is used to reduce the electric field near the bottom of the first polysilicon layer, thereby increasing the device breakdown voltage, improving the device drain / source leakage, and ultimately improving the device performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0119] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a shielded gate trench MOSFET device, characterized in that: The preparation method comprises the following steps: Providing a semiconductor substrate having an epitaxial layer, and forming a plurality of first trench units in the epitaxial layer; forming a first high-k dielectric layer on the inner wall of the first trench unit and the surface of the epitaxial layer; Etching and removing the first high-k dielectric layer at the bottom of the first trench unit, and filling the first polysilicon layer in the first trench unit; Etching the first high-k dielectric layer and the first polysilicon layer in the first trench unit to a first preset position; forming a first gate dielectric layer on the surfaces of the first high-k dielectric layer and the first polysilicon layer, etching the first gate dielectric layer to form a second trench unit, wherein the first polysilicon layer is exposed at the bottom of the second trench unit; Filling a second polysilicon layer in the second trench unit, and etching the second polysilicon layer in the second trench unit and the first gate dielectric layer to a second preset position; Forming a trench gate structure at the first gate dielectric layer and the second polysilicon layer, performing ion implantation on the upper surface of the epitaxial layer at the side of the first trench unit to form a body region, and performing ion implantation on the upper surface of the body region to form a source region; forming an interlayer dielectric layer on the source region, and etching the interlayer dielectric layer, the source region and the body region to form a plurality of first contact holes penetrating the interlayer dielectric layer and the source region and exposing the body region; A metal is deposited on the interlayer dielectric layer to form a front metal layer, and the front metal layer fills the first contact hole.

2. The method for preparing a shielded gate trench MOSFET device according to claim 1, characterized in that: After forming the front metal layer, the method also includes forming a passivation layer, etching the passivation layer to form a metal lead, and forming a drain electrode, wherein the passivation layer is located on the surface of the front metal layer, and the drain electrode is electrically connected to the back side of the semiconductor substrate.

3. The method for preparing a shielded gate trench MOSFET device according to claim 1, characterized in that: The first high-k dielectric layer and the first polysilicon layer have flush surfaces. The first high-k dielectric layer includes a first high-k sub-dielectric layer and a second high-k sub-dielectric layer. The first high-k sub-dielectric layer and the second high-k sub-dielectric layer are symmetrically distributed with respect to the first polysilicon layer.

4. The method for preparing a shielded gate trench MOSFET device according to claim 3, characterized in that: The ratio of the lateral width of the first polysilicon layer to the lateral width of the first high-k dielectric layer is 0.2-5, and the ratio of the lateral width of the first polysilicon layer to the lateral width of the second polysilicon layer is 0.2-5.

5. The method for preparing a shielded gate trench MOSFET device according to claim 1, characterized in that: The first gate dielectric layer and the second polysilicon layer have flush surfaces, the first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer, and the first sub-gate dielectric layer and the second sub-gate dielectric layer are symmetrically distributed about the second polysilicon layer.

6. The method for preparing a shielded gate trench MOSFET device according to claim 5, characterized in that: The ratio of the lateral width of the second polysilicon layer to the lateral width of the first sub-gate dielectric layer is 0.2-5.

7. The method for preparing a shielded gate trench MOSFET device according to claim 1, characterized in that: The ratio of the longitudinal height of the first high-k dielectric layer to the longitudinal height of the second polysilicon layer is 0.25-4.

8. A shielded gate trench MOSFET device, characterized in that: include: A semiconductor substrate having an epitaxial layer; A first trench unit is located in the epitaxial layer; A first high-k dielectric layer is located on an inner wall of the first trench unit, the first high-k dielectric layer includes a first high-k sub-dielectric layer and a second high-k sub-dielectric layer, and a height of the first high-k dielectric layer is lower than a height of the first trench unit; A first polysilicon layer, located between the first high-k dielectric layer and the second high-k dielectric layer and filling the first trench unit, and having a flush surface with the first high-k dielectric layer; a first gate dielectric layer, wherein the first gate dielectric layer is located in the first trench unit and on the first polysilicon layer, a second trench unit is formed in the first gate dielectric layer, and the first polysilicon layer is exposed at the bottom of the second trench unit; A second polysilicon layer, filling the second trench unit and being in contact with the first polysilicon layer, and having a surface flush with the first gate dielectric layer; a trench gate structure, wherein the trench gate structure is located on the second polysilicon layer and the first gate dielectric layer, and an upper surface of the trench gate structure is flush with the source region; a body region, located on an upper surface of the epitaxial layer and adjacent to the first trench unit, wherein a lower surface of the body region is higher than the second polysilicon layer; A source region, located on an upper surface of the body region; an interlayer dielectric layer, located on an upper surface of the source region, and having a first contact hole exposing the body region; A front metal layer is located on the interlayer dielectric layer and fills the first contact hole.

9. The shielded gate trench MOSFET device according to claim 8, characterized in that: The trench gate structure includes a second gate dielectric layer and a third polysilicon gate, wherein the third polysilicon gate is isolated from the source region, the body region and the second polysilicon layer by the second gate dielectric layer, and the second gate dielectric layer covers the upper surface of the third polysilicon gate and is flush with the source region.

10. The shielded gate trench MOSFET device according to claim 8, characterized in that: The shielded gate trench MOSFET device includes a P-type MOSFET device or an N-type MOSFET device.

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