Thin film transistor and preparation method thereof

Abstract

The invention discloses a thin film transistor and a preparation method thereof, and relates to the field of transistor preparation, and the preparation method comprises the steps: depositing a first metal electrode layer on a driving backboard, and etching the first metal electrode layer to obtain a source-drain metal electrode; sequentially depositing a Spacer layer material and a second metal electrode layer on the source-drain metal electrode; etching the second metal electrode layer to obtain an initial drain-source metal electrode, and etching the Spacer layer material to obtain a Spacer layer; etching the initial drain-source metal electrode again to obtain a final drain-source metal electrode; depositing an active layer material on the source-drain metal electrode, the final drain-source metal electrode and the Spacer layer, and etching to obtain an active layer; depositing a gate insulating layer on the source-drain metal electrode, the active layer and the final drain-source metal electrode, and etching to obtain a contact hole pattern; and depositing a third metal electrode layer on the gate insulating layer and etching to obtain a gate electrode, thereby completing the preparation. The channel length-width ratio of the thin film transistor device can be increased.

Description

Technical Field

[0001] The present application relates to the field of transistor preparation, and in particular to a thin film transistor and a preparation method thereof. Background Art

[0002] Thin Film Transistors (TFT) serve as the backplane driving module in the display screen, controlling the display of the Organic Light Emitting Diode (OLED) or Liquid Crystal Display (LCD) on the pixel electrode. It determines the driving performance and minimum size of the device and is one of the most important components in the display panel.

[0003] At present, the channel length L of the vertical channel thin film transistor device is usually controlled by adjusting the thickness of the Spacer layer. However, in order to ensure the process beat and device characteristics, the thickness variation range of the Spacer layer is limited; and the channel width W of the device can be adjusted over a large range through the photolithography process. Therefore, the vertical channel device currently prepared can easily achieve a large channel width-to-length ratio (i.e., channel width / channel length W / L).

[0004] However, in the relevant pixel driving circuit, the thin film transistors of the control device are divided into two categories, namely the switch tube and the drive tube. Among them, the switch tube mainly realizes the rapid switching of the current, so a large W / L device is required; in order to achieve more display grayscales, the drive tube needs to be designed as a device with a large channel aspect ratio (i.e., channel length / channel width L / W). Under the existing photolithography process conditions, when W is the smallest size, how to design a large channel length L is the current technical problem. Therefore, how to increase the channel length L of the thin film transistor device and prepare a large L / W device has become a problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the present application is to provide a thin film transistor and a method for manufacturing the same, which can increase the channel aspect ratio of the thin film transistor device.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a method for preparing a thin film transistor, comprising:

[0008] Depositing a first metal electrode layer on the driving backplane, and etching the first metal electrode layer from a first end to obtain source and drain metal electrodes;

[0009] Depositing a Spacer layer material on the source-drain metal electrode, and depositing a second metal electrode layer on the Spacer layer material;

[0010] Etching the second metal electrode layer from the first end to obtain an initial drain-source metal electrode;

[0011] Using the initial drain-source metal electrode as a hard mask layer of the Spacer layer material, etching the Spacer layer material from the first end to obtain a Spacer layer; the horizontal distance between the etching end side of the initial drain-source metal electrode and the etching end side of the Spacer layer is 0;

[0012] The initial drain-source metal electrode is further etched from the first end to obtain a final drain-source metal electrode; the horizontal distance between the etched end side of the final drain-source metal electrode and the etched end side of the Spacer layer is greater than 0;

[0013] Depositing active layer materials on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer, and etching the active layer materials to obtain an active layer; the active layer covers a portion of the top surface of the source-drain metal electrodes, the Spacer layer and the etched end side surface of the final drain-source metal electrodes;

[0014] Depositing a gate insulating layer on the source-drain metal electrode, the active layer and the final drain-source metal electrode, and etching the gate insulating layer to form a contact hole pattern on the final drain-source metal electrode;

[0015] A third metal electrode layer is deposited on the gate insulating layer, and the third metal electrode layer is etched to obtain a gate electrode, thereby completing the preparation of a thin film transistor.

[0016] Optionally, etching the second metal electrode layer from the first end to obtain an initial drain-source metal electrode specifically includes: performing a patterning process on the second metal electrode layer, and etching from the first end using a first wet etching process to form an initial drain-source metal electrode;

[0017] The initial drain-source metal electrode is etched again from the first end to obtain the final drain-source metal electrode, specifically including: patterning the initial drain-source metal electrode, and etching from the first end using a second wet etching process to form the final drain-source metal electrode.

[0018] Optionally, depositing a first metal electrode layer on the driving backplane specifically includes: depositing the first metal electrode layer on the driving backplane using a magnetron sputtering method under a first set deposition condition or depositing the first metal electrode layer on the driving backplane using an atomic layer deposition method;

[0019] Depositing a second metal electrode layer on the Spacer layer material specifically includes: depositing the second metal electrode layer on the Spacer layer material by magnetron sputtering under a first set deposition condition or depositing the second metal electrode layer on the Spacer layer material by atomic layer deposition;

[0020] Depositing a third metal electrode layer on the gate insulating layer specifically includes: depositing the third metal electrode layer on the gate insulating layer by magnetron sputtering under first set deposition conditions or depositing the third metal electrode layer on the gate insulating layer by atomic layer deposition.

[0021] Optionally, depositing a Spacer layer material on the source-drain metal electrode specifically includes: depositing the Spacer layer material on the source-drain metal electrode using a plasma enhanced chemical vapor deposition method under a second set deposition condition or depositing the Spacer layer material on the source-drain metal electrode using an atomic layer deposition method;

[0022] Depositing a gate insulating layer on the source-drain metal electrode, the active layer and the final drain-source metal electrode specifically includes: using plasma enhanced chemical vapor deposition to deposit a gate insulating layer on the source-drain metal electrode, the active layer and the final drain-source metal electrode under a second set deposition condition.

[0023] Optionally, active layer materials are deposited on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer, specifically including: depositing active layer materials on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer using magnetron sputtering under a third set deposition condition, or depositing active layer materials on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer using atomic layer deposition.

[0024] Optionally, the first set deposition conditions include: a deposition power range of 0.1KW to 1.0KW, a working pressure range of 10 -6 Pa~10 -4 Pa and deposition temperature from room temperature to 350°C.

[0025] Optionally, the second set deposition conditions include: a deposition power range of 0.1 KW to 2.0 KW, a working gas pressure range of 0.5 Pa to 5 Pa, and a deposition temperature of 80° C. to 350° C.

[0026] Optionally, the third set deposition condition includes: a deposition power range of 0.1KW to 2.0KW, a working pressure range of 10 -6 Pa~10 -4 Pa and deposition temperature from room temperature to 350°C.

[0027] Optionally, the thickness range of the first metal electrode layer, the second metal electrode layer and the third metal electrode layer is 20nm to 1000nm; the thickness range of the spacer layer material is 50nm to 2000nm; the thickness range of the active layer material is 10nm to 200nm.

[0028] In a second aspect, the present application provides a thin film transistor, which is manufactured using the above-mentioned method for manufacturing a thin film transistor.

[0029] According to the specific embodiments provided in this application, this application has the following technical effects:

[0030] The present application provides a thin film transistor and a preparation method thereof. During the preparation process, the second metal electrode layer is preliminarily etched to obtain an initial drain-source metal electrode. At this time, the length of the etched end side of the Spacer layer is the length of the device channel, which is consistent with the channel length of a traditional channel device. On this basis, the initial drain-source metal electrode is etched again to obtain a final drain-source metal electrode. The horizontal distance between the etched end side of the final drain-source metal electrode and the etched end side of the Spacer layer is greater than 0, and the horizontal distance between the etched end side of the final drain-source metal electrode and the etched end side of the Spacer layer is added as the length of the device channel. Therefore, the channel length of the thin film transistor prepared in the present application is determined by two parts: the length of the etched end side of the Spacer layer and the horizontal distance between the etched end side of the final drain-source metal electrode and the etched end side of the Spacer layer. Through the combination of these two parts, the channel length of the entire device is made longer, and the channel aspect ratio of the thin film transistor device is increased, thereby manufacturing a large L / W channel device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 is a schematic structural diagram of a conventional vertical channel thin film transistor device;

[0033] Figure 2 A flow chart of a method for preparing a thin film transistor provided in one embodiment of the present application;

[0034] Figure 3 A schematic diagram of the structure of a thin film transistor provided in one embodiment of the present application;

[0035] Figure 4 A schematic diagram of a T1C pixel driving circuit for a large W / L vertical device and a large L / W vertical device provided in an embodiment of the present application that are prepared simultaneously and compatibly;

[0036] Figure 5 A schematic diagram of a T1C pixel driving structure of an embodiment 2 of the present application, which provides a large W / L vertical device and a large L / W vertical device that are prepared simultaneously and compatibly.

[0037] Figure numerals: driving backplane—100, source-drain metal electrodes—201, spacer layer—301, drain-source metal electrodes—401, final drain-source metal electrodes—402, active layer—501, gate insulating layer—600, contact hole pattern—601, gate electrode—701. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0040] Conventional vertical channel thin film transistor devices such as Figure 1 As shown, at present, the preparation process of the vertical channel thin film transistor device is as follows: (1) depositing a first metal electrode layer on a clean driving backplane 100 (such as a glass substrate), and forming a source-drain metal electrode 201 through a patterning process such as photolithography and etching; (2) depositing a layer of spacer layer material, and then depositing a second metal electrode layer, firstly etching the second metal electrode layer through a patterning process such as photolithography and etching to form a drain-source metal electrode 401, and then etching the second metal electrode layer through a photolithography and dry etching process. The drain-source metal electrode formed after etching is a hard mask, and the Spacer layer material is dry-etched. The Spacer layer 301 is etched into a vertical structure as the vertical channel surface of the device; (3) the active layer material is deposited, and an active layer 501 is formed through patterning processes such as photolithography and etching; (4) the gate insulating layer 600 is deposited, and a contact hole pattern 601 is prepared through patterning processes such as photolithography and dry etching; (5) the third metal electrode layer is deposited, and a gate electrode 701 is prepared through patterning processes such as photolithography and etching.

[0041] The length of the device channel prepared by the above preparation method is the length of the etched end side of the Spacer layer 301. If the angle between the etched end side and the horizontal plane is 90 degrees, the length of the vertical channel is the thickness of the Spacer layer 301.

[0042] In order to increase the channel aspect ratio of a thin film transistor device, thereby manufacturing a channel device with a large L / W, the present application provides a method for preparing a thin film transistor, such as Figure 2 As shown, according to Figure 2 The thin film transistor device prepared by the preparation method shown in FIG. Figure 3 shown.

[0043] See also Figure 2 The method for preparing a thin film transistor provided in the present application includes the following steps.

[0044] Step S1 : depositing a first metal electrode layer on the driving backplane 100 , and etching the first metal electrode layer from a first end to obtain a source-drain metal electrode 201 .

[0045] The driving backplane 100 may be a TFT driving backplane.

[0046] Step S2, depositing a spacer layer material on the source-drain metal electrode 201, and depositing a second metal electrode layer on the spacer layer material.

[0047] Step S3, etching the second metal electrode layer from the first end to obtain an initial drain-source metal electrode. Figure 1 The drain-source metal electrode 401 is shown.

[0048] Step S4 , using the initial drain-source metal electrode as a hard mask layer of the Spacer layer material, etching the Spacer layer material from the first end to obtain the Spacer layer 301 .

[0049] The horizontal distance between the etched end side surface of the initial drain-source metal electrode and the etched end side surface of the Spacer layer 301 is 0.

[0050] Step S5 , etching the initial drain-source metal electrode again from the first end to obtain the final drain-source metal electrode 402 .

[0051] The horizontal distance between the etched end side surface of the final drain-source metal electrode 402 and the etched end side surface of the Spacer layer 301 is greater than 0.

[0052] Step S6 , depositing active layer materials on the source-drain metal electrodes 201 , the final drain-source metal electrodes 402 and the spacer layer 301 , and etching the active layer materials to obtain an active layer 501 .

[0053] The active layer 501 covers a portion of the top surface of the source-drain metal electrode 201 , the spacer layer 301 , and the etched end side surface of the final drain-source metal electrode 402 .

[0054] Step S7 , depositing a gate insulating layer 600 on the source-drain metal electrode 201 , the active layer 501 and the final drain-source metal electrode 402 , and etching the gate insulating layer 600 to form a contact hole pattern 601 on the final drain-source metal electrode 402 .

[0055] Step S8, depositing a third metal electrode layer on the gate insulating layer 600, and etching the third metal electrode layer to obtain a gate electrode 701, thereby completing the preparation of the thin film transistor.

[0056] The channel length of the thin film transistor prepared by implementing the above steps S1 to S8 is determined by two parts: the length of the etched end side of the Spacer layer 301 and the horizontal distance between the etched end side of the final drain-source metal electrode 402 and the etched end side of the Spacer layer 301. Through the combination of these two parts, the channel length of the entire device is made longer, and the channel aspect ratio of the thin film transistor device is increased, thereby manufacturing a large L / W channel device.

[0057] In this embodiment, the horizontal distance between the etched end side of the final drain-source metal electrode 402 and the etched end side of the Spacer layer 301 is determined by the functional requirements of the circuit structure. Devices with different aspect ratios have different uses. Different horizontal distances of etching are performed during preparation according to the required uses to meet different aspect ratios.

[0058] In an exemplary embodiment, step S3 specifically includes: performing a patterning process on the second metal electrode layer, and etching from the first end portion using a first wet etching process to form an initial drain-source metal electrode.

[0059] Step S5 specifically includes: performing a patterning process on the initial drain-source metal electrode, and etching from the first end portion using a second wet etching process to form a final drain-source metal electrode 402 .

[0060] In the first wet etching process and the second wet etching process in this embodiment, a metal etching solution corresponding to the second metal electrode layer well known in the art is used, the etching process temperature is from room temperature to 60° C., and the etching time is from 10 s to 300 s.

[0061] In another exemplary embodiment of the present application, step S1 specifically includes: depositing a first metal electrode layer on the driving backplane 100 by magnetron sputtering with a first set deposition condition or depositing a first metal electrode layer on the driving backplane 100 by atomic layer deposition. The first set deposition condition includes: a deposition power range of 0.1KW to 1.0KW, a working pressure range of 10 -6 Pa~10 -4 Pa and deposition temperature from room temperature to 350°C.

[0062] Step S2 specifically includes: depositing a second metal electrode layer on the Spacer layer material using a magnetron sputtering method under a first set deposition condition or depositing a second metal electrode layer on the Spacer layer material using an atomic layer deposition method.

[0063] Step S8 specifically includes: depositing a third metal electrode layer on the gate insulating layer 600 by magnetron sputtering under first set deposition conditions or depositing the third metal electrode layer on the gate insulating layer 600 by atomic layer deposition.

[0064] In this embodiment, the thickness of the first metal electrode layer, the second metal electrode layer and the third metal electrode layer are all in the range of 20nm to 1000nm. The first metal electrode layer, the second metal electrode layer and the third metal electrode layer can be made of one of aluminum (Al), molybdenum (Mo), silver (Ag), copper (Cu), titanium (Ti), gold (Au), indium tin oxide (ITO) or a stack of two or more of these materials.

[0065] In another exemplary embodiment of the present application, step S2 specifically includes: using plasma enhanced chemical vapor deposition to deposit a Spacer layer material on the source-drain metal electrode 201 under a second set deposition condition or using atomic layer deposition to deposit a Spacer layer material on the source-drain metal electrode 201. The second set deposition condition includes: a deposition power range of 0.1KW to 2.0KW, a working gas pressure range of 0.5Pa to 5Pa, and a deposition temperature of 80°C to 350°C.

[0066] Step S7 specifically includes: depositing a gate insulating layer 600 on the source-drain metal electrode 201 , the active layer 501 and the final drain-source metal electrode 402 by plasma enhanced chemical vapor deposition under a second set deposition condition.

[0067] In this embodiment, when plasma enhanced chemical vapor deposition is used for preparation, the materials of the spacer layer and the gate insulating layer 600 can be selected from SiOx, SiNx or SiOx / SiNx stacked films, wherein there is no special requirement for the value of x, and silicon oxide or silicon nitride well known in the art can be used.

[0068] When the atomic layer deposition method is used for preparation, the spacer layer material is selected from high-K dielectric materials such as Al2O3 and HfO2. The thickness of the spacer layer material ranges from 50nm to 2000nm.

[0069] In another exemplary embodiment of the present application, step S6 specifically includes: depositing active layer materials on the source-drain metal electrode 201, the final drain-source metal electrode 402 and the Spacer layer 301 by magnetron sputtering with a third set deposition condition, or depositing active layer materials on the source-drain metal electrode 201, the final drain-source metal electrode 402 and the Spacer layer 301 by atomic layer deposition. The third set deposition condition includes: a deposition power range of 0.1KW to 2.0KW, a working pressure range of 10 -6 Pa~10 -4 Pa and deposition temperature range from room temperature to 350° C. The thickness of the active layer material ranges from 10 nm to 200 nm. When the active layer 501 is annealed, the annealing temperature ranges from 150° C. to 500° C.

[0070] The working process of the thin film transistor prepared in the above embodiment is as follows: by loading the source-drain voltage on the designed and manufactured vertical structure source-drain metal electrode 201, loading the drain-source voltage on the final drain-source metal electrode 402, loading the gate voltage on the gate electrode 701, the direction of the device channel active layer 501 is perpendicular to the driving backplane 100; at the same time, the length L of the device channel is determined by two parts: the first part is the length of the bevel of the Spacer layer 301 formed by dry etching (that is, the length of the etching end side of the Spacer layer 301), which is consistent with the channel length of the traditional vertical channel device, and the second part is the distance between the final drain-source metal electrode 402 and the bevel edge of the Spacer layer 301 formed by dry etching (that is, the horizontal distance between the etching end side of the final drain-source metal electrode 402 and the etching end side of the Spacer layer 301). Through the combination of the two parts, the channel length of the entire device is made longer, thereby manufacturing a vertical channel device with a large L / W.

[0071] Based on the same inventive concept, the present application also provides a thin film transistor. The thin film transistor is prepared by the thin film transistor preparation method of the above embodiment. The structure of the thin film transistor is as follows: Figure 3 shown.

[0072] A preparation process of this embodiment can be described as follows:

[0073] 1. Clean the driving backplane 100 and deposit a first metal electrode layer in the driving backplane 100 , and manufacture source and drain metal electrodes 201 through patterning processes such as photolithography and etching.

[0074] 2. Deposit a spacer layer material and a second metal electrode layer on the source-drain metal electrode 201, pattern the second metal electrode layer, and form initial drain-source metal electrodes using a first wet etching process.

[0075] 3. Using the initial drain-source metal electrodes as the hard mask layer of the spacer layer material, a spacer layer 301 is formed by dry etching.

[0076] 4. The initial drain-source metal electrode is patterned and subjected to a second wet etching process to form the final drain-source metal electrode 402 .

[0077] 5. A layer of active layer material is deposited on the entire surface of the source-drain metal electrode 201 , the final drain-source metal electrode 402 and the spacer layer 301 , and the active layer 501 of the device is formed by patterning processes such as photolithography and etching.

[0078] 6. A gate insulating layer 600 is deposited on the entire surface of the active layer 501 ; a contact hole pattern 601 is produced on the final drain-source metal electrode 402 through patterning processes such as photolithography and etching.

[0079] 7. A third metal electrode layer is deposited on the gate insulating layer 600 , and a gate electrode 701 of the device is formed by patterning processes such as photolithography and etching.

[0080] 8. The first metal electrode layer, the second metal electrode layer and the third metal electrode layer can be prepared by magnetron sputtering or by atomic layer deposition.

[0081] 9. The above-mentioned spacer layer material and gate insulating layer 600 can be prepared by plasma enhanced chemical vapor deposition. The spacer layer material can also be prepared by atomic layer deposition.

[0082] 10. The above active layer material can be deposited and prepared by magnetron sputtering or atomic layer deposition.

[0083] 11. A vertical thin film transistor is prepared.

[0084] The present application controls the channel length L of the device by adjusting the distance between the drain-source metal electrode formed by the second metal electrode layer in the vertical channel thin film transistor and the vertical channel surface etched by the spacer layer 301 through structural design, and prepares a large L / W device. At the same time, this structural design can also easily realize the interconnection of devices with different aspect ratios.

[0085] Figure 4 The embodiment 2T1C pixel driving circuit of the large W / L vertical device and the large L / W vertical device prepared simultaneously and compatibly is shown, Figure 5 An embodiment 2T1C pixel driving structure of a large W / L vertical device and a large L / W vertical device that are prepared simultaneously and compatibly is shown. Figure 4 and Figure 5 The interconnection between the traditional vertical channel thin film transistor device and the thin film transistor of the present application is realized. Figure 4 It is a classic 2T1C structure, interconnected by two transistors T1, T2 and a capacitor C. In order to distinguish between the conventional vertical channel thin film transistor device and the thin film transistor of the present application, (a) and (b) are used for marking, (a) corresponds to the structure in the conventional vertical channel thin film transistor device, (b) corresponds to the structure in the thin film transistor of the present application, for example, the source and drain metal electrodes 201(a) in the conventional vertical channel thin film transistor device, the source and drain metal electrodes 201(b) in the thin film transistor of the present application, the gate electrode 701(a) in the conventional vertical channel thin film transistor device, and the gate electrode 701(b) in the thin film transistor of the present application.

[0086] This embodiment can overcome the shortcomings of the current technology and use the same process to realize the preparation of large W / L vertical devices and large L / W vertical devices, solving the technical problem that the existing vertical device technology cannot realize large L / W vertical devices, further optimizing the area of ​​pixel driving circuit devices, and significantly improving the resolution of the display panel.

[0087] The present application can be applied to flat panel display technology, especially a method for manufacturing a vertical channel thin film crystal display panel. Through the preparation method of the present application, vertical channel thin film crystal devices can realize integrated preparation of different channel width-to-length ratio structures according to different circuit structure application requirements.

[0088] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A method for preparing a thin film transistor, characterized in that: The method for preparing the thin film transistor comprises: Depositing a first metal electrode layer on the driving backplane, and etching the first metal electrode layer from a first end to obtain source and drain metal electrodes; Depositing a Spacer layer material on the source-drain metal electrode, and depositing a second metal electrode layer on the Spacer layer material; Etching the second metal electrode layer from the first end to obtain an initial drain-source metal electrode; Using the initial drain-source metal electrode as a hard mask layer of the Spacer layer material, etching the Spacer layer material from the first end to obtain a Spacer layer; the horizontal distance between the etching end side of the initial drain-source metal electrode and the etching end side of the Spacer layer is 0; The initial drain-source metal electrode is further etched from the first end to obtain a final drain-source metal electrode; the horizontal distance between the etched end side of the final drain-source metal electrode and the etched end side of the Spacer layer is greater than 0; Depositing active layer materials on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer, and etching the active layer materials to obtain an active layer; the active layer covers a portion of the top surface of the source-drain metal electrodes, the Spacer layer and the etched end side surface of the final drain-source metal electrodes; Depositing a gate insulating layer on the source-drain metal electrode, the active layer and the final drain-source metal electrode, and etching the gate insulating layer to form a contact hole pattern on the final drain-source metal electrode; A third metal electrode layer is deposited on the gate insulating layer, and the third metal electrode layer is etched to obtain a gate electrode, thereby completing the preparation of a thin film transistor.

2. The method for preparing a thin film transistor according to claim 1, characterized in that: Etching the second metal electrode layer from the first end to obtain an initial drain-source metal electrode, specifically comprising: performing a patterning process on the second metal electrode layer, and etching from the first end using a first wet etching process to form an initial drain-source metal electrode; The initial drain-source metal electrode is etched again from the first end to obtain the final drain-source metal electrode, specifically including: patterning the initial drain-source metal electrode, and etching from the first end using a second wet etching process to form the final drain-source metal electrode.

3. The method for preparing a thin film transistor according to claim 1, characterized in that: Depositing a first metal electrode layer on the driving backplane specifically includes: depositing the first metal electrode layer on the driving backplane using a magnetron sputtering method under a first set deposition condition or depositing the first metal electrode layer on the driving backplane using an atomic layer deposition method; Depositing a second metal electrode layer on the Spacer layer material specifically includes: depositing the second metal electrode layer on the Spacer layer material by magnetron sputtering under a first set deposition condition or depositing the second metal electrode layer on the Spacer layer material by atomic layer deposition; Depositing a third metal electrode layer on the gate insulating layer specifically includes: depositing the third metal electrode layer on the gate insulating layer by magnetron sputtering under first set deposition conditions or depositing the third metal electrode layer on the gate insulating layer by atomic layer deposition.

4. The method for preparing a thin film transistor according to claim 1, characterized in that: Depositing a Spacer layer material on the source-drain metal electrode specifically includes: depositing the Spacer layer material on the source-drain metal electrode using a plasma enhanced chemical vapor deposition method under a second set deposition condition or depositing the Spacer layer material on the source-drain metal electrode using an atomic layer deposition method; Depositing a gate insulating layer on the source-drain metal electrode, the active layer and the final drain-source metal electrode specifically includes: using plasma enhanced chemical vapor deposition to deposit a gate insulating layer on the source-drain metal electrode, the active layer and the final drain-source metal electrode under a second set deposition condition.

5. The method for preparing a thin film transistor according to claim 1, characterized in that: Depositing active layer materials on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer specifically includes: using magnetron sputtering to deposit active layer materials on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer under a third set deposition condition, or using atomic layer deposition to deposit active layer materials on the source-drain metal electrodes, the final drain-source metal electrodes and the Spacer layer.

6. The method for preparing a thin film transistor according to claim 3, characterized in that: The first set deposition conditions include: a deposition power range of 0.1KW to 1.0KW, a working pressure range of 10 -6 Pa~10 -4 Pa and deposition temperature from room temperature to 350°C.

7. The method for preparing a thin film transistor according to claim 4, characterized in that: The second set deposition conditions include: a deposition power ranging from 0.1 KW to 2.0 KW, a working gas pressure ranging from 0.5 Pa to 5 Pa, and a deposition temperature ranging from 80° C. to 350° C.

8. The method for preparing a thin film transistor according to claim 5, characterized in that: The third set deposition conditions include: a deposition power range of 0.1KW to 2.0KW, a working pressure range of 10 -6 Pa~10 -4 Pa and deposition temperature from room temperature to 350°C.

9. The method for preparing a thin film transistor according to claim 1, characterized in that: The thickness range of the first metal electrode layer, the second metal electrode layer and the third metal electrode layer is 20nm to 1000nm; the thickness range of the spacer layer material is 50nm to 2000nm; the thickness range of the active layer material is 10nm to 200nm.

10. A thin film transistor, characterized in that: The thin film transistor is manufactured by the method for manufacturing a thin film transistor according to any one of claims 1 to 8.

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