High-voltage super-junction high-power MOSFET component and preparation process thereof

Abstract

The invention relates to the technical field of semiconductor device preparation, in particular to a high-voltage super-junction high-power MOSFET component and a preparation process thereof.The alternate ion implantation technology is adopted, implantation energy and dosage are controlled according to preset requirements, and different types of ions are alternately implanted into a substrate base material to form an alternate doping area needed by a super junction; a photoetching machine is used for transferring a pre-designed device pattern to the photoresist through exposure, developing treatment is carried out, the photoresist of the exposed part is removed, and an etching area is obtained; carrying out etching treatment on the etching region, removing an unwanted epitaxial layer part, and forming a source electrode, a drain electrode and a grid electrode structure outline; and depositing an insulating layer material on the etched structure by adopting a chemical vapor deposition method, and after deposition is completed, carrying out annealing treatment on the component. According to the invention, high-precision manufacturing of the high-voltage super-junction high-power MOSFET component is realized, and the voltage endurance capability, the conduction performance and the reliability of the component can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor device preparation, in particular to a high-voltage super junction high-power MOSFET component and a preparation process thereof. Background Art

[0002] High-voltage super-junction high-power MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor) components are a key device widely used in the field of power electronics. Its core advantage lies in its ability to achieve efficient energy conversion and switch control under high voltage and high current conditions. Traditional power MOSFET devices face an inherent contradiction between on-resistance and breakdown voltage in high-voltage applications, that is, increasing the breakdown voltage usually leads to an increase in on-resistance, thereby reducing the efficiency of the device. In order to solve this problem, super-junction technology came into being. By introducing an alternating arrangement of P-type and N-type column structures in the drift region, the electric field distribution is optimized, the on-resistance is significantly reduced, and a high breakdown voltage is maintained. This structure enables high-voltage super-junction MOSFETs to exhibit excellent performance in high-power applications and is widely used in switching power supplies, motor drives, new energy generation and other fields.

[0003] In terms of preparation process, the manufacture of high-voltage super-junction high-power MOSFET involves multiple key technical steps. First, it is necessary to grow a high-quality epitaxial layer on the semiconductor substrate to form a drift region; second, through the alternating ion implantation technology, the distribution of P-type and N-type doped regions is precisely controlled to form a super-junction structure; then, the geometry of the source, drain and gate is defined by photolithography and etching processes, and the insulating layer and metallization layer are deposited by chemical vapor deposition (CVD) and other methods to complete the electrical connection of the device. In addition, in order to ensure the reliability of the device under high voltage, it is also necessary to design a terminal structure at the edge of the device to optimize the electric field distribution, and cover the surface with a passivation layer to prevent environmental damage. The entire preparation process places extremely high demands on equipment accuracy, material quality and process control, especially in the formation of the super-junction structure and the deposition of the insulating layer, it is necessary to precisely control the doping concentration, thickness uniformity and interface quality. In view of this, the present invention proposes a high-voltage super-junction high-power MOSFET component and its preparation process. Summary of the invention

[0004] The present invention overcomes the deficiencies of the prior art and provides a high-voltage super junction high-power MOSFET component and a preparation process thereof.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: The first aspect of the present invention discloses a process for preparing a high-voltage super junction high-power MOSFET component, comprising the following steps: Obtaining a semiconductor substrate, ultrasonically cleaning the substrate with deionized water, and immersing and cleaning the substrate with an acid solution; The epitaxial material is grown on the substrate according to the set thickness and doping concentration, and the growth status of the epitaxial layer is monitored at a preset time node, and the epitaxial growth parameters are regulated according to the growth status; Using the alternating ion implantation technology, the implantation energy and dosage are controlled according to the preset requirements, and different types of ions are alternately implanted into the substrate to form the alternating doping regions required for the super junction; Using a photolithography machine, the pre-designed device pattern is transferred to the photoresist through exposure, and then developed to remove the photoresist of the exposed part to obtain the etching area; Etching the etching area to remove unnecessary epitaxial layer portions to form source, drain and gate structure outlines; On the etched structure, an insulating layer material is deposited by chemical vapor deposition, and after the deposition is completed, the components are annealed; Conduct electrical tests on components after annealing to screen out products that meet performance requirements, and classify, package and label qualified finished components.

[0006] Furthermore, the growth status of the epitaxial layer is monitored at a preset time node, specifically: At a preset time node, a spectral image of the epitaxial layer is acquired by a spectral imager, a voxelization algorithm is introduced, and the spectral image is voxelized according to the voxelization algorithm to divide the spectral image into a plurality of voxel grids; Performing feature extraction processing on the spectral image in each voxel grid respectively to obtain the spectral features corresponding to each voxel grid; wherein the spectral features include peak position, peak intensity, peak width, peak shape and peak area; Compare the spectral features corresponding to each voxel grid with the preset standard to obtain the matching degree between the spectral features corresponding to each voxel grid and the preset standard; If the matching degree between the spectral feature corresponding to a certain voxel grid and the preset standard is greater than the preset matching degree, the voxel grid is marked as a voxel grid with a normal growth state; If the matching degree between the spectral feature corresponding to a certain voxel grid and the preset standard is not greater than the preset matching degree, the voxel grid is marked as a voxel grid with abnormal growth state; Calculating the total number of the abnormal growth state voxel grids and calculating the total number of the normal growth state voxel grids; performing ratio processing on the total number of the abnormal growth state voxel grids and the total number of the normal growth state voxel grids to obtain the abnormal growth voxel grid ratio; The abnormal growth voxel grid ratio is compared with a preset threshold; if the abnormal growth voxel grid ratio is greater than the preset threshold, it indicates that the growth condition of the epitaxial layer is abnormal; if the abnormal growth voxel grid ratio is not greater than the preset threshold, it indicates that the growth condition of the epitaxial layer is normal.

[0007] Furthermore, epitaxial growth parameters are regulated according to the growth conditions, specifically: If the growth condition of the epitaxial layer is abnormal, an image region corresponding to a voxel grid with an abnormal growth condition is marked in the spectral image to obtain an abnormal growth region of the epitaxial layer; Calculating the area value of the abnormal growth region of the epitaxial layer, and determining whether the area value of the abnormal growth region of the epitaxial layer is greater than a preset area value; If the area value of the abnormal growth region of the epitaxial layer is greater than the preset area value, the epitaxial growth equipment is controlled to shut down, and the substrate base material in the epitaxial growth equipment is scrapped; If the area value of the abnormal growth region of the epitaxial layer is not greater than the preset area value, then obtaining various real-time epitaxial growth parameters of the epitaxial growth equipment; the real-time epitaxial growth parameters include temperature, pressure, gas flow rate and reactant concentration; Calculating the difference between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter to obtain the deviation value between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter; Comparing the deviation value between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter with the preset deviation value threshold value respectively; Marking the real-time epitaxial growth parameter whose deviation value is greater than a preset deviation value threshold as a drift epitaxial growth parameter, and obtaining the drift value of the drift epitaxial growth parameter; The drift value of the drift epitaxial growth parameter is the difference between the real-time epitaxial growth parameter whose deviation value is greater than the preset deviation value threshold and the corresponding preset epitaxial growth parameter.

[0008] Further, regulating and processing the epitaxial growth parameters according to the growth condition further includes: Prefabricate in advance the control measures corresponding to the various drift amplitudes of various epitaxial growth parameters in the epitaxial growth equipment; Constructing a knowledge graph, and importing the control measures corresponding to various drift amplitudes of various epitaxial growth parameters in the extracted and formulated epitaxial growth equipment into the knowledge graph; and regularly updating the knowledge graph; If the area value of the abnormal growth region of the epitaxial layer is not greater than the preset area value, obtaining the drift epitaxial growth parameter of the epitaxial growth equipment and its drift value; Importing the drift epitaxial growth parameters and the drift values ​​of the epitaxial growth equipment into the knowledge graph for matching, and obtaining corresponding control measures through matching; The epitaxial growth equipment is regulated according to the matched regulation measures.

[0009] Furthermore, the alternating ion implantation technology is used to control the implantation energy and dosage according to preset requirements, and different types of ions are alternately implanted into the substrate to form the alternating doping regions required for the super junction, specifically: According to the design requirements of the super junction structure, determine the distribution pattern, ion type, implantation energy and dose range of the alternating doping region, and set the cycle and sequence of the alternating implantation; Initialize the parameters of the ion implantation equipment, including ion source selection, acceleration voltage, beam intensity, implantation angle, and scanning path; Start the ion implantation process, select different types of ion sources in turn according to the preset alternating implantation sequence, and dynamically adjust the acceleration voltage and beam intensity according to the implantation energy and dose requirements of each ion; During the implantation process, the implantation energy and dose deviations are monitored in real time, and the implantation parameters are fine-tuned through a feedback control system. At the same time, the implantation sequence and dose distribution are dynamically optimized based on the real-time doping concentration distribution of the substrate and the preset alternating doping area targets to compensate for the non-uniformity during the implantation process. After completing a round of alternating injection, the substrate base material is tested for doping concentration distribution. If the test result deviates from the preset target, the injection parameters are readjusted and supplementary injection is performed until the concentration distribution of the alternating doping area meets the design requirements.

[0010] Further, the etching area is etched to remove unnecessary epitaxial layer portions to form source, drain and gate structure profiles, specifically: Determine the geometry, size and position of the source, drain and gate according to the component design drawings, and generate the corresponding etching mask pattern; Transferring the etching mask pattern to the photoresist layer through a photolithography process to form an etching area with a preset profile; Initialize the parameters of the etching equipment, including etching gas type, gas flow, reaction chamber pressure, RF power and etching time; Start the etching process and dynamically adjust the etching gas flow rate and RF power according to the depth and sidewall morphology requirements of the etching area; During the etching process, the changes in etching depth and sidewall morphology are monitored in real time, and the etching parameters are fine-tuned through a feedback control system. At the same time, according to the characteristics of the epitaxial layer material and the geometric shape of the etching area, the ratio of etching gas and the pressure of the reaction chamber are optimized to reduce lateral erosion and bottom residue during the etching process. After etching is completed, the etched area is subjected to morphological inspection. If the inspection result deviates from the preset target, the etching parameters are readjusted and supplementary etching is performed until the structural contours of the source, drain and gate meet the design requirements.

[0011] Furthermore, on the etched structure, an insulating layer material is deposited by a chemical vapor deposition method, specifically: According to the design requirements of components, determine the type, thickness and uniformity requirements of the insulating layer material, and set the target parameters of the deposition process, including the type of reaction gas, gas flow, reaction chamber pressure, deposition temperature and deposition time; Initialize the parameters of the chemical vapor deposition equipment to ensure that the reaction chamber is clean and free of contamination, and preheat to the target deposition temperature; then, start the deposition process, introduce the reaction gas into the reaction chamber according to the preset gas flow rate and reaction chamber pressure, so that it chemically reacts on the surface of the etched structure to generate an insulating layer material; During the deposition process, the growth rate and thickness distribution of the insulating layer are monitored in real time, and the gas flow rate and reaction chamber pressure are dynamically adjusted through the feedback control system to ensure the uniformity and consistency of the deposition thickness. At the same time, according to the characteristics of the insulating layer material and the geometric shape of the etched structure, the ratio of the reaction gas and the deposition temperature are optimized to reduce defects and stress accumulation during the deposition process. After the deposition is completed, the thickness and uniformity of the insulating layer are tested. If the test results deviate from the preset targets, the deposition parameters are readjusted and additional deposition is performed until the thickness and uniformity of the insulating layer meet the design requirements.

[0012] A second aspect of the present invention discloses a high-voltage super junction high-power MOSFET component, which is applied to a preparation process of a high-voltage super junction high-power MOSFET component as described in any one of the above items, comprising: The substrate is made of silicon or silicon carbide and is used to support the structure of the entire device; The epitaxial layer is used to form the drift region of the device to withstand voltage; Superjunction structure, consisting of alternating P-type and N-type columns, is used to optimize the device's breakdown voltage and on-resistance performance; Source, located in the N+ doped region on the surface of the component, is used to provide injection and collection of electrons; The drain is an N+ doped region at the bottom or back of the device that collects electrons and outputs current. Gate, a thin oxide layer between the gate and the channel, is used to isolate the gate and form an electric field to control the channel.

[0013] The present invention solves the technical defects existing in the background technology, and has the following beneficial effects: by precisely controlling key steps such as epitaxial layer growth, alternating ion implantation, photolithography, etching, insulating layer deposition and annealing, high-precision manufacturing of high-voltage super junction high-power MOSFET components is achieved, which can improve the device's voltage resistance, conduction performance and reliability, while ensuring the consistency and traceability of the product, and is suitable for high-power, high-voltage application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying creative work.

[0015] Figure 1 This is the first flow chart of the high-voltage super-junction high-power MOSFET component preparation process; Figure 2 This is the second flow chart of the high-voltage super junction high-power MOSFET component preparation process; Figure 3 This is the third flow chart of the high-voltage super junction high-power MOSFET component preparation process. DETAILED DESCRIPTION

[0016] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0017] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0018] like Figure 1 As shown, the first aspect of the present invention discloses a process for preparing a high-voltage super junction high-power MOSFET component, comprising the following steps: S102, obtaining a semiconductor substrate, ultrasonically cleaning the substrate with deionized water, and immersing and cleaning the substrate with an acid solution; S104, growing the epitaxial material on the substrate according to the set thickness and doping concentration, acquiring and monitoring the growth status of the epitaxial layer at a preset time node, and regulating and processing the epitaxial growth parameters according to the growth status; S106, using an alternating ion implantation technique, controlling the implantation energy and dosage according to preset requirements, and alternately implanting different types of ions into the substrate to form an alternating doping region required for a super junction; S108, using a photolithography machine, transferring the pre-designed device pattern to the photoresist by exposure, and performing a development process to remove the photoresist of the exposed part to obtain an etching area; S110, performing etching processing on the etching area to remove unnecessary epitaxial layer portions to form source, drain and gate structure outlines; S112, depositing an insulating layer material on the etched structure by a chemical vapor deposition method, and performing an annealing treatment on the components after the deposition is completed; S114. Conduct electrical tests on components after annealing to select products that meet the performance requirements, and classify, package and label qualified finished components.

[0019] It should be noted that this preparation process achieves high-precision manufacturing of high-voltage super-junction high-power MOSFET components by precisely controlling key steps such as epitaxial layer growth, alternating ion implantation, photolithography, etching, insulating layer deposition and annealing. It can improve the device's voltage resistance, conduction performance and reliability, while ensuring product consistency and traceability, and is suitable for high-power, high-voltage application scenarios.

[0020] Furthermore, the growth status of the epitaxial layer is monitored at a preset time node, such as Figure 2 As shown, specifically: S202, obtaining a spectral image of the epitaxial layer through a spectral imager at a preset time node, introducing a voxelization algorithm, and voxelizing the spectral image according to the voxelization algorithm to divide the spectral image into a plurality of voxel grids; S204, performing feature extraction processing on the spectral image in each voxel grid respectively to obtain the spectral features corresponding to each voxel grid; wherein the spectral features include peak position, peak intensity, peak width, peak shape and peak area; S206, comparing the spectral features corresponding to each voxel grid with a preset standard, and obtaining a matching degree between the spectral features corresponding to each voxel grid and the preset standard; S208, if the matching degree between the spectral feature corresponding to a certain voxel grid and the preset standard is greater than the preset matching degree, marking the voxel grid as a voxel grid with a normal growth state; S210, if the matching degree between the spectral feature corresponding to a certain voxel grid and the preset standard is not greater than the preset matching degree, marking the voxel grid as a voxel grid with abnormal growth status; S212, calculating the total number of the abnormal growth state voxel grids, and calculating the total number of the normal growth state voxel grids; performing ratio processing on the total number of the abnormal growth state voxel grids and the total number of the normal growth state voxel grids to obtain the abnormal growth voxel grid ratio; S214, comparing the abnormal growth voxel grid ratio with a preset threshold; if the abnormal growth voxel grid ratio is greater than the preset threshold, it indicates that the growth condition of the epitaxial layer is abnormal; if the abnormal growth voxel grid ratio is not greater than the preset threshold, it indicates that the growth condition of the epitaxial layer is normal.

[0021] It should be noted that the spectral image of the epitaxial layer is obtained by the spectral imager at the preset time node to monitor the growth status of the epitaxial layer in real time. The voxelization algorithm is introduced to divide the spectral image into several voxel grids (three-dimensional pixel units) to facilitate subsequent local feature analysis and processing. The spectral image in each voxel grid is feature extracted to obtain spectral features, including peak position, peak intensity, peak width, peak shape, and peak area. These spectral features reflect the key information of the epitaxial layer material, such as crystal quality, doping concentration, and stress distribution. The spectral features of each voxel grid are compared with the preset standard to calculate the matching degree. Among them, "preset standards" refer to reference values ​​or ranges of spectral characteristics set in advance during the growth of the epitaxial layer. These reference values ​​are determined through experiments or theoretical models based on the growth state of the ideal epitaxial layer (such as crystal quality, doping concentration, stress distribution, etc.). The preset standards include specific values ​​or ranges of spectral characteristics such as peak position, peak intensity, peak width, peak shape and peak area, which are used to compare with the actually monitored spectral characteristics to determine whether the growth condition of the epitaxial layer is normal. Through the preset standards, quantitative evaluation and real-time monitoring of the quality of epitaxial layer growth can be achieved.

[0022] In summary, this process method uses a spectral imager to monitor the growth status of the epitaxial layer in real time, and combines voxelization algorithm and spectral feature extraction to achieve accurate evaluation of the growth quality of the epitaxial layer. By calculating the abnormal growth voxel grid ratio and comparing it with the preset threshold, it is possible to quickly and accurately determine whether the growth status of the epitaxial layer is normal. Through real-time monitoring and feedback mechanisms, the uniformity and consistency of epitaxial layer growth can be significantly improved, and the formation of defects and abnormal areas can be reduced, thereby improving the performance and reliability of high-voltage super-junction high-power MOSFET components.

[0023] Furthermore, epitaxial growth parameters are regulated according to the growth conditions, such as Figure 3 As shown, specifically: S302, if the growth condition of the epitaxial layer is abnormal, marking the image area corresponding to the voxel grid with abnormal growth condition in the spectral image to obtain the abnormal growth area of ​​the epitaxial layer; S304, calculating the area value of the abnormal growth region of the epitaxial layer, and determining whether the area value of the abnormal growth region of the epitaxial layer is greater than a preset area value; S306, if the area value of the abnormal growth region of the epitaxial layer is greater than a preset area value, the epitaxial growth equipment is controlled to shut down, and the substrate base material in the epitaxial growth equipment is scrapped; S308, if the area value of the abnormal growth region of the epitaxial layer is not greater than the preset area value, obtaining various real-time epitaxial growth parameters of the epitaxial growth equipment; the real-time epitaxial growth parameters include temperature, pressure, gas flow rate and reactant concentration; S310, calculating the difference between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter to obtain the deviation value between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter; S312, respectively comparing the deviation value between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter with the preset deviation value threshold; S314, calibrating the real-time epitaxial growth parameter whose deviation value is greater than a preset deviation value threshold as a drift epitaxial growth parameter, and obtaining the drift value of the drift epitaxial growth parameter; The drift value of the drift epitaxial growth parameter is the difference between the real-time epitaxial growth parameter whose deviation value is greater than the preset deviation value threshold and the corresponding preset epitaxial growth parameter.

[0024] It should be noted that if the growth condition of the epitaxial layer is abnormal, the image area corresponding to the voxel grid of the abnormal growth state is marked in the spectral image to determine the abnormal growth area of ​​the epitaxial layer. The area value of the abnormal growth area is calculated and compared with the preset area value to determine the severity of the abnormal area. If the area value of the abnormal area is greater than the preset area value, it means that the abnormal area is too large, affecting the overall device performance. At this time, the epitaxial growth equipment is controlled to shut down and the substrate is scrapped to avoid resource waste. If the area value of the abnormal area is not greater than the preset area value, it means that the abnormal area is small and can be repaired by parameter adjustment. At this time, the real-time epitaxial growth parameters of the epitaxial growth equipment are continued to be obtained. The real-time epitaxial growth parameters of the epitaxial growth equipment are obtained, including temperature, pressure, gas flow rate, and reactant concentration. The difference between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter is calculated to obtain the deviation value. The deviation value of each real-time epitaxial growth parameter is compared with the preset deviation value threshold. The real-time epitaxial growth parameter with a deviation value greater than the preset deviation value threshold is calibrated as a "drift epitaxial growth parameter" and its drift value (i.e., deviation value) is recorded.

[0025] This process method realizes precise control of the epitaxial growth process by marking and calculating the area of ​​abnormal epitaxial layer growth, combined with the deviation analysis of real-time epitaxial growth parameters. When the abnormal area is too large, the substrate is promptly shut down and scrapped to avoid waste of resources; when the abnormal area is small, the deviation value of the real-time epitaxial growth parameter is analyzed to identify the drift parameter and quantify its deviation degree, providing a basis for subsequent parameter adjustment.

[0026] Further, regulating and processing the epitaxial growth parameters according to the growth condition further includes: Prefabricate in advance the control measures corresponding to the various drift amplitudes of various epitaxial growth parameters in the epitaxial growth equipment; Constructing a knowledge graph, and importing the control measures corresponding to various drift amplitudes of various epitaxial growth parameters in the extracted and formulated epitaxial growth equipment into the knowledge graph; and regularly updating the knowledge graph; If the area value of the abnormal growth region of the epitaxial layer is not greater than the preset area value, obtaining the drift epitaxial growth parameter of the epitaxial growth equipment and its drift value; Importing the drift epitaxial growth parameters and the drift values ​​of the epitaxial growth equipment into the knowledge graph for matching, and obtaining corresponding control measures through matching; The epitaxial growth equipment is regulated according to the matched regulation measures.

[0027] It should be noted that the corresponding control measures for different drift amplitudes of various epitaxial growth parameters (such as temperature, pressure, gas flow, reactant concentration, etc.) in the epitaxial growth equipment should be formulated in advance. These measures are based on experimental data, process experience and theoretical models to ensure rapid response and adjustment when parameters drift. The prefabricated epitaxial growth parameter drift amplitudes and their corresponding control measures are imported into the knowledge graph. The knowledge graph is a structured knowledge representation method that can clearly show the relationship between parameter drift and control measures. The knowledge graph is updated regularly to ensure that it contains the latest process data and optimization measures to adapt to process improvements and equipment changes.

[0028] If the area value of the abnormal growth region of the epitaxial layer is not greater than the preset area value, the drift epitaxial growth parameters and their drift values ​​of the epitaxial growth equipment are obtained. The drift epitaxial growth parameters and their drift values ​​are imported into the knowledge graph for matching, and the control measures corresponding to the current drift situation are found. According to the control measures obtained by matching the knowledge graph, the epitaxial growth equipment is controlled in real time to correct the parameter drift and restore the ideal state of epitaxial growth.

[0029] The intelligent control mechanism of this process method based on the knowledge graph can significantly improve the stability and consistency of the epitaxial growth process, reduce the formation of abnormal areas, and improve the performance and yield of high-voltage super-junction high-power MOSFET components.

[0030] Furthermore, the alternating ion implantation technology is used to control the implantation energy and dosage according to preset requirements, and different types of ions are alternately implanted into the substrate to form the alternating doping regions required for the super junction, specifically: According to the design requirements of the super junction structure, determine the distribution pattern, ion type, implantation energy and dose range of the alternating doping region, and set the cycle and sequence of the alternating implantation; Initialize the parameters of the ion implantation equipment, including ion source selection, acceleration voltage, beam intensity, implantation angle, and scanning path; Start the ion implantation process, select different types of ion sources in turn according to the preset alternating implantation sequence, and dynamically adjust the acceleration voltage and beam intensity according to the implantation energy and dose requirements of each ion; During the implantation process, the implantation energy and dose deviations are monitored in real time, and the implantation parameters are fine-tuned through a feedback control system. At the same time, the implantation sequence and dose distribution are dynamically optimized based on the real-time doping concentration distribution of the substrate and the preset alternating doping area targets to compensate for the non-uniformity during the implantation process. After completing a round of alternating injection, the substrate base material is tested for doping concentration distribution. If the test result deviates from the preset target, the injection parameters are readjusted and supplementary injection is performed until the concentration distribution of the alternating doping area meets the design requirements.

[0031] It should be noted that according to the design requirements of the super junction structure, the distribution pattern, ion type, injection energy and dosage range of the alternating doping area are clearly defined, and the cycle and sequence of the alternating injection are set. These parameters are the key to the performance of the super junction structure and directly affect the device's withstand voltage and conduction characteristics. Initialize the parameters of the ion implantation equipment, including ion source selection, acceleration voltage, beam intensity, implantation angle and scanning path. The precise setting of these parameters is the basis for ensuring the stability and consistency of the ion implantation process.

[0032] According to the preset alternating injection sequence, different types of ion sources are selected in turn, and the acceleration voltage and beam intensity are dynamically adjusted according to the injection energy and dosage requirements of each ion. During the injection process, the deviation of the injection energy and dosage is monitored in real time, and the injection parameters are fine-tuned through the feedback control system to ensure the injection accuracy. According to the real-time doping concentration distribution of the substrate base material, combined with the preset alternating doping area target, the injection sequence and dose distribution are dynamically optimized to compensate for the non-uniformity during the injection process. After completing a round of alternating injection, the doping concentration distribution of the substrate base material is tested to evaluate the injection effect. If there is a deviation between the test result and the preset target, the injection parameters are readjusted and supplementary injection is performed until the concentration distribution of the alternating doping area meets the design requirements.

[0033] This process method achieves the high-precision formation of the alternating doped regions required for the super junction structure by precisely controlling the ion type, injection energy, dose, sequence and cycle of the alternating ion implantation, combined with real-time monitoring and feedback control. Dynamic optimization of the implantation sequence and dose distribution can effectively compensate for the non-uniformity during the implantation process and ensure the uniformity and consistency of the doping concentration distribution. The performance stability of the super junction structure is further improved by doping concentration detection and supplementary implantation. This high-precision ion implantation process can effectively improve the voltage resistance and conduction characteristics of high-voltage super junction high-power MOSFET components, while improving production efficiency and product yield, providing reliable technical support for the manufacture of high-performance power devices.

[0034] Further, the etching area is etched to remove unnecessary epitaxial layer portions to form source, drain and gate structure profiles, specifically: Determine the geometry, size and position of the source, drain and gate according to the component design drawings, and generate the corresponding etching mask pattern; Transferring the etching mask pattern to the photoresist layer through a photolithography process to form an etching area with a preset profile; Initialize the parameters of the etching equipment, including etching gas type, gas flow, reaction chamber pressure, RF power and etching time; Start the etching process and dynamically adjust the etching gas flow rate and RF power according to the depth and sidewall morphology requirements of the etching area; During the etching process, the changes in etching depth and sidewall morphology are monitored in real time, and the etching parameters are fine-tuned through a feedback control system. At the same time, according to the characteristics of the epitaxial layer material and the geometric shape of the etching area, the ratio of etching gas and the pressure of the reaction chamber are optimized to reduce lateral erosion and bottom residue during the etching process. After etching is completed, the etched area is subjected to morphological inspection. If the inspection result deviates from the preset target, the etching parameters are readjusted and supplementary etching is performed until the structural contours of the source, drain and gate meet the design requirements.

[0035] It should be noted that this process method achieves high-precision formation of the source, drain and gate structure contours by precisely controlling the generation of the etching mask pattern, the transfer of the photolithography process and the parameter adjustment of the etching process. The real-time monitoring and feedback control mechanism can dynamically adjust the etching parameters to ensure the accuracy of the etching depth and sidewall morphology, while optimizing the gas ratio and reaction chamber pressure to reduce lateral erosion and bottom residue. The accuracy and consistency of the structural contour are further improved through morphology detection and supplementary etching.

[0036] Furthermore, on the etched structure, an insulating layer material is deposited by a chemical vapor deposition method, specifically: According to the design requirements of components, determine the type, thickness and uniformity requirements of the insulating layer material, and set the target parameters of the deposition process, including the type of reaction gas, gas flow, reaction chamber pressure, deposition temperature and deposition time; Initialize the parameters of the chemical vapor deposition equipment to ensure that the reaction chamber is clean and free of contamination, and preheat to the target deposition temperature; then, start the deposition process, introduce the reaction gas into the reaction chamber according to the preset gas flow rate and reaction chamber pressure, so that it chemically reacts on the surface of the etched structure to generate an insulating layer material; During the deposition process, the growth rate and thickness distribution of the insulating layer are monitored in real time, and the gas flow rate and reaction chamber pressure are dynamically adjusted through the feedback control system to ensure the uniformity and consistency of the deposition thickness. At the same time, according to the characteristics of the insulating layer material and the geometric shape of the etched structure, the ratio of the reaction gas and the deposition temperature are optimized to reduce defects and stress accumulation during the deposition process. After the deposition is completed, the thickness and uniformity of the insulating layer are tested. If the test results deviate from the preset targets, the deposition parameters are readjusted and additional deposition is performed until the thickness and uniformity of the insulating layer meet the design requirements.

[0037] It should be noted that the type of insulating layer material (such as silicon dioxide, silicon nitride, etc.), thickness and uniformity requirements are determined according to the component design requirements. Set the target parameters of the deposition process, including the type of reaction gas, gas flow, reaction chamber pressure, deposition temperature and deposition time. Initialize the parameters of the chemical vapor deposition equipment to ensure that the reaction chamber is clean and pollution-free to prevent impurities from affecting the quality of the insulating layer. Preheat the reaction chamber to the target deposition temperature to ensure the stability and consistency of the deposition process. Start the deposition process and introduce the reaction gas into the reaction chamber according to the preset gas flow and reaction chamber pressure so that it reacts chemically on the surface of the etched structure to generate an insulating layer material.

[0038] During the deposition process, the growth rate and thickness distribution of the insulating layer are monitored in real time, and the gas flow rate and reaction chamber pressure are dynamically adjusted through the feedback control system to ensure the uniformity and consistency of the deposition thickness. According to the characteristics of the insulating layer material and the geometric shape of the etched structure, the ratio of the reaction gas and the deposition temperature are optimized to reduce defects (such as pinholes, cracks) and stress accumulation during the deposition process. After the deposition is completed, the thickness and uniformity of the insulating layer are tested to evaluate the deposition effect. If the test results deviate from the preset targets, the deposition parameters are readjusted and additional deposition is performed until the thickness and uniformity of the insulating layer meet the design requirements.

[0039] This process step achieves high-quality deposition of insulating layer materials by precisely controlling the parameters of the chemical vapor deposition process (such as the type of reaction gas, gas flow, reaction chamber pressure, deposition temperature and deposition time) combined with real-time monitoring and feedback control mechanisms.

[0040] A second aspect of the present invention discloses a high-voltage super junction high-power MOSFET component, which is applied to a preparation process of a high-voltage super junction high-power MOSFET component as described in any one of the above items, comprising: The substrate is made of silicon or silicon carbide and is used to support the structure of the entire device; The epitaxial layer is used to form the drift region of the device to withstand voltage; Superjunction structure, consisting of alternating P-type and N-type columns, is used to optimize the device's breakdown voltage and on-resistance performance; Source, located in the N+ doped region on the surface of the component, is used to provide injection and collection of electrons; The drain is an N+ doped region at the bottom or back of the device that collects electrons and outputs current. Gate, a thin oxide layer between the gate and the channel, is used to isolate the gate and form an electric field to control the channel.

[0041] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0042] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0043] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0044] A person of ordinary skill in the art can understand that: all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0045] Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods of each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0046] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A process for preparing a high-voltage super junction high-power MOSFET component, characterized in that: The following steps are involved: Obtaining a semiconductor substrate, ultrasonically cleaning the substrate with deionized water, and immersing and cleaning the substrate with an acid solution; The epitaxial material is grown on the substrate according to the set thickness and doping concentration, and the growth status of the epitaxial layer is monitored at a preset time node, and the epitaxial growth parameters are regulated according to the growth status; Using the alternating ion implantation technology, the implantation energy and dosage are controlled according to the preset requirements, and different types of ions are alternately implanted into the substrate to form the alternating doping regions required for the super junction; Using a photolithography machine, the pre-designed device pattern is transferred to the photoresist through exposure, and then developed to remove the photoresist of the exposed part to obtain the etching area; Etching the etching area to remove unnecessary epitaxial layer portions to form source, drain and gate structure outlines; On the etched structure, an insulating layer material is deposited by chemical vapor deposition, and after the deposition is completed, the components are annealed; Conduct electrical tests on components after annealing to screen out products that meet performance requirements, and classify, package and label qualified finished components.

2. A process for preparing a high-voltage super junction high-power MOSFET component according to claim 1, characterized in that: The growth status of the epitaxial layer is monitored at a preset time node, specifically: At a preset time node, a spectral image of the epitaxial layer is acquired by a spectral imager, a voxelization algorithm is introduced, and the spectral image is voxelized according to the voxelization algorithm to divide the spectral image into a plurality of voxel grids; Performing feature extraction processing on the spectral image in each voxel grid respectively to obtain the spectral features corresponding to each voxel grid; wherein the spectral features include peak position, peak intensity, peak width, peak shape and peak area; Compare the spectral features corresponding to each voxel grid with the preset standard to obtain the matching degree between the spectral features corresponding to each voxel grid and the preset standard; If the matching degree between the spectral feature corresponding to a certain voxel grid and the preset standard is greater than the preset matching degree, the voxel grid is marked as a voxel grid with a normal growth state; If the matching degree between the spectral feature corresponding to a certain voxel grid and the preset standard is not greater than the preset matching degree, the voxel grid is marked as a voxel grid with abnormal growth state; Calculating the total number of the abnormal growth state voxel grids and calculating the total number of the normal growth state voxel grids; performing ratio processing on the total number of the abnormal growth state voxel grids and the total number of the normal growth state voxel grids to obtain the abnormal growth voxel grid ratio; The abnormal growth voxel grid ratio is compared with a preset threshold; if the abnormal growth voxel grid ratio is greater than the preset threshold, it indicates that the growth condition of the epitaxial layer is abnormal; if the abnormal growth voxel grid ratio is not greater than the preset threshold, it indicates that the growth condition of the epitaxial layer is normal.

3. A process for preparing a high-voltage super junction high-power MOSFET component according to claim 2, characterized in that: The epitaxial growth parameters are regulated according to the growth conditions, specifically: If the growth condition of the epitaxial layer is abnormal, an image region corresponding to a voxel grid with an abnormal growth condition is marked in the spectral image to obtain an abnormal growth region of the epitaxial layer; Calculating the area value of the abnormal growth region of the epitaxial layer, and determining whether the area value of the abnormal growth region of the epitaxial layer is greater than a preset area value; If the area value of the abnormal growth region of the epitaxial layer is greater than the preset area value, the epitaxial growth equipment is controlled to shut down, and the substrate base material in the epitaxial growth equipment is scrapped; If the area value of the abnormal growth region of the epitaxial layer is not greater than the preset area value, then obtaining various real-time epitaxial growth parameters of the epitaxial growth equipment; the real-time epitaxial growth parameters include temperature, pressure, gas flow rate and reactant concentration; Calculating the difference between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter to obtain the deviation value between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter; Comparing the deviation value between each real-time epitaxial growth parameter and the corresponding preset epitaxial growth parameter with the preset deviation value threshold value respectively; Marking the real-time epitaxial growth parameter whose deviation value is greater than a preset deviation value threshold as a drift epitaxial growth parameter, and obtaining the drift value of the drift epitaxial growth parameter; The drift value of the drift epitaxial growth parameter is the difference between the real-time epitaxial growth parameter whose deviation value is greater than the preset deviation value threshold and the corresponding preset epitaxial growth parameter.

4. The process for preparing a high-voltage super junction high-power MOSFET component according to claim 3, characterized in that: The epitaxial growth parameters are regulated according to the growth condition, and further comprising: Prefabricate in advance the control measures corresponding to the various drift amplitudes of various epitaxial growth parameters in the epitaxial growth equipment; Constructing a knowledge graph, and importing the control measures corresponding to various drift amplitudes of various epitaxial growth parameters in the extracted and formulated epitaxial growth equipment into the knowledge graph; and regularly updating the knowledge graph; If the area value of the abnormal growth region of the epitaxial layer is not greater than the preset area value, obtaining the drift epitaxial growth parameter of the epitaxial growth equipment and its drift value; Importing the drift epitaxial growth parameters and the drift values ​​of the epitaxial growth equipment into the knowledge graph for matching, and obtaining corresponding control measures through matching; The epitaxial growth equipment is regulated according to the matched regulation measures.

5. The process for preparing a high-voltage super junction high-power MOSFET component according to claim 1, characterized in that: Using the alternating ion implantation technology, the implantation energy and dose are controlled according to the preset requirements, and different types of ions are alternately implanted into the substrate to form the alternating doping areas required for the super junction, specifically: According to the design requirements of the super junction structure, determine the distribution pattern, ion type, implantation energy and dose range of the alternating doping region, and set the cycle and sequence of the alternating implantation; Initialize the parameters of the ion implantation equipment, including ion source selection, acceleration voltage, beam intensity, implantation angle, and scanning path; Start the ion implantation process, select different types of ion sources in turn according to the preset alternating implantation sequence, and dynamically adjust the acceleration voltage and beam intensity according to the implantation energy and dose requirements of each ion; During the implantation process, the implantation energy and dose deviations are monitored in real time, and the implantation parameters are fine-tuned through a feedback control system. At the same time, the implantation sequence and dose distribution are dynamically optimized based on the real-time doping concentration distribution of the substrate and the preset alternating doping area targets to compensate for the non-uniformity during the implantation process. After completing a round of alternating injection, the substrate base material is tested for doping concentration distribution. If the test result deviates from the preset target, the injection parameters are readjusted and supplementary injection is performed until the concentration distribution of the alternating doping area meets the design requirements.

6. The process for preparing a high-voltage super junction high-power MOSFET component according to claim 1, characterized in that: The etching area is etched to remove unnecessary epitaxial layer portions to form source, drain and gate structure profiles, specifically: Determine the geometry, size and position of the source, drain and gate according to the component design drawings, and generate the corresponding etching mask pattern; Transferring the etching mask pattern to the photoresist layer through a photolithography process to form an etching area with a preset profile; Initialize the parameters of the etching equipment, including etching gas type, gas flow, reaction chamber pressure, RF power and etching time; Start the etching process and dynamically adjust the etching gas flow rate and RF power according to the depth and sidewall morphology requirements of the etching area; During the etching process, the changes in etching depth and sidewall morphology are monitored in real time, and the etching parameters are fine-tuned through a feedback control system. At the same time, according to the characteristics of the epitaxial layer material and the geometric shape of the etching area, the ratio of etching gas and the pressure of the reaction chamber are optimized to reduce lateral erosion and bottom residue during the etching process. After etching is completed, the etched area is subjected to morphological inspection. If the inspection result deviates from the preset target, the etching parameters are readjusted and supplementary etching is performed until the structural contours of the source, drain and gate meet the design requirements.

7. The process for preparing a high-voltage super junction high-power MOSFET component according to claim 1, characterized in that: On the etched structure, the insulating layer material is deposited by chemical vapor deposition method, specifically: According to the design requirements of components, determine the type, thickness and uniformity requirements of the insulating layer material, and set the target parameters of the deposition process, including the type of reaction gas, gas flow, reaction chamber pressure, deposition temperature and deposition time; Initialize the parameters of the chemical vapor deposition equipment, ensure that the reaction chamber is clean and free of contamination, and preheat to the target deposition temperature; Then, the deposition process is started, and the reaction gas is introduced into the reaction chamber according to the preset gas flow rate and reaction chamber pressure, so that the reaction gas undergoes a chemical reaction on the surface of the etched structure to generate an insulating layer material; During the deposition process, the growth rate and thickness distribution of the insulating layer are monitored in real time, and the gas flow rate and reaction chamber pressure are dynamically adjusted through the feedback control system to ensure the uniformity and consistency of the deposition thickness. At the same time, according to the characteristics of the insulating layer material and the geometric shape of the etched structure, the ratio of the reaction gas and the deposition temperature are optimized to reduce defects and stress accumulation during the deposition process. After the deposition is completed, the thickness and uniformity of the insulating layer are tested. If the test results deviate from the preset targets, the deposition parameters are readjusted and additional deposition is performed until the thickness and uniformity of the insulating layer meet the design requirements.

8. A high-voltage super junction high-power MOSFET component, applied to the preparation process of a high-voltage super junction high-power MOSFET component according to any one of claims 1 to 7, characterized in that: include: The substrate is made of silicon or silicon carbide and is used to support the structure of the entire device; The epitaxial layer is used to form the drift region of the device to withstand voltage; Superjunction structure, consisting of alternating P-type and N-type columns, is used to optimize the device's breakdown voltage and on-resistance performance; Source, located in the N+ doped region on the surface of the component, is used to provide injection and collection of electrons; The drain is an N+ doped region at the bottom or back of the device that collects electrons and outputs current. Gate, a thin oxide layer between the gate and the channel, is used to isolate the gate and form an electric field to control the channel.

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