Manufacturing method of super junction device
By forming a barrier-like barrier layer on the semiconductor substrate layer of the superjunction device and forming an injection window at the scribe groove area and chip area locations, the problem of difficulty in removing the barrier layer is solved, and the effectiveness and consistency of the wet etching process is achieved.
Patent Information
- Application Number
- CN202510101139.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-25
AI Technical Summary
In the prior art, it is difficult to remove the barrier layer in the scribed groove area, resulting in residual or overetching of the barrier layer in the wet removal process.
A barrier-like barrier layer is formed on the semiconductor substrate layer, and an injection window is formed at the scribe groove area and the chip area location to ensure that the barrier layer etching rate of the wet etching of the two regions is consistent.
The complete removal of the barrier layer in the scribe groove area in the wet etching process is achieved, and the problem of residual or overetching is avoided.
Smart Images
Figure CN119894029A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a super junction device. Background Art
[0002] In order to solve the problem of increased on-resistance due to increased rated voltage, super junction MOS devices arrange multiple vertical PN junction structures between the drain and source terminals to achieve low on-resistance while maintaining high voltage. The existence of super junctions has greatly broken through the theoretical limits of silicon, and the higher the rated voltage, the more obvious the reduction in on-resistance.
[0003] The super junction device in the related technology includes a scribe groove area. When performing super junction injection, it is necessary to form an injection pattern with a high aspect ratio on the silicon through a barrier layer, and retain a hard mask of a certain thickness on the silicon surface at the injection pattern window position. The injected ions pass through the hard mask at the window position and are injected into the silicon to form a super junction with a certain depth in the silicon.
[0004] However, the related art does not form an injection pattern window in the barrier layer in the scribe groove area, that is, the scribe groove area is completely covered by the barrier layer. Therefore, in the subsequent barrier layer wet removal process, if the wet removal is performed for a shorter time, a larger area of the barrier layer in the scribe groove area will remain, and if the wet removal is performed for a longer time, the hard mask thickness will easily become too thin, both of which are not conducive to subsequent processes. Summary of the invention
[0005] The present application provides a method for manufacturing a super junction device, which can solve the problem of difficulty in removing the barrier layer in the scribe groove area in the related art.
[0006] In order to solve the technical problem in the background technology, the present application provides a method for manufacturing a super junction device, and the method for manufacturing a super junction device comprises the following steps:
[0007] Providing a semiconductor base layer, the semiconductor base layer comprising a chip region and a scribe groove region isolated between the chip regions, trench gates are formed in the semiconductor base layer of the chip region, and adjacent trench gates are spaced apart;
[0008] forming an oxide layer, a first hard mask layer and a barrier layer in sequence on the semiconductor base layer;
[0009] forming an injection window in the barrier layer at the chip region and the scribe line region, wherein the injection window is located between adjacent trench gates;
[0010] Etching and thinning the first hard mask layer exposed from the injection window to form a second hard mask layer;
[0011] Performing ion implantation, the implanted ions pass through the implantation window and the second hard mask layer into the semiconductor base layer at the chip area and the scribe groove area to form a super junction doping column;
[0012] The barrier layer is removed by wet etching.
[0013] Optionally, in the step of forming an injection window in the barrier layer at the chip area and the scribe groove area, wherein the injection window is located between adjacent trench gates, a width of the injection window formed in the barrier layer at the scribe groove area is smaller than a width of the injection window formed in the barrier layer at the chip area.
[0014] Optionally, in the step of sequentially forming an oxide layer, a first hard mask layer and a barrier layer on the semiconductor base layer, the thickness of the first hard mask layer is 1000 Å to 1500 Å.
[0015] Optionally, in the step of sequentially forming an oxide layer, a first hard mask layer and a barrier layer on the semiconductor base layer, the thickness of the barrier layer is 4 um to 6 um.
[0016] Optionally, in the step of etching and thinning the first hard mask layer exposed from the implantation window to form a second hard mask layer, the thickness of the second hard mask layer is 300 Å to 400 Å.
[0017] Optionally, the step of performing ion implantation to implant ions through the implantation window and the second hard mask layer into the semiconductor base layer at the chip region and the scribe groove region to form a super junction doping column includes:
[0018] Ion implantation is performed at an energy of 3000Kev to 4000Kev, and the implanted ions pass through the implantation window and the second hard mask layer into the semiconductor base layer at the chip region and the scribe groove region to form a super junction doping column.
[0019] The technical solution of the present application has at least the following advantages: since the barrier layer in the scribe groove area is in the shape of a spacer grid, that is, the barrier layer in the scribe groove area forms spaced injection windows, thus being in the shape of a spacer grid, the wet etching rate of the barrier layer in the scribe groove area and the barrier layer in the chip area is consistent, thereby avoiding the problem of incomplete or over-etching of the barrier layer in the scribe groove area by the wet etching process. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 A flow chart of a method for manufacturing a super junction device provided in one embodiment of the present application is shown;
[0022] Figure 2 A schematic diagram of the cross-sectional structure of the semiconductor substrate layer in step S1 is shown;
[0023] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0024] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0025] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S5 is completed is shown;
[0026] Figure 6 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S6 is completed. DETAILED DESCRIPTION
[0027] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0029] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0031] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a super junction device according to an embodiment of the present application. Figure 1 It can be seen that the manufacturing method of the super junction device includes the following steps:
[0032] Step S1: providing a semiconductor base layer, wherein the semiconductor base layer comprises a chip region, a scribe groove region is formed between adjacent chip regions, and trench gates are formed in the semiconductor base layer of the chip region, and adjacent trench gates are spaced apart.
[0033] Figure 2 The schematic diagram of the cross-sectional structure of the semiconductor substrate layer in step S1 is shown. Figure 2 As can be seen in the figure, the semiconductor base layer 100 includes a chip region 110, and a scribe groove region 120 is formed between adjacent chip regions 110. A trench gate 200 is formed in the semiconductor base layer 100 at the location of the chip region 110, and the trench gate 200 extends downward from the upper surface of the semiconductor base layer 100, and adjacent trench gates 200 are spaced apart.
[0034] The width of the scribe groove area is about 30um to 60um. The scribe groove area is used to isolate different chip areas and to cut and separate different chips in the later stage of wafer processing.
[0035] Step S2: forming an oxide layer, a first hard mask layer and a barrier layer in sequence on the semiconductor base layer.
[0036] Figure 3 The schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown. Figure 3 It can be seen from the figure that an oxide layer 300 , a first hard mask layer 400 and a barrier layer 500 are sequentially formed on the semiconductor base layer 100 .
[0037] Optionally, the oxide layer 300 may have a thickness ranging from 200 Å to 300 Å, the first hard mask layer 400 may have a thickness ranging from 1000 Å to 1500 Å, and the barrier layer 500 may have a thickness ranging from 4 um to 6 um.
[0038] Step S3: forming an implantation window in the barrier layer at the chip region and the scribe line region, wherein the implantation window is located between adjacent trench gates.
[0039] Figure 4 The schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown. An injection window 510 is formed in the barrier layer 500 at the chip area 110 and the scribe line area 120 . The injection window 510 is located between adjacent trench gates 200 .
[0040] Exemplarily, a photoresist layer can be first deposited on the barrier layer, so that the photoresist layer is patterned to form an injection window pattern, and the barrier layer is etched based on the injection window pattern to form an injection window in the barrier layer at the chip area and the scribe line area, and the injection window is located between adjacent trench gates.
[0041] The width of the implantation window formed in the barrier layer at the position of the scribe line area is smaller than the width of the implantation window formed in the barrier layer at the position of the chip area.
[0042] Step S4: etching and thinning the first hard mask layer exposed from the implantation window to form a second hard mask layer.
[0043] Under the protection of the barrier layer with the injection window, the first hard mask layer exposed from the injection window is etched to reduce the thickness from the first hard mask layer to the second hard mask layer. The thickness of the second hard mask layer may be 300 Å to 400 Å.
[0044] Step S5: performing ion implantation, wherein the implanted ions pass through the implantation window and the second hard mask layer into the semiconductor base layer at the chip region and the scribe groove region to form a super junction doping column.
[0045] Figure 5 The schematic diagram of the cross-sectional structure of the device after step S5 is completed is shown. Figure 5 As can be seen in the figure, when ion implantation is performed on the barrier layer 500 with the implantation window 510, the implanted ions will pass through the implantation window 510 and the second hard mask layer 400 with a thickness of 300A to 400A and the oxide layer with a thickness of 200A to 300A and be implanted into the semiconductor base layer 100 to form a super junction doping column 600. The super junction doping column 600 at the chip region 110 is spaced between the two trench gates 200.
[0046] Exemplarily, ion implantation may be performed at an energy of 3000Kev to 4000Kev, and the implanted ions pass through the implantation window and the second hard mask layer into the semiconductor base layer at the chip region and the scribe groove region to form super junction doping columns.
[0047] Exemplarily, the width of the injection window formed in the barrier layer at the scribe groove area is smaller than the width of the injection window formed in the barrier layer at the chip area, so that after the super junction doped column is formed after ion implantation, the width of the super junction doped column at the scribe groove area is smaller than the width of the super junction doped column at the chip area.
[0048] Step S6: removing the barrier layer by wet etching.
[0049] In this embodiment, since the barrier layer in the scribe groove region is in the shape of a spacer grid, that is, the barrier layer in the scribe groove region forms spaced injection windows, thus being in the shape of a spacer grid, the wet etching has the same etching rate for the barrier layer in the scribe groove region and the barrier layer in the chip region, thereby avoiding the problem of incomplete or over-etching of the barrier layer in the scribe groove region by the wet etching process.
[0050] Figure 6 The schematic diagram of the cross-sectional structure of the device after step S6 is completed is shown. Figure 6 It can be seen that after step S6 is completed, the barrier layer in the scribe groove area can be completely etched, which can avoid the problem of incomplete or over-etching of the barrier layer in the scribe groove area by the wet etching process.
[0051] For example, the wafer is immersed in an acid bath, and the etching solution can be used to remove the barrier layer of the scribe groove within the time required for the barrier layer of the chip area to be etched.
[0052] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing a super junction device, characterized in that: The method for manufacturing the super junction device comprises the following steps: Providing a semiconductor base layer, the semiconductor base layer comprising a chip region and a scribe groove region isolated between the chip regions, trench gates are formed in the semiconductor base layer of the chip region, and adjacent trench gates are spaced apart; forming an oxide layer, a first hard mask layer and a barrier layer in sequence on the semiconductor base layer; forming an injection window in the barrier layer at the chip region and the scribe line region, wherein the injection window is located between adjacent trench gates; Etching and thinning the first hard mask layer exposed from the injection window to form a second hard mask layer; Performing ion implantation, the implanted ions pass through the implantation window and the second hard mask layer into the semiconductor base layer at the chip area and the scribe groove area to form a super junction doping column; The barrier layer is removed by wet etching.
2. The method for manufacturing a super junction device according to claim 1, characterized in that In the step of forming an injection window in the barrier layer at the chip area and the scribe groove area, wherein the injection window is located between adjacent trench gates, the width of the injection window formed in the barrier layer at the scribe groove area is smaller than the width of the injection window formed in the barrier layer at the chip area.
3. The method for manufacturing a super junction device according to claim 1, wherein: In the step of sequentially forming an oxide layer, a first hard mask layer and a barrier layer on the semiconductor base layer, the thickness of the first hard mask layer is 1000A to 1500A.
4. The method for manufacturing a super junction device according to claim 1, wherein: In the step of sequentially forming an oxide layer, a first hard mask layer and a barrier layer on the semiconductor base layer, the thickness of the barrier layer is 4 um to 6 um.
5. The method for manufacturing a super junction device according to claim 1, wherein: In the step of etching and thinning the first hard mask layer exposed from the implantation window to form a second hard mask layer, the thickness of the second hard mask layer is 300 Å to 400 Å.
6. The method for manufacturing a super junction device according to claim 1, wherein: The step of performing ion implantation to implant ions through the implantation window and the second hard mask layer into the semiconductor base layer at the chip area and the scribe groove area to form a super junction doping column includes: Ion implantation is performed at an energy of 3000Kev to 4000Kev, and the implanted ions pass through the implantation window and the second hard mask layer into the semiconductor base layer at the chip region and the scribe groove region to form a super junction doping column.