Power device and preparation method thereof

Abstract

The invention discloses a power device and a preparation method thereof. The power device is characterized in that a doped nitride semiconductor layer covers part of a barrier layer; the first strain layer is positioned on one side, far away from the substrate, of the doped nitride semiconductor layer, and covers the surface, far away from the substrate, of the doped nitride semiconductor layer; the spacing layer covers the first strain layer; the second strain layer covers the surface, away from the substrate, of the spacing layer, the side wall of the spacing layer, the side wall of the first strain layer, the side wall of the doped nitride semiconductor layer and part of the barrier layer; the passivation structure is located on the side, away from the substrate, of the second strain layer; the vertical projection of the first through hole in the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer; the gate metal is located in the first through hole and is in contact with the doped nitride semiconductor layer. The performance and reliability of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof. Background Art

[0002] In the existing gate-last (GT last) design of power devices, the source and drain are usually first formed into an ohmic contact through heat treatment; then a gate opening (GO) process is used and gate metal is deposited to form a Schottky contact with the doped nitride semiconductor layer, and then activated through heat treatment. The doped nitride semiconductor layer is easily damaged during the opening process, affecting the performance and reliability of the device. Summary of the invention

[0003] The invention provides a power device and a preparation method thereof, which can improve the performance and reliability of the device.

[0004] According to one aspect of the present invention, there is provided a power device, comprising:

[0005] A substrate, a channel layer, a barrier layer and a doped nitride semiconductor layer are stacked in sequence; the doped nitride semiconductor layer covers a portion of the barrier layer;

[0006] A first strained layer, the first strained layer is located at a side of the doped nitride semiconductor layer away from the substrate, and the first strained layer covers a surface of the doped nitride semiconductor layer away from the substrate;

[0007] A spacer layer, the spacer layer is located on a side of the first strained layer away from the substrate; the spacer layer covers the first strained layer;

[0008] a second strained layer, the second strained layer being located on a side of the spacer layer away from the substrate, the second strained layer covering a surface of the spacer layer away from the substrate, a side wall of the spacer layer, a side wall of the first strained layer, a side wall of the doped nitride semiconductor layer and a portion of the barrier layer;

[0009] A passivation structure, the passivation structure is located on a side of the second strained layer away from the substrate;

[0010] A first through hole and a gate metal, the first through hole is located on a surface of the passivation structure away from the substrate, and a vertical projection of the first through hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer; the gate metal is at least located in the first through hole and in contact with the doped nitride semiconductor layer.

[0011] Optionally, the passivation structure includes a first passivation layer, a second passivation layer and a third passivation layer;

[0012] The second passivation layer is located between the first passivation layer and the third passivation layer. The third passivation layer is located on a side of the first passivation layer away from the substrate. The first passivation layer covers the second strained layer.

[0013] Optionally, the power device further includes:

[0014] a first field plate, the first field plate being located between the first passivation layer and the second passivation layer, the vertical projection of the first field plate on the substrate not overlapping with the vertical projection of the doped nitride semiconductor layer on the substrate; the second passivation layer covering the first field plate and a portion of the first passivation layer;

[0015] The second field plate is located on a side of the third passivation layer away from the substrate; the vertical projection of the second field plate on the first field plate covers part of the first field plate, and the second field plate extends in a direction away from the doped nitride semiconductor layer from the first field plate.

[0016] Optionally, the power device further includes:

[0017] A second through hole and a third through hole, wherein the third through hole is located on a side of the first through hole away from the second through hole; the second through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; the third through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer;

[0018] The source metal and the drain metal, the source metal is at least located in the second through hole and in contact with the barrier layer; the drain metal is at least located in the third through hole and in contact with the barrier layer.

[0019] Optionally, the source metal and the drain metal are made of the same material;

[0020] The material of the spacer layer includes silicon nitride or silicon oxynitride.

[0021] According to another aspect of the present invention, there is provided a method for preparing a power device, comprising:

[0022] forming a channel layer on one side of the substrate;

[0023] forming a barrier layer on a side of the channel layer away from the substrate;

[0024] Forming a doped nitride semiconductor material layer on a side of the barrier layer away from the channel layer; wherein the doped nitride semiconductor material layer covers the barrier layer;

[0025] forming a spacer layer;

[0026] Etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer;

[0027] forming a second strained material layer on a side of the spacer layer away from the substrate;

[0028] forming a passivation structure on a side of the second strained material layer away from the substrate;

[0029] A first through hole, a first strained layer and a second strained layer are formed; the first strained layer is located on a side of the doped nitride semiconductor layer away from the substrate, and the first strained layer covers the surface of the doped nitride semiconductor layer away from the substrate; the spacer layer is located on a side of the first strained layer away from the substrate; the spacer layer covers the first strained layer; the second strained layer is located on a side of the spacer layer away from the substrate, and the second strained layer covers the surface of the spacer layer away from the substrate, the sidewall of the spacer layer, the sidewall of the first strained layer, the sidewall of the doped nitride semiconductor layer and part of the barrier layer; the first through hole is located on a surface of the passivation structure away from the substrate, and the vertical projection of the first through hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer;

[0030] A gate metal is formed at least in the first through hole; the gate metal is in contact with the doped nitride semiconductor layer.

[0031] Optionally, before forming the spacer layer, the method further includes:

[0032] forming a third strained material layer on a side of the doped nitride semiconductor material layer away from the substrate; the third strained material layer covers the doped nitride semiconductor material layer;

[0033] forming a virtual gate material layer on a side of the third strained material layer away from the substrate; the virtual gate material layer covers the third strained material layer;

[0034] removing a portion of the third strained material layer and a portion of the dummy gate material layer to form a third strained layer and a dummy gate;

[0035] A first strained sublayer is formed on a side of the virtual gate away from the substrate; the first strained sublayer covers a surface of the virtual gate away from the substrate, a sidewall of the virtual gate, a sidewall of the third strained layer and a portion of the doped nitride semiconductor material layer;

[0036] Forming a spacer material layer on a side of the first strained sublayer away from the substrate; the spacer material layer covers the first strained sublayer;

[0037] A spacer layer is formed, comprising:

[0038] The spacer material layer and the first strained sublayer are etched to form a spacer layer and a first strained sublayer; the first strained sublayer covers the sidewall of the virtual gate, the sidewall of the third strained layer 03 and a part of the doped nitride semiconductor material layer;

[0039] While forming the first through hole, the method further comprises:

[0040] The third strained layer and the dummy gate are removed.

[0041] Optionally, a passivation structure is formed on a side of the second strained material layer away from the substrate, comprising:

[0042] forming a first passivation layer on a side of the second strained material layer away from the substrate; the first passivation layer covers the second strained material layer;

[0043] forming a second passivation layer on a side of the first passivation layer away from the substrate;

[0044] forming a third passivation layer on a side of the second passivation layer away from the substrate;

[0045] After forming a first passivation layer on a side of the second strained material layer away from the substrate, the method further includes:

[0046] A first field plate is formed on a side of the first passivation layer away from the substrate; a vertical projection of the first field plate on the substrate does not overlap with a vertical projection of the doped nitride semiconductor layer on the substrate;

[0047] While forming the gate metal at least in the first through hole, the method further comprises:

[0048] A second field plate is formed; the second field plate is located on a side of the third passivation layer away from the substrate, the vertical projection of the second field plate on the first field plate covers part of the first field plate, and the second field plate extends in a direction away from the doped nitride semiconductor layer from the first field plate.

[0049] Optionally, forming the first through hole, the first strained layer, and the second strained layer includes:

[0050] A first sub-hole is formed; a vertical projection of the first sub-hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first sub-hole penetrates the passivation structure, the second strained material layer and a portion of the virtual gate;

[0051] The dummy gate, the first strained sub-layer 2 of the dummy gate side wall, part of the second strained layer and the third strained layer are removed to form a first through hole, a first strained layer and a second strained layer.

[0052] Optionally, after forming a second passivation layer on a side of the first passivation layer away from the substrate, the method further includes:

[0053] A second through hole and a third through hole are formed at the same time; the third through hole is located on a side of the first through hole away from the second through hole; the second through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; the third through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer;

[0054] A source metal is formed at least in the second through hole, and a drain metal is formed at least in the third through hole; the source metal contacts the barrier layer, and the drain metal contacts the barrier layer.

[0055] In the power device provided by the technical solution of the embodiment of the present invention, the first strained layer is located on the side of the doped nitride semiconductor layer away from the substrate, and the first strained layer covers the surface of the doped nitride semiconductor layer away from the substrate; the spacer layer is located on the side of the first strained layer away from the substrate; the spacer layer covers the first strained layer; the second strained layer is located on the side of the spacer layer away from the substrate, and the second strained layer covers the surface of the spacer layer away from the substrate, the side wall of the spacer layer, the side wall of the first strained layer, the side wall of the doped nitride semiconductor layer and part of the barrier layer; the passivation structure is located on the side of the second strained layer away from the substrate; the first through hole is located on the surface of the passivation structure away from the substrate, and the vertical projection of the first through hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer; the gate metal is at least located in the first through hole and contacts with the doped nitride semiconductor layer. The first strained layer and the second strained layer can increase the stress of the device, improve the two-dimensional electron gas concentration, and protect the doped nitride semiconductor layer away from the surface and side wall of the substrate; the side wall of the first through hole can be made smoother, the side wall of the gate metal is not damaged, and the gate metal leakage can be avoided, thereby improving the device performance and reliability.

[0056] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0058] Figure 1 It is a schematic diagram of the structure of a power device provided by an embodiment of the present invention.

[0059] Figure 2 It is a flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0060] Figure 3-Figure 14 It is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention.

[0061] Fig.15 This is a flow chart of another method for preparing a power device provided in an embodiment of the present invention.

[0062] Fig.16 It is an intermediate flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0063] Fig.17 yes Figure 2 Detailed flow chart of S180. DETAILED DESCRIPTION

[0064] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0065] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0066] An embodiment of the present invention provides a power device, Figure 1 is a schematic diagram of a power device provided by an embodiment of the present invention, with reference to Figure 1 The power device comprises: a substrate 10, a channel layer 20, a barrier layer 30 and a doped nitride semiconductor layer 40 which are stacked in sequence; the doped nitride semiconductor layer 40 covers a portion of the barrier layer 30;

[0067] A first strained layer 51, the first strained layer 51 is located at a side of the doped nitride semiconductor layer 40 away from the substrate 10, and the first strained layer 51 covers a surface of the doped nitride semiconductor layer 40 away from the substrate 10;

[0068] A spacer layer 60, the spacer layer 60 is located on a side of the first strained layer 51 away from the substrate 10; the spacer layer 60 covers the first strained layer 51;

[0069] A second strained layer 52, the second strained layer 52 is located on a side of the spacer layer 60 away from the substrate 10, and the second strained layer 52 covers a surface of the spacer layer 60 away from the substrate 10, a sidewall of the spacer layer 60, a sidewall of the first strained layer 51, a sidewall of the doped nitride semiconductor layer 40 and a portion of the barrier layer 30;

[0070] A passivation structure 70 , where the passivation structure 70 is located on a side of the second strained layer 52 away from the substrate 10 ;

[0071] A first through hole A1 and a gate metal 80, wherein the first through hole A1 is located on a surface of the passivation structure 70 away from the substrate 10, and a vertical projection of the first through hole A1 on the doped nitride semiconductor layer 40 is located within the doped nitride semiconductor layer 40; the first through hole A1 extends from the passivation structure 70 to the doped nitride semiconductor layer 40; the gate metal 80 is at least located within the first through hole A1 and in contact with the doped nitride semiconductor layer 40.

[0072] The substrate 10 may be a silicon substrate or a silicon carbide substrate; the material of the channel layer 20 may be a gallium nitride material; the material of the barrier layer 30 may be AlGaN. The doped nitride semiconductor layer 40 may be a P-type gallium nitride layer. The material of the first strained layer 51 and the second strained layer 52 can be aluminum nitride; the first strained layer 51 and the second strained layer 52 can be used to increase the stress of the device and improve the concentration of the two-dimensional electron gas. The first strained layer 51 can protect the doped nitride semiconductor layer 40 from the surface of the substrate, and the second strained layer 52 can protect the side wall of the doped nitride semiconductor layer 40; the spacer layer 60 can avoid damaging the side wall of the first through hole A1 when forming the first through hole A1, so that the side wall of the first through hole A1 is smooth, and avoids the rough profile of the gate metal 80 when the gate metal 80 is subsequently formed in the first through hole A1, causing the gate metal 80 to leak; the spacer layer 60 can make the side wall of the first through hole A1 smoother, so that the side wall of the gate metal 80 is not damaged, and the gate metal 80 can be prevented from leaking, thereby improving the device performance and reliability.

[0073] In the process of forming the gate metal 80, it is necessary to first form a first through hole A1, and the first through hole A1 extends from the passivation structure 70 to the doped nitride semiconductor layer 40; in the process of forming the device, the through hole can be firstly dry-etched to form a first sub-hole, and a third strained layer can be set as an etching stop layer for etching the bottom of the first sub-hole by a dry etching process, and an etching stop layer is set on the side wall of the first sub-hole, and the etching stop layer of the side wall of the first sub-hole can be formed at the same time as the first strained layer, and the etching stop layer of the side wall is located between the first sub-hole and the spacer layer 60; the vertical projection of the third strained layer on the doped nitride semiconductor layer 40 is the same as the vertical projection of the first sub-hole on the doped nitride semiconductor layer 40. The vertical projections of the doped nitride semiconductor layer 40 overlap, which can avoid dry etching to damage the doped nitride semiconductor layer 40; then the third strained layer and the etching stop layer of the side wall are removed by wet etching to form the first through hole A1. The wet etching will not affect the doped nitride semiconductor layer 40 and the spacer layer 60. The spacer layer 60 can avoid damaging the side wall of the first through hole A1 during wet etching, so that when the first through hole A1 is formed, the surface of the doped nitride semiconductor layer 40 and the spacer layer 60 is smooth, and the rough profile of the subsequent gate metal 80 can be avoided to cause the gate metal 80 to leak, thereby improving the device performance and reliability.

[0074] In the power device provided by the technical solution of the embodiment of the present invention, the first strained layer 51 is located on the side of the doped nitride semiconductor layer 40 away from the substrate 10, and the first strained layer 51 covers the surface of the doped nitride semiconductor layer 40 away from the substrate 10; the spacer layer 60 is located on the side of the first strained layer 51 away from the substrate 10; the spacer layer 60 covers the first strained layer 51; the second strained layer 52 is located on the side of the spacer layer 60 away from the substrate 10, and the second strained layer 52 covers the surface of the spacer layer 60 away from the substrate 10, the sidewall of the spacer layer 60, and the first strained layer The first strained layer 51 and the second strained layer 52 are provided on the sidewall of the second strained layer 52 away from the substrate 10; the passivation structure 70 is located on the side of the second strained layer 52 away from the substrate 10; the first through hole A1 is located on the surface of the passivation structure 70 away from the substrate 10, and the vertical projection of the first through hole A1 on the doped nitride semiconductor layer 40 is located in the doped nitride semiconductor layer 40; the first through hole A1 extends from the passivation structure 70 to the doped nitride semiconductor layer 40; the gate metal 80 is at least located in the first through hole A1 and in contact with the doped nitride semiconductor layer 40. The first strained layer 51 and the second strained layer 52 can increase the stress of the device, increase the concentration of the two-dimensional electron gas, and protect the surface and sidewall of the doped nitride semiconductor layer 40 away from the substrate; the sidewall of the first through hole A1 can be made smoother, so that the sidewall of the gate metal 80 is not damaged, and the gate metal 80 can be prevented from leaking electricity, thereby improving the performance and reliability of the device.

[0075] Optional, reference Figure 1The passivation structure 70 includes a first passivation layer 71, a second passivation layer 72 and a third passivation layer 73; the second passivation layer 72 is located between the first passivation layer 71 and the third passivation layer 73, and the third passivation layer 73 is located on a side of the first passivation layer 71 away from the substrate 10; the first passivation layer 71 covers the second strained layer 52.

[0076] The material of the first passivation layer 71 and the second passivation layer 72 may be silicon oxide; the first passivation layer 71 and the second passivation layer 72 are formed respectively mainly for the subsequent preparation of the first field plate, and the first passivation layer 71 and the second passivation layer 72 play the role of insulation isolation; the material of the third passivation layer 73 may be silicon nitride, and the third passivation layer 73 may be used as an etching stop layer. When wet etching is performed in the subsequent formation of the first through hole A1, the hydrofluoric acid (HF) used in the wet etching will not affect the third passivation layer 73, and the height of the third passivation layer 73 can be effectively avoided from being affected. The height of the third passivation layer 73 corresponds to the height of the subsequent second field plate. If the height of the third passivation layer 73 is affected, it will affect the electric field regulation. Therefore, the third passivation layer 73 can be set to effectively block the influence of the subsequent wet etching process on the height of the second field plate, thereby improving the device performance and reliability. The gate metal 80 fills the first through hole A1 and extends from the first through hole A1 to the surface of the third passivation layer 73 away from the substrate 10, thereby increasing the conductivity of the device.

[0077] Optional, reference Figure 1 , a first field plate 91, the first field plate 91 is located between the first passivation layer 71 and the second passivation layer 72, the vertical projection of the first field plate 91 on the substrate 10 does not overlap with the vertical projection of the doped nitride semiconductor layer 40 on the substrate; the second passivation layer 72 covers the first field plate 91 and a portion of the first passivation layer 71;

[0078] The second field plate 92 is located on the side of the third passivation layer 73 away from the substrate 10 ; the vertical projection of the second field plate 92 on the first field plate 91 covers part of the first field plate 91 , and the second field plate 92 extends in the direction away from the doped nitride semiconductor layer 40 from the first field plate 91 .

[0079] Among them, the first field plate 91 can adjust the electric field on one side of the gate metal 80 to prevent the device from being broken down due to excessive electric field. The material of the first field plate 91 can be titanium nitride. The second field plate 92 can further adjust the electric field to prevent the device from being broken down due to excessive electric field. The second field plate 92 is formed at the same time as the gate metal 80, and both are made of the same material, and the preparation process is simple.

[0080] Optional, reference Figure 1The power device further includes: a second through hole A2 and a third through hole A3, wherein the third through hole A3 is located on a side of the first through hole A1 away from the second through hole A2; the second through hole A2 penetrates the second strained layer 52, the first passivation layer 71 and the second passivation layer 72 to the barrier layer 30; the third through hole A3 penetrates the second strained layer 52, the first passivation layer 71 and the second passivation layer 72 to the barrier layer 30;

[0081] The source metal 101 and the drain metal 102 , the source metal 101 is at least located in the second through hole A2 and in contact with the barrier layer 30 ; the drain metal 102 is at least located in the third through hole A3 and in contact with the barrier layer 30 .

[0082] Among them, the second through hole A2 and the third through hole A3 can be formed simultaneously by the same process, which can reduce the process cost and improve the process preparation efficiency. Before forming the source metal 101 and the drain metal 102, a conductive layer 103 can be formed first. The conductive layer 103 is located on the surface of the second passivation layer 72 away from the substrate 10, and is at least located between the source metal 101 and the drain metal 102 and the second passivation layer 72. The conductive layer 103 can also extend from the side walls of the second through hole A2 and the third through hole A3 to the surface of part of the second passivation layer 72 away from the substrate 10, which can only prevent the metal ions of the source metal 101 and the drain metal 102 from diffusing on the side walls, causing the device to short-circuit, and improve the reliability of the device; the material of the conductive layer 103 includes titanium nitride; the source metal 101 and the drain metal 102 can be formed by the same material, and the process is simple.

[0083] Optional, reference Figure 1 The source metal 101 and the drain metal 102 are made of the same material; the spacer layer 60 is made of silicon nitride or silicon nitride oxide.

[0084] Among them, the source metal 101 and the drain metal 102 are made of the same material, the preparation process is simple, and it can further reduce the control of thin film deposition materials and reduce costs. The material of the spacer layer 60 includes silicon nitride or silicon oxynitride, which can avoid damaging the side wall of the first through hole A1 when a wet etching process is used when forming the first through hole A1, and avoid the rough outline of the gate metal 80 when the gate metal 80 is subsequently formed in the first through hole A1, causing the gate metal 80 to leak. The spacer layer 60 can make the side wall of the first through hole A1 smoother, so that the side wall of the gate metal 80 is not damaged, thereby improving the performance and reliability of the device. In the future, the gate metal, source metal and drain metal can be connected by metal wiring, and the gate metal, source metal and drain metal can be controlled by metal wiring to realize the metal interconnection between the device and the outside.

[0085] In the prior art, the gate opening process is a huge challenge to the existing preparation methods of power devices. Under-etching will cause the gate metal to be unable to contact the doped nitride semiconductor layer; over-etching will cause gate damage. The defects between the gate metal and the doped nitride semiconductor layer are mainly concentrated on the contact surface and the corner position, affecting the performance and reliability of the device; therefore, usually dry etching is used to etch to the interface above the doped nitride semiconductor layer close to the doped nitride semiconductor layer, and then the remaining structure is removed by wet etching; since the structure above the doped nitride semiconductor layer has uneven thickness due to process errors, and the etching speed of dry etching is uneven, the thickness of the residual structure above the doped nitride semiconductor layer will be different. At this time, an excessive amount of wet etching solution is needed to promote each other, but the uniformity of wet etching is not good, resulting in poor profile roughness, affecting device performance and reliability.

[0086] In order to solve the above problems, an embodiment of the present invention provides a method for preparing a power device based on the above embodiments, which is used to prepare the power device described in any embodiment of the present invention and improve the performance and reliability of the power device. Figure 2 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, Figure 3-Figure 14 is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention, with reference to Figure 2-Figure 14 , the preparation method comprises:

[0087] S110 , forming a channel layer on one side of the substrate.

[0088] Among them, reference Figure 3 , a channel layer 20 may be epitaxially grown on one side of the substrate 10; the channel layer 20 covers the substrate 10. The material of the substrate 10 may be silicon or silicon carbide; the material of the channel layer 20 may be gallium nitride material.

[0089] S120 , forming a barrier layer on a side of the channel layer away from the substrate.

[0090] Among them, reference Figure 3 The material of the barrier layer 30 may be AlGaN, and the barrier layer 30 may be epitaxially grown on a side of the channel layer 20 away from the substrate 10 , and the barrier layer 30 covers the channel layer 20 .

[0091] S130, forming a doped nitride semiconductor material layer on a side of the barrier layer away from the channel layer; wherein the doped nitride semiconductor material layer covers the barrier layer.

[0092] Among them, reference Figure 3 The doped nitride semiconductor material layer 41 may be a P-type gallium nitride layer.

[0093] S140, forming a spacer layer.

[0094] This step is Fig.15 Detailed description is given in S200-S141.

[0095] S150, etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer.

[0096] Among them, reference Figure 7 , a doped nitride semiconductor layer is formed by an etching process, wherein the doped nitride semiconductor layer covers a portion of the barrier layer 30 , and the remaining portion of the barrier layer 30 is exposed.

[0097] S160 , forming a second strained material layer on a side of the spacer layer away from the substrate.

[0098] Among them, reference Figure 8 , a second strained material layer 521 is formed by a deposition process.

[0099] S170 , forming a passivation structure on a side of the second strained material layer away from the substrate.

[0100] The passivation structure may be formed by a deposition process.

[0101] S180, forming a first through hole, a first strained layer and a second strained layer; the first strained layer is located on a side of the doped nitride semiconductor layer away from the substrate, and the first strained layer covers the surface of the doped nitride semiconductor layer away from the substrate; the spacer layer is located on a side of the first strained layer away from the substrate; the spacer layer covers the first strained layer; the second strained layer is located on a side of the spacer layer away from the substrate, and the second strained layer covers the surface of the spacer layer away from the substrate, the sidewall of the spacer layer, the sidewall of the first strained layer, the sidewall of the doped nitride semiconductor layer and part of the barrier layer; the first through hole is located on a surface of the passivation structure away from the substrate, and the vertical projection of the first through hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer.

[0102] This step is Fig.17 Detailed description is given in S181-S182.

[0103] S190, forming a gate metal at least in the first through hole; the gate metal is in contact with the doped nitride semiconductor layer.

[0104] Among them, the gate metal and the second field plate are formed simultaneously by depositing metal, and the second field plate is formed on the side of the third passivation layer away from the substrate; the vertical projection of the second field plate on the first field plate covers part of the first field plate, and the second field plate extends in the direction of the first field plate away from the doped nitride semiconductor layer.

[0105] The method for preparing a power device provided by the technical solution of the embodiment of the present invention can make the side wall of the first through hole smoother, so that the side wall of the gate metal is not damaged, and the gate metal leakage can be avoided, thereby improving the device performance and reliability.

[0106] Optional, Fig.15 is a flowchart of another method for preparing a power device provided by an embodiment of the present invention, with reference to Fig.15 , the preparation method comprises:

[0107] S110 , forming a channel layer on one side of the substrate.

[0108] S120 , forming a barrier layer on a side of the channel layer away from the substrate.

[0109] S130, forming a doped nitride semiconductor material layer on a side of the barrier layer away from the channel layer; wherein the doped nitride semiconductor material layer covers the barrier layer.

[0110] S200, forming a third strained material layer on a side of the doped nitride semiconductor material layer away from the substrate; the third strained material layer covers the doped nitride semiconductor material layer.

[0111] Among them, reference Figure 3 , a third strained material layer 01 is deposited by a deposition process, and the third strained material layer 01 may be an aluminum nitride layer.

[0112] S210 , forming a virtual gate material layer on a side of the third strained material layer away from the substrate; the virtual gate material layer covers the third strained material layer.

[0113] Among them, reference Figure 3 The virtual gate material layer 02 is deposited by a plasma enhanced chemical vapor deposition process, and the material of the virtual gate material layer 02 can be silicon oxide.

[0114] S220 , removing a portion of the third strained material layer and a portion of the dummy gate material layer to form a third strained layer and a dummy gate.

[0115] Among them, reference Figure 4, a portion of the third strained material layer 01 and a portion of the dummy gate material layer 02 are removed by photolithography, etching, deposition and other processes to form a third strained layer 03 and a dummy gate 04. The vertical projection of the third strained layer on the doped nitride semiconductor material layer and the vertical projection of the dummy gate on the doped nitride semiconductor material layer overlap, and the third strained material layer and the dummy gate can be completely removed when the first through hole is formed later.

[0116] S230, forming a first strained sublayer on a side of the virtual gate away from the substrate; the first strained sublayer covers a surface of the virtual gate away from the substrate, a sidewall of the virtual gate, a sidewall of the third strained layer and a portion of the doped nitride semiconductor material layer.

[0117] Among them, reference Figure 5 A first strain sublayer 511 is formed by a deposition process, and the material of the first strain sublayer 511 may be aluminum nitride.

[0118] S240, forming a spacer material layer on a side of the first strained sublayer away from the substrate; the spacer material layer covers the first strained sublayer.

[0119] Among them, reference Figure 6 , a spacer material layer 61 is deposited by a deposition process, and the material of the spacer material layer 61 may be silicon nitride or silicon nitride oxide.

[0120] S141, etching the spacer material layer and the first strained sublayer to form a spacer layer and a first strained sublayer; the first strained sublayer covers the sidewall of the virtual gate, the sidewall of the third strained layer and a part of the doped nitride semiconductor material layer.

[0121] Among them, reference Figure 6 and Figure 7 , the spacer material layer 61 and the first strain sublayer 511 are etched by a spacer process to form a spacer layer 60 and a first strain sublayer 512. The spacer process is performed by dry etching.

[0122] S150, etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer.

[0123] Among them, reference Figure 7 The doped nitride semiconductor material layer is dry-etched using the spacer layer 60 , the first strained sub-layer 512 and the virtual gate 04 as masks to form a doped nitride semiconductor layer 40 .

[0124] S160 , forming a second strained material layer on a side of the spacer layer away from the substrate.

[0125] Among them, reference Figure 8, a second strained material layer 521 is formed by a deposition process, and the second strained material layer 521 covers the virtual gate 04 and extends to the surface of the barrier layer 30 away from the substrate 10 .

[0126] S170 , forming a passivation structure on a side of the second strained material layer away from the substrate.

[0127] S180, forming a first through hole, a first strained layer and a second strained layer; the first strained layer is located on a side of the doped nitride semiconductor layer away from the substrate, and the first strained layer covers the surface of the doped nitride semiconductor layer away from the substrate; the spacer layer is located on a side of the first strained layer away from the substrate; the spacer layer covers the first strained layer; the second strained layer is located on a side of the spacer layer away from the substrate, and the second strained layer covers the surface of the spacer layer away from the substrate, the sidewall of the spacer layer, the sidewall of the first strained layer, the sidewall of the doped nitride semiconductor layer and part of the barrier layer; the first through hole is located on a surface of the passivation structure away from the substrate, and the vertical projection of the first through hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer.

[0128] Wherein, while forming the first through hole, the method further includes: removing the third strain layer and the dummy gate. The vertical projection of the third strain layer on the substrate and the vertical projection of the dummy gate on the substrate are located within the vertical projection of the first through hole on the substrate.

[0129] S190, forming a gate metal at least in the first through hole; the gate metal is in contact with the doped nitride semiconductor layer.

[0130] Optional, Fig.16 is an intermediate flow chart of a method for preparing a power device provided by an embodiment of the present invention, with reference to Fig.16 , Fig.16 The method includes the steps of forming a passivation structure, a first field plate, a second field plate, a source metal and a drain metal, and the preparation method includes:

[0131] S171 , forming a first passivation layer on a side of the second strained material layer away from the substrate; the first passivation layer covers the second strained material layer.

[0132] Among them, reference Fig. 9 , a first passivation layer 71 is formed by a deposition process, and a material of the first passivation layer 71 includes silicon oxide.

[0133] S172, forming a first field plate on a side of the first passivation layer away from the substrate; a vertical projection of the first field plate on the substrate does not overlap with a vertical projection of the doped nitride semiconductor layer on the substrate.

[0134] Among them, reference Fig.10, a whole layer of the first field plate can be formed on the side of the first passivation layer 71 away from the substrate 10 by thin film deposition, and then the first field plate 91 is formed by photolithography, etching and other methods.

[0135] S173, forming a second passivation layer on a side of the first passivation layer away from the substrate; the second passivation layer covers the first field plate and a portion of the first passivation layer.

[0136] Among them, reference Fig.11 , a second passivation layer 72 is formed by a deposition process, and a material of the second passivation layer 72 includes silicon oxide.

[0137] S174, forming a second through hole and a third through hole at the same time; the third through hole is located on a side of the first through hole away from the second through hole; the second through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; the third through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer.

[0138] Among them, reference Fig.11 , a second through hole A2 and a third through hole A3 are formed by an etching process.

[0139] S175, forming a source metal at least in the second through hole, and forming a drain metal at least in the third through hole; the source metal contacts the barrier layer, and the drain metal contacts the barrier layer.

[0140] Among them, reference Fig.11 By depositing metal, a conductive layer 103, a source metal 101 and a drain metal 102 are formed, thereby forming an ohmic contact.

[0141] S176, forming a third passivation layer on a side of the second passivation layer away from the substrate.

[0142] Among them, reference Fig.12 The third passivation layer 73 is formed by a deposition process. The material of the third passivation layer 73 includes silicon nitride. The third passivation layer 73 can cover the source metal 101, the drain metal 102 and a portion of the second passivation layer 72.

[0143] Optionally, while forming the gate metal at least in the first through hole, the method further comprises:

[0144] A second field plate is formed; the second field plate is located on a side of the third passivation layer away from the substrate, the vertical projection of the second field plate on the first field plate covers part of the first field plate, and the second field plate extends in a direction away from the doped nitride semiconductor layer from the first field plate.

[0145] The second field plate and the gate metal can be formed simultaneously, which can simplify the process flow.

[0146] Optional, Fig.17 yes Figure 2For detailed flow chart of S180, please refer to Fig.17 , S180, forming a first through hole, a first strained layer and a second strained layer, including:

[0147] S181, forming a first sub-hole; the vertical projection of the first sub-hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first sub-hole penetrates the passivation structure, the second strained material layer and part of the virtual gate.

[0148] Among them, reference Fig.13 The passivation structure 70, the second strained material layer 521 and most of the virtual gate are etched by a dry etching process. The third strained layer 03 and the first strained sub-layer 512 on the side wall of the virtual gate can be used as an etching stop layer for dry etching to avoid plasma damage to the surface of the doped nitride semiconductor layer during dry etching, which will cause the device performance (such as threshold voltage, Vt) and reliability (such as high temperature gate bias, HTGB) to fail to meet the requirements; due to the influence of process errors, part of the virtual gate will remain; so that when the device forms the first sub-hole A11, the doped nitride semiconductor layer will not be damaged, thereby improving the performance and reliability of the device.

[0149] S182, removing the dummy gate, the first strained sub-layer 2 of the dummy gate sidewall, a portion of the second strained layer and the third strained layer to form a first through hole, a first strained layer and a second strained layer.

[0150] Among them, reference Fig.14 , a wet etching process is used to remove the virtual gate, the first strained sub-layer 2, part of the second strained layer and the third strained layer on the side wall of the virtual gate to form a first through hole, a first strained layer and a second strained layer; hydrofluoric acid (HF) used in wet etching only removes the remaining part of the virtual gate, the first strained sub-layer 2, part of the second strained layer and the third strained layer, thereby forming a first through hole A1, and the wet etching will not affect the doped nitride semiconductor layer 40 and the spacer layer 60, and the spacer layer 60 can avoid damaging the side wall of the first through hole A1 during wet etching, so that the side wall of the first through hole A1 can be made smooth, and the roughness of the profile of the subsequent gate metal 80 is avoided, and the gate metal 80 is avoided from leaking, thereby improving the device performance and reliability.

[0151] refer to Figure 1 The first through hole A1 is formed by dry etching and wet etching, and the gate metal 80 and the second field plate 92 are subsequently formed by deposition, photolithography, etching, etc., and a heat treatment process is subsequently performed to form a Schottky junction between the contact surface of the gate metal 80 and the doped nitride semiconductor layer 40. The gate metal, the source metal, and the drain metal can be connected by metal wires, and the gate metal, the source metal, and the drain metal can be controlled by the metal wires to realize metal interconnection between the device and the outside.

[0152] The following is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, the preparation method specifically includes:

[0153] S1. Forming a channel layer on one side of a substrate.

[0154] S2. Form a barrier layer on a side of the channel layer away from the substrate.

[0155] S3. Forming a doped nitride semiconductor material layer on a side of the barrier layer away from the channel layer; wherein the doped nitride semiconductor material layer covers the barrier layer.

[0156] S4. Form a third strained material layer on a side of the doped nitride semiconductor material layer away from the substrate; the third strained material layer covers the doped nitride semiconductor material layer.

[0157] S5. Form a virtual gate material layer on a side of the third strained material layer away from the substrate; the virtual gate material layer covers the third strained material layer.

[0158] S6, removing part of the third strained material layer and part of the dummy gate material layer to form a third strained layer and a dummy gate.

[0159] S7, forming a first strained sublayer on the side of the virtual gate away from the substrate; the first strained sublayer covers the surface of the virtual gate away from the substrate, the sidewall of the virtual gate, the sidewall of the third strained layer and a portion of the doped nitride semiconductor material layer.

[0160] S8, forming a spacer material layer on a side of the first strained sublayer away from the substrate; the spacer material layer covers the first strained sublayer.

[0161] S9, etching the spacer material layer and the first strained sublayer to form a spacer layer and a first strained sublayer; the first strained sublayer covers the sidewall of the virtual gate, the sidewall of the third strained layer and a portion of the doped nitride semiconductor material layer.

[0162] S10, etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer.

[0163] S11, forming a second strained material layer on a side of the spacer layer away from the substrate; the second strained material layer covers the virtual gate and extends to a surface of the barrier layer away from the substrate;.

[0164] S12, forming a first passivation layer on a side of the second strained material layer away from the substrate; the first passivation layer covers the second strained material layer.

[0165] S13, forming a first field plate on a side of the first passivation layer away from the substrate; a vertical projection of the first field plate on the substrate does not overlap with a vertical projection of the doped nitride semiconductor layer on the substrate.

[0166] S14, forming a second passivation layer on a side of the first passivation layer away from the substrate; the second passivation layer covers the first field plate and a portion of the first passivation layer.

[0167] S15, forming a second through hole and a third through hole at the same time; the third through hole is located on a side of the first through hole away from the second through hole; the second through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; the third through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer.

[0168] S16, forming a source metal at least in the second through hole, and forming a drain metal at least in the third through hole; the source metal contacts the barrier layer, and the drain metal contacts the barrier layer.

[0169] S17. Form a third passivation layer on a side of the second passivation layer away from the substrate.

[0170] S18, forming a first sub-hole; the vertical projection of the first sub-hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; the first sub-hole penetrates the passivation structure, the second strained material layer and part of the virtual gate.

[0171] S19, removing the dummy gate, the first strained sub-layer 2 of the dummy gate sidewall, a portion of the second strained layer and the third strained layer to form a first through hole, a first strained layer and a second strained layer.

[0172] S20, forming a gate metal and a second field plate; forming a gate metal at least in the first through hole; the gate metal is in contact with the doped nitride semiconductor layer; forming a second field plate on a side of the third passivation layer away from the substrate; the vertical projection of the second field plate on the first field plate covers a portion of the first field plate, and the second field plate extends in a direction in which the first field plate is away from the doped nitride semiconductor layer.

[0173] In the method for preparing a power device provided by the technical solution of the embodiment of the present invention, during the entire process of forming the gate metal, a combination of dry etching and wet etching is used in the gate opening process, and the doped nitride semiconductor layer can be completely protected from plasma damage (plasma damage) caused by dry etching through the third strained layer and the first strained sub-layer of the virtual gate side wall, and precise control of the gate profile by wet etching is achieved through the spacer layer; and the introduction of the third passivation layer can effectively block the influence of wet etching on the height of the second field plate, thereby greatly improving the device performance and reliability.

[0174] The method for preparing the power device provided in the embodiment of the present invention has the same beneficial effects as the power device provided in any embodiment of the present invention.

[0175] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0176] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: include: A substrate, a channel layer, a barrier layer and a doped nitride semiconductor layer are stacked in sequence; the doped nitride semiconductor layer covers a portion of the barrier layer; a first strained layer, the first strained layer being located on a side of the doped nitride semiconductor layer away from the substrate, and the first strained layer covering a surface of the doped nitride semiconductor layer away from the substrate; a spacer layer, the spacer layer being located on a side of the first strained layer away from the substrate; The spacer layer covers the first strain layer; a second strained layer, the second strained layer being located on a side of the spacer layer away from the substrate, the second strained layer covering a surface of the spacer layer away from the substrate, a sidewall of the spacer layer, a sidewall of the first strained layer, a sidewall of the doped nitride semiconductor layer and a portion of the barrier layer; a passivation structure, the passivation structure being located on a side of the second strained layer away from the substrate; A first through hole and a gate metal, wherein the first through hole is located on a surface of the passivation structure away from the substrate, and a vertical projection of the first through hole on the doped nitride semiconductor layer is located within the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer; the gate metal is at least located within the first through hole and in contact with the doped nitride semiconductor layer.

2. The power device according to claim 1, characterized in that: The passivation structure comprises a first passivation layer, a second passivation layer and a third passivation layer; The second passivation layer is located between the first passivation layer and the third passivation layer, and the third passivation layer is located on a side of the first passivation layer away from the substrate; The first passivation layer covers the second strained layer.

3. The power device according to claim 2, characterized in that: Also includes: a first field plate, the first field plate being located between the first passivation layer and the second passivation layer, a vertical projection of the first field plate on the substrate not overlapping with a vertical projection of the doped nitride semiconductor layer on the substrate; the second passivation layer covering the first field plate and a portion of the first passivation layer; A second field plate, the second field plate is located on a side of the third passivation layer away from the substrate; a vertical projection of the second field plate on the first field plate covers a portion of the first field plate, and the second field plate extends in a direction in which the first field plate is away from the doped nitride semiconductor layer.

4. The power device according to claim 2, characterized in that: Also includes: a second through hole and a third through hole, wherein the third through hole is located on a side of the first through hole away from the second through hole; the second through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; the third through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; A source metal and a drain metal, wherein the source metal is at least located in the second through hole and in contact with the barrier layer; and the drain metal is at least located in the third through hole and in contact with the barrier layer.

5. The power device according to claim 4, characterized in that: The source metal and the drain metal are made of the same material; The material of the spacer layer includes silicon nitride or silicon oxynitride.

6. A method for preparing a power device, characterized in that: include: forming a channel layer on one side of the substrate; forming a barrier layer on a side of the channel layer away from the substrate; forming a doped nitride semiconductor material layer on a side of the barrier layer away from the channel layer; wherein the doped nitride semiconductor material layer covers the barrier layer; forming a spacer layer; Etching the doped nitride semiconductor material layer to form a doped nitride semiconductor layer; the doped nitride semiconductor layer covers a portion of the barrier layer; forming a second strained material layer on a side of the spacer layer away from the substrate; forming a passivation structure on a side of the second strained material layer away from the substrate; A first through hole, a first strained layer and a second strained layer are formed; the first strained layer is located on a side of the doped nitride semiconductor layer away from the substrate, and the first strained layer covers the surface of the doped nitride semiconductor layer away from the substrate; the spacer layer is located on a side of the first strained layer away from the substrate; the spacer layer covers the first strained layer; the second strained layer is located on a side of the spacer layer away from the substrate, and the second strained layer covers the surface of the spacer layer away from the substrate, the sidewall of the spacer layer, the sidewall of the first strained layer, the sidewall of the doped nitride semiconductor layer and part of the barrier layer; the first through hole is located on a surface of the passivation structure away from the substrate, and a vertical projection of the first through hole on the doped nitride semiconductor layer is located within the doped nitride semiconductor layer; the first through hole extends from the passivation structure to the doped nitride semiconductor layer; A gate metal is formed at least in the first through hole; the gate metal is in contact with the doped nitride semiconductor layer.

7. The method for preparing a power device according to claim 6, characterized in that: Before forming the spacer layer, it also includes: forming a third strained material layer on a side of the doped nitride semiconductor material layer away from the substrate; the third strained material layer covers the doped nitride semiconductor material layer; forming a virtual gate material layer on a side of the third strained material layer away from the substrate; the virtual gate material layer covers the third strained material layer; Removing part of the third strained material layer and part of the dummy gate material layer to form a third strained layer and a dummy gate; A first strained sublayer is formed on a side of the virtual gate away from the substrate; the first strained sublayer covers a surface of the virtual gate away from the substrate, a sidewall of the virtual gate, a sidewall of the third strained layer and a portion of the doped nitride semiconductor material layer; Forming a spacer material layer on a side of the first strained sublayer away from the substrate; the spacer material layer covers the first strained sublayer; A spacer layer is formed, comprising: Etching the spacer material layer and the first strained sublayer to form a spacer layer and a first strained sublayer; the first strained sublayer covers the sidewall of the virtual gate, the sidewall of the third strained layer 03 and part of the doped nitride semiconductor material layer; While forming the first through hole, the method further comprises: The third strained layer and the dummy gate are removed.

8. The method for preparing a power device according to claim 7, characterized in that: A passivation structure is formed on a side of the second strained material layer away from the substrate, comprising: forming a first passivation layer on a side of the second strained material layer away from the substrate; the first passivation layer covers the second strained material layer; forming a second passivation layer on a side of the first passivation layer away from the substrate; forming a third passivation layer on a side of the second passivation layer away from the substrate; After forming a first passivation layer on a side of the second strained material layer away from the substrate, the method further comprises: forming a first field plate on a side of the first passivation layer away from the substrate; a vertical projection of the first field plate on the substrate does not overlap with a vertical projection of the doped nitride semiconductor layer on the substrate; At least while forming the gate metal in the first through hole, the method further comprises: A second field plate is formed; the second field plate is located on a side of the third passivation layer away from the substrate, a vertical projection of the second field plate on the first field plate covers a portion of the first field plate, and the second field plate extends in a direction in which the first field plate is away from the doped nitride semiconductor layer.

9. The method for preparing a power device according to claim 7, characterized in that: Forming a first through hole, a first strained layer and a second strained layer, comprising: forming a first sub-hole; wherein a vertical projection of the first sub-hole on the doped nitride semiconductor layer is located in the doped nitride semiconductor layer; and the first sub-hole penetrates the passivation structure, the second strained material layer and a portion of the virtual gate; The dummy gate, the first strained sub-layer 2 of the dummy gate sidewall, a portion of the second strained layer and the third strained layer are removed to form a first through hole, a first strained layer and a second strained layer.

10. The method for preparing a power device according to claim 8, characterized in that: After forming a second passivation layer on a side of the first passivation layer away from the substrate, the method further comprises: A second through hole and a third through hole are formed at the same time; the third through hole is located on a side of the first through hole away from the second through hole; the second through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; the third through hole penetrates the second strained layer, the first passivation layer and the second passivation layer to the barrier layer; A source metal is formed at least in the second through hole, and a drain metal is formed at least in the third through hole; the source metal is in contact with the barrier layer, and the drain metal is in contact with the barrier layer.

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