Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a channel layer, a source / drain region, and a gate structure. The channel layer is located on the substrate, wherein the channel layer comprises silicon germanium. The source / drain region adjoins the channel layer. The gate structure is located on the channel layer, wherein the gate structure comprises a dielectric layer and a work function metal layer. The dielectric layer is located on the channel layer. The work function metal layer is located on the dielectric layer. The channel layer of the semiconductor device may apply an internal compressive force, increasing mobility of the channel and thus increasing the drive current of the transistor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] As is well known, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) utilizes a gate modulated conductivity channel of either N-type or P-type conductivity, and is therefore referred to as "NMOS" or "PMOS", respectively. In the operation of a MOSFET device, a higher drive current means better device performance. To increase the drive current of a MOSFET, a common approach is to apply a compressive force to the channel between the source / drain regions, and this can be accomplished in a variety of ways. Summary of the invention

[0003] One aspect of the present disclosure provides a semiconductor device.

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a channel layer, a source / drain region, and a gate structure. The channel layer is located on the substrate, wherein the channel layer includes silicon germanium. The source / drain region is adjacent to the channel layer. The gate structure is located on the channel layer, wherein the gate structure includes a dielectric layer and a work function metal layer. The dielectric layer is located on the channel layer. The work function metal layer is located on the dielectric layer.

[0005] In some embodiments of the present disclosure, the substrate has a lattice constant different from that of the channel layer.

[0006] In some embodiments of the present disclosure, the gate structure further includes an interface layer, which is located between the dielectric layer and the channel layer.

[0007] In some embodiments of the present disclosure, the interface layer partially overlaps the source / drain region in the vertical direction.

[0008] In some embodiments of the present disclosure, the gate structure further includes a filling layer, and the filling layer is located on the work function metal layer.

[0009] In some embodiments of the present disclosure, the semiconductor device further includes a capping layer, which is located between the channel layer and the gate structure.

[0010] In some embodiments of the present disclosure, the substrate includes silicon.

[0011] Another aspect of the present disclosure provides a semiconductor device.

[0012] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a channel layer, a source / drain region, and a gate structure. The channel layer is located on the substrate, wherein the channel layer includes silicon germanium and is configured to apply a compressive force. The source / drain region is adjacent to the channel layer. The gate structure is located on the channel layer.

[0013] In some embodiments of the present disclosure, the semiconductor device further includes an interlayer dielectric layer. The interlayer dielectric layer is located on the substrate and the gate structure.

[0014] In some embodiments of the present disclosure, an interlayer dielectric layer surrounds the gate structure.

[0015] In some embodiments of the present disclosure, the semiconductor device further includes a first conductive contact located on the source / drain region.

[0016] In some embodiments of the present disclosure, the semiconductor device further includes a second conductive contact located on the gate structure.

[0017] In some embodiments of the present disclosure, the first conductive contact includes tungsten, and the second conductive contact includes tungsten and cobalt.

[0018] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device.

[0019] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes forming source / drain regions on a substrate, growing a channel layer on the substrate, wherein the channel layer directly contacts the substrate and includes silicon germanium, and forming a gate structure on the channel layer.

[0020] In some embodiments of the present disclosure, growing a channel layer on a substrate includes simultaneously growing a channel layer on the substrate and a source / drain region and etching the channel layer to expose the source / drain region.

[0021] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes controlling the thickness of the channel layer.

[0022] In some embodiments of the present disclosure, forming a gate structure on the channel layer further includes forming a dielectric layer on the channel layer, forming a work function metal layer on the dielectric layer, and forming a filling layer on the work function metal layer.

[0023] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes forming an interlayer dielectric layer on the substrate and the gate structure.

[0024] In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes forming a plurality of openings in an interlayer dielectric layer, and forming a first conductive contact and a second conductive contact in the openings, respectively, wherein the second conductive contact comprises a material different from that of the first conductive contact.

[0025] In the aforementioned embodiments of the present disclosure, since the channel layer includes silicon germanium, which has a larger lattice constant than the substrate including silicon, the channel layer can exert an internal compressive force to increase the mobility of the channel and thus increase the driving current of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] When accompanied by Figure 1 When read together, the aspects of the present disclosure can be best understood from the following embodiments. Note that according to standard practice in this industry, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0027] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure.

[0028] Figure 2 to Figure 3 for Figure 1 A cross-sectional view of a semiconductor device in an intermediate step of a manufacturing method according to an embodiment of the present disclosure.

[0029] Figure 4 for Figure 3 Critical thickness of the channel layer versus germanium content in Fig.

[0030] Figures 5 to 11 for Figure 1 Method for manufacturing semiconductor device in Figure 3 A cross-sectional view of the intermediate steps that follow. DETAILED DESCRIPTION

[0031] The following disclosure provides many different embodiments or examples for implementing the different features of the described subject matter. Specific examples of components and configurations are described below to simplify this specification. Of course, these are merely examples and are not restrictive. For example, forming a first feature on or above a second feature in the subsequent description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or reference letters in multiple examples. Such repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the multiple embodiments and / or configurations discussed.

[0032] Spatially relative terms such as "below," "beneath," "bottom," "above," "top," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0033] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1, the semiconductor device 100 includes a substrate 110, a channel layer 120, at least one source / drain region 112, and a gate structure 140. The channel layer 120 is directly located on the substrate 110, wherein the channel layer 120 includes silicon germanium (SiGe) and is configured to apply a compressive force. The source / drain region 112 is adjacent to both sides of the channel layer 120. The gate structure 140 is located on the channel layer 120, wherein the gate structure includes a dielectric layer 144, a work function metal layer 146, and a filling layer 148. The dielectric layer 144 is located on the channel layer 120. The work function metal layer 146 is located on the dielectric layer 144. The filling layer 148 is located on the work function metal layer 146. Generally speaking, the semiconductor device 100 is often referred to as a high-k metal gate (HKMG) PMOS transistor, wherein the dielectric layer 144 includes a dielectric material having a dielectric constant greater than 3.9. Such dielectric materials include hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), lanthanum oxide (La2O3), cerium oxide (CeO2), bismuth silicate (Bi2Si2O 12 ), tungsten oxide (WO3), yttrium oxide (Y2O3), lanthanum aluminate (LaAlO-3), barium strontium titanate (Ba x Sr x TiO3), strontium titanate (SrTiO-3), lead zirconate (SrTiO-3), lead scandium titanate (PbZrO3), lead zirconate titanate (PST), lead zinc niobate (PZN), lead zirconate titanate (PZT), lead magnesium niobate (PMN), or a combination thereof. For example, the dielectric constant of hafnium oxide is in the range of 16 to 19.

[0034] During operation of the semiconductor device 100, the compressive force applied to the channel layer 120 can significantly increase the carrier mobility of the channel, thereby increasing the drive current. d satisfy

[0035] I d =1 / 2μ n C ox (W / L)(V gs -V t )…Eq.

[0036] where μ n is the carrier mobility of the channel, C ox is the capacitance density, W represents the channel width, L represents the channel length, V gs is the gate-source voltage of the semiconductor device 100, V tis the threshold voltage of the semiconductor device 100. This equation shows that the carrier mobility of the channel is proportional to the drive current. In the present embodiment, the method of applying a compressive force to the channel layer 120 is by growing an epitaxial SiGe channel layer 120 on the substrate 110. Therefore, the substrate 110 has a different lattice constant from the channel layer 120, wherein the substrate 110 includes silicon and the channel layer 120 includes silicon germanium. Due to the larger lattice constant of the epitaxial SiGe when grown on the silicon-based substrate 110, the channel layer 120 including SiGe can apply a compressive force, thereby improving the carrier mobility of the channel layer 120.

[0037] Refer to Figure 1 , the gate structure 140 further includes an interface layer 142. The interface layer 142 is located between the dielectric layer 144 and the channel layer 120. The interface layer 142 partially overlaps the source / drain region 112 in the vertical direction. The interface layer 142 includes silicon dioxide or a similar dielectric material. In some embodiments, the gate structure 140 may further include a spacer structure (not shown) to obtain better electrical isolation between the gate structure 140 and the source / drain region 112. In some embodiments, the semiconductor device 100 further includes a cap layer 130, an interlayer dielectric (ILD) layer 150, two first conductive contacts 160 and a second conductive contact 170. The cap layer 130 is located between the channel layer 120 and the gate structure 140. The interlayer dielectric layer 150 is located between the substrate 110 and the gate structure 140 and surrounds the gate structure 140. The two first conductive contacts 160 are respectively located on each source / drain region 112. The second conductive contact 170 is located on the gate structure 140, wherein the second conductive contact 170 comprises a different material from the first conductive contact 160. In the present embodiment, the second conductive contact 170 is a double-layer structure having a bottom contact 172 and a top contact 174. In some embodiments, the first conductive contact 160 comprises tungsten (W) and the second conductive contact comprises tungsten and cobalt (Co).

[0038] It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, but will be described first. In the following description, a method for manufacturing the semiconductor device 100 will be described.

[0039] Figure 2 to Figure 3 for Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 100 in an intermediate step of a manufacturing method according to an embodiment of the present disclosure. Figure 2 , a method for manufacturing a semiconductor device 100 includes forming a source / drain region 112 in a substrate 110. The source / drain region 112 may be formed by using a deposition technique, such as chemical vapor deposition (CVD), metal-oxide chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), ion implantation, combinations thereof, or other similar methods.

[0040] Reference Figure 3 Then, a channel layer 120 is grown on the substrate 110, wherein the channel layer 120 directly contacts the substrate 110 and comprises silicon germanium. The channel layer 120 may be an epitaxial layer. In some embodiments, this step includes synchronously growing the channel layer 120 on the substrate 110 and on the source / drain region 112 and etching the channel layer 120 so that the source / drain region 112 is exposed. This step is called "selective etching" of the epitaxial layer, wherein the above two steps (epitaxial growth and etching) are performed simultaneously, thereby "selectively" forming the channel layer 120 only on the exposed portion of the substrate 110. Optimally, the etching rate and the growth rate are controlled so that the channel layer 120 does not grow on the source / drain region 112. In this embodiment, this step also includes a pre-cleaning step before the selective etching step. Such a pre-cleaning step includes a wet cleaning step and a baking step to clean the surface of the substrate 110 and to allow the channel layer 120 to grow directly on the substrate 110. The etching process is performed with hydrogen chloride (HCl) gas and is an in-situ process.

[0041] Figure 4 for Figure 3 Critical thickness-germanium content diagram of the channel layer 120 in FIG. Figure 4 When the channel layer 120 is grown, the thickness affects the performance of the channel layer 120, so the thickness of the channel layer 120 should be controlled. If the thickness is greater than the critical thickness (the upper edge of the steady-state region), SiGe epitaxy will form dislocations due to strain relaxation of the compressed lattice, which will cause the desired compressive force applied to the channel layer 120 to decrease. By controlling the temperature and the ratio of silicon to germanium in the epitaxial process, the critical thickness can be increased at low growth temperature and low germanium concentration, so that the thickness of the channel layer 120 can be controlled within a larger tolerance range. In addition, the exposed area of ​​the substrate 110 can also make the process change. If the exposed area of ​​the substrate 110 is too small, the gas concentration in the epitaxial process needs to be maintained at a lower concentration to avoid the thickness exceeding the critical thickness. In addition, the etching process needs to consider the loading effect, in which the density of the pattern to be grown needs to be designed to be consistent to avoid the difference in etching rate between dense areas and thin areas, and have a consistent thickness of the channel layer 120.

[0042] Figures 5 to 11 for Figure 1 Method for manufacturing semiconductor device in Figure 3 Cross-section diagram of the intermediate steps. Figure 5 ,exist Figure 3 After the step of forming the channel layer 120, a capping layer 130 is formed on the channel layer 120. In some embodiments, the capping layer 130 includes silicon.

[0043] Reference Figure 6Then, an interface layer 142 is formed on the cap layer 130, wherein the interface layer 142 partially overlaps the source / drain region 112 in a vertical direction. In some embodiments, the interface layer 142 includes silicon dioxide and can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In some embodiments, forming the interface layer 142 further includes a patterning process.

[0044] Reference Figure 7 Next, a dielectric layer 144 is formed on the interface layer 142. The dielectric layer 144 includes a high-k dielectric material and may be formed by using chemical vapor deposition (CVD), metal-oxide chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0045] Reference Figure 8 and Fig. 9 , then, a work function metal layer 146 is formed on the dielectric layer 144. Then, a filling layer 148 is formed on the work function metal layer 146, thereby forming the gate structure 140. The work function metal layer 146 includes a material such as titanium nitride (TiN) and can be formed by using atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The filling layer 148 includes a material such as polysilicon.

[0046] Reference Fig.10 and Fig.11 Then, an interlayer dielectric layer 150 is formed on the substrate 110 and the gate structure 140. The interlayer dielectric layer 150 may include, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), undoped silicate glass (USG), silicon dioxide (SiO x C y ), spin-on glass (SOG), spin-on polymer, carbon-doped silicon material, a combination thereof or similar materials, and can be formed by spin coating, chemical vapor deposition or other similar methods. Next, an opening 210 is formed in the interlayer dielectric layer 150 .

[0047] Reference Figure 1 Then, a first conductive contact 160 and a second conductive contact 170 are formed in the openings respectively, wherein the second conductive contact 170 has a material different from that of the first conductive contact 160 .

[0048] In summary, since the channel layer 120 includes silicon germanium, which has a larger lattice constant than the substrate 110 including silicon, the channel layer 120 can exert an internal compressive force to increase the mobility of the channel and thus increase the driving current of the transistor.

[0049] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and constructions for achieving the same purpose and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may be variously changed, substituted, and modified herein without departing from the spirit and scope of the present disclosure.

[0050]

Explanation of symbols

[0051] 100:Semiconductor device

[0052] 110:Substrate

[0053] 112: Source / drain region

[0054] 120: Channel layer

[0055] 130: Covering layer

[0056] 140: Gate structure

[0057] 142: Interface layer

[0058] 144: Dielectric layer

[0059] 146: Work function metal layer

[0060] 148: Filling layer

[0061] 150: interlayer dielectric layer

[0062] 160: first conductive contact

[0063] 170: second conductive contact

[0064] 172: Bottom contact

[0065] 174: Top contact

[0066] 210: Speak.

Claims

1. A semiconductor device, characterized in that: Include: substrate; A channel layer is located on the substrate, wherein the channel layer comprises silicon germanium; a source / drain region adjacent to the channel layer; as well as A gate structure is located on the channel layer, wherein the gate structure comprises: a dielectric layer, located on the channel layer; as well as The work function metal layer is located on the dielectric layer.

2. The semiconductor device according to claim 1, characterized in that The substrate has a different lattice constant than the channel layer.

3. The semiconductor device according to claim 1, wherein The gate structure also includes: The interface layer is located between the dielectric layer and the channel layer.

4. The semiconductor device according to claim 3, characterized in that The interface layer partially overlaps the source / drain region in a vertical direction.

5. The semiconductor device according to claim 1, wherein The gate structure also includes: The filling layer is located on the work function metal layer.

6. The semiconductor device according to claim 1, wherein: Also includes: The covering layer is located between the channel layer and the gate structure.

7. The semiconductor device according to claim 1, characterized in that The substrate includes silicon.

8. A semiconductor device, characterized in that: Include: substrate; a channel layer disposed on the substrate, wherein the channel layer comprises silicon germanium and is configured to apply a compressive force; a source / drain region adjacent to the channel layer; as well as A gate structure is located on the channel layer.

9. The semiconductor device according to claim 8, wherein: Also includes: The interlayer dielectric layer is located on the substrate and the gate structure.

10. The semiconductor device according to claim 9, characterized in that The interlayer dielectric layer is constructed around the gate.

11. The semiconductor device according to claim 8, wherein: Also includes: The first conductive contact is located on the source / drain region.

12. The semiconductor device according to claim 11, wherein: Also includes: The second conductive contact is located on the gate structure.

13. The semiconductor device according to claim 12, characterized in that The first conductive contact includes tungsten, and the second conductive contact includes tungsten and cobalt.

14. A method for manufacturing a semiconductor device, characterized in that: Include: forming source / drain regions on the substrate; growing a channel layer on the substrate, wherein the channel layer directly contacts the substrate and comprises silicon germanium; and A gate structure is formed on the channel layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein Growing the channel layer on the substrate comprises: The channel layer is grown on the substrate and the source / drain region simultaneously, and the channel layer is etched to expose the source / drain region.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: Also includes: Controls the thickness of this channel layer.

17. The method for manufacturing a semiconductor device according to claim 14, wherein Forming the gate structure on the channel layer further comprises: forming a dielectric layer on the channel layer; forming a work function metal layer on the dielectric layer; and A filling layer is formed on the work function metal layer.

18. The method for manufacturing a semiconductor device according to claim 17, wherein Forming the gate structure on the channel layer further comprises: Before forming the dielectric layer, an interface layer is formed on the channel layer, wherein the interface layer partially overlaps with the source / drain region in a vertical direction.

19. The method for manufacturing a semiconductor device according to claim 14, wherein: Also includes: An interlayer dielectric layer is formed on the substrate and the gate structure.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: Also includes: forming a plurality of openings in the interlayer dielectric layer; and A first conductive contact and a second conductive contact are formed in the plurality of openings respectively, wherein the second conductive contact comprises a material different from that of the first conductive contact.

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