P-channel GaN field effect transistor and preparation method thereof

Abstract

The invention relates to a p-channel GaN field effect transistor and a preparation method thereof, and belongs to the technical field of semiconductors, the p-channel GaN field effect transistor comprises an epitaxial wafer, the epitaxial wafer comprises a p-GaN layer, the p-GaN layer is provided with a source electrode, a drain electrode, a first connecting wall, a second connecting wall, a dielectric layer and a grid electrode, the source electrode and the drain electrode are electrically connected along a first direction through the first connecting wall, and the dielectric layer is electrically connected with the grid electrode through the second connecting wall. The source electrode, the drain electrode and the first connecting wall jointly define a groove, the groove extends in the second direction perpendicular to the first direction, the first side wall of the groove is located between the source electrode and the groove, the second side wall of the groove is located between the drain electrode and the groove, the bottom wall of the groove is located on the first connecting wall, the first connecting wall and the second connecting wall are arranged at an included angle, and the second connecting wall is located in the groove. The second connecting wall is electrically connected with the source electrode and the drain electrode, the dielectric layer covers the first connecting wall and the second connecting wall, and the grid electrode is laid on the dielectric layer. The conductive channels of the GaN field effect transistor comprise at least two types of conductive channels, the grid control capability is higher, and the output current is higher.

Description

Technical Field

[0001] The invention relates to a p-channel GaN field effect transistor and a preparation method thereof, belonging to the technical field of semiconductors. Background Art

[0002] Due to its high voltage resistance, high frequency, and radiation resistance, GaN has advantages that are difficult to replace by Si-based materials, and is expected to break through the bottleneck faced by Si-based materials. Due to its unique piezoelectric polarization effect, gallium-polar GaN has a net positive charge accumulation at the AlGaN / GaN interface, thereby attracting electrons to form a two-dimensional electron gas (2DEG). GaN field-effect transistors designed based on 2DEG are all n-channel, and p-channel construction is difficult. Due to the lack of effective p-channel GaN field-effect transistors, it is difficult to form CMOS-like structures such as inverters, NOR gates, NAND gates and other logic gate circuits, which limits the further development of GaN electronic devices in the field of integrated circuits. In the field of power electronics, the lack of effective p-channel GaN field-effect transistors also limits the further application of GaN in fields such as high-side switches. Summary of the invention

[0003] In view of the deficiencies of the prior art, one of the objectives of the present invention is to provide a p-channel GaN field effect transistor with stronger gate control capability; a second objective of the present invention is to provide a method for preparing a p-channel GaN field effect transistor.

[0004] In order to solve the above technical problems, the technical solution of the present invention is as follows:

[0005] The present embodiment provides a p-channel GaN field effect transistor, comprising an epitaxial wafer, the epitaxial wafer comprising a p-GaN layer, a source electrode, a drain electrode, a first connecting wall, a second connecting wall, a dielectric layer and a gate electrode are arranged on the p-GaN layer, the source electrode and the drain electrode are electrically connected along a first direction through the first connecting wall, and the source electrode, the drain electrode and the first connecting wall define a groove, the groove extends along a second direction perpendicular to the first direction, and the first side wall of the groove is located between the source electrode and the groove, the second side wall of the groove is located between the drain electrode and the groove, the bottom wall of the groove is located at the first connecting wall, the second connecting wall is located in the groove, the first connecting wall and the second connecting wall are arranged at an angle, and the second connecting wall is electrically connected to the source electrode and the drain electrode respectively, the dielectric layer covers the first connecting wall and the second connecting wall, and the gate electrode is laid on the dielectric layer.

[0006] Thus, a 3D and 2D structure combining a “planar groove” (first connecting wall) and a “sidewall fin gate” (second connecting wall) is formed, thereby effectively enhancing the gate control capability.

[0007] Furthermore, the second connecting wall has a first wall surface, a second wall surface, and a third wall surface, the first wall surface is respectively connected to the second wall surface and the third wall surface along the second direction, the first wall surface and the bottom wall of the groove are not in the same plane, the second wall surface intersects with the plane where the bottom wall of the groove is located, the third wall surface intersects with the plane where the bottom wall of the groove is located, and the gate covers the first connecting wall, the first wall surface, the second wall surface and the third wall surface.

[0008] Furthermore, the second wall surface is perpendicular to the first connecting wall.

[0009] Furthermore, the third wall surface is perpendicular to the first connecting wall.

[0010] Furthermore, the second wall surface is connected to the first connecting wall, or a gap is left between the second wall surface and the first connecting wall.

[0011] Furthermore, the number of the second connecting walls is at least one; when the number of the second connecting walls is at least two, the second connecting walls are spaced apart along the second direction.

[0012] Furthermore, the thicknesses of the second connecting walls are equal.

[0013] Furthermore, the epitaxial wafer also includes a substrate, a nucleation layer, a buffer layer, and an insulating layer. The nucleation layer, the buffer layer, the insulating layer and the p-GaN layer are stacked in sequence on the substrate, and the first connecting wall and the second connecting wall are located on the surface of the p-GaN layer away from the insulating layer.

[0014] Furthermore, an AlGaN layer and / or an AlN layer is disposed between the insulating layer and the p-GaN layer.

[0015] This embodiment also provides a method for preparing a p-channel GaN field effect transistor, comprising the following steps:

[0016] Providing epitaxial wafers;

[0017] Depositing a source electrode and a drain electrode on the epitaxial wafer, and performing annealing in an oxygen atmosphere;

[0018] forming a first connecting wall and a second connecting wall on the epitaxial wafer by photolithography and etching;

[0019] Growing a dielectric layer on the surfaces of the first connecting wall and the second connecting wall;

[0020] A gate is evaporated on the dielectric layer.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] (1) Different from the conventional p-channel GaN field effect transistor whose conductive channel is simply bottom conductive, the conductive channel of the GaN field effect transistor of the present invention includes at least two types of conductive channels, namely, the first connecting wall and the second connecting wall, and has a stronger conductive capability.

[0023] (2) The gate electrode of the p-channel GaN field effect transistor of the present invention forms a wrapping around the second connecting wall on at least three sides, and its gate control capability is stronger than that of the traditional p-channel GaN field effect transistor with only a groove gate structure, and the output current is higher. The gate electrode of the traditional structure only covers the plane.

[0024] (3) Due to the fluctuation of etching rate, the structure of the traditional p-channel GaN field effect transistor is easy to significantly change the conductivity of the bottom conductive channel (first connecting wall) due to over-etching or under-etching, so that the device performance is greatly affected by the etching process and the repeatability is poor. The p-channel GaN field effect transistor of the present invention adds at least one second connecting wall conductive channel, which can compensate for the process fluctuation of the bottom conductive channel (first connecting wall) to a certain extent, improve the repeatability and robustness of the p-channel GaN field effect transistor preparation process, and can also reduce the requirements for the control precision of various details of the preparation process, which is conducive to promotion and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the cross-sectional structure of an epitaxial wafer of the present invention.

[0026] Figure 2 It is a three-dimensional diagram of a device portion of a p-channel GaN field effect transistor of the present invention.

[0027] Figure 3 It is a top view of a device portion of a p-channel GaN field effect transistor of the present invention.

[0028] Figure 4 for Figure 2 and Figure 3 A cross-sectional view along a second direction perpendicular to the first direction.

[0029] Figure 5 is the transfer characteristic curve of the p-channel GaN field effect transistor of Example 1 of the present invention, wherein the horizontal axis is the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (I D ).

[0030] Figure 6 is the output characteristic curve of the p-channel GaN field effect transistor of Example 1 of the present invention, wherein the horizontal axis is the drain-source electrode voltage (V D ), the ordinate is the current between the drain and source electrodes (I D ).

[0031] Figure 7 It is a cross-sectional view of another device of the present invention along a second direction perpendicular to the first direction, and the second wall surfaces of the first connecting wall and the second connecting wall are not connected.

[0032] Figure 8 It is a top view of a device portion of another p-channel GaN field effect transistor of the present invention.

[0033] Fig. 9 is the transfer characteristic curve of the p-channel GaN field effect transistor of Example 2 of the present invention, wherein the horizontal axis is the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (I D ).

[0034] Fig.10 is the output characteristic curve of the p-channel GaN field effect transistor of Example 2 of the present invention, wherein the horizontal axis is the drain-source electrode voltage (V D ), the ordinate is the current between the drain and source electrodes (I D ).

[0035] Fig.11 It is a top view of a device portion of another p-channel GaN field effect transistor of the present invention.

[0036] Fig.12 is the transfer characteristic curve of the p-channel GaN field effect transistor of Example 3 of the present invention, wherein the horizontal axis is the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (I D ).

[0037] Fig.13 is the output characteristic curve of the p-channel GaN field effect transistor of Example 3 of the present invention, wherein the horizontal axis is the drain-source electrode voltage (V D ), the ordinate is the current between the drain and source electrodes (I D ).

[0038] Fig.14 It is a top view of a device portion of another p-channel GaN field effect transistor of the present invention.

[0039] Fig.15 is the transfer characteristic curve of the p-channel GaN field effect transistor of Example 4, wherein the horizontal axis is the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (I D ).

[0040] Fig.16 is the output characteristic curve of the p-channel GaN field effect transistor of Example 4, wherein the horizontal axis is the drain-source electrode voltage (V D), the ordinate is the current between the drain and source electrodes (I D ).

[0041] Fig.17 It is a top view of a device portion of another p-channel GaN field effect transistor of the present invention.

[0042] Fig.18 is the transfer characteristic curve of the p-channel GaN field effect transistor of Example 5, wherein the horizontal axis is the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (I D ).

[0043] Fig.19 is the output characteristic curve of the p-channel GaN field effect transistor of Example 5, wherein the horizontal axis is the drain-source electrode voltage (V D ), the ordinate is the current between the drain and source electrodes (I D ).

[0044] Fig. 20 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction.

[0045] Fig.21 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction, and the second wall surfaces of the first connecting wall and the second connecting wall are not connected.

[0046] Fig. 22 is the transfer characteristic curve of the p-channel GaN field effect transistor of Example 6, wherein the horizontal axis is the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (I D ).

[0047] Fig.23 is the output characteristic curve of the p-channel GaN field effect transistor of Example 6, wherein the horizontal axis is the drain-source electrode voltage (V D ), the ordinate is the current between the drain and source electrodes (I D ).

[0048] Fig.24 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction.

[0049] Fig.25 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction, and the second wall surfaces of the first connecting wall and the second connecting wall are not connected.

[0050] Fig.26It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction.

[0051] Fig. 27 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction, and the second wall surfaces of the first connecting wall and the second connecting wall are not connected.

[0052] Fig.28 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction.

[0053] Fig.29 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction, and the second wall surfaces of the first connecting wall and the second connecting wall are not connected.

[0054] Fig.30 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction.

[0055] Fig.31 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction, and the second wall surfaces of the first connecting wall and the second connecting wall are not connected.

[0056] Fig.32 It is a cross-sectional view of a device portion of another p-channel GaN field effect transistor of the present invention along a second direction perpendicular to the first direction.

[0057] Fig.33 A top view of a device portion of a conventional p-channel GaN field effect transistor.

[0058] Fig.34 The transfer characteristic curve of the p-channel GaN field effect transistor of comparative example 1, wherein the horizontal axis is the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (I D ).

[0059] Fig.35 The output characteristic curve of the p-channel GaN field effect transistor of comparative example 1 is shown in FIG. 1 , where the horizontal axis is the drain-source electrode voltage (V D ), the ordinate is the current between the drain and source electrodes (I D ).

[0060] Fig.36 The transfer characteristic curve of the p-channel GaN field effect transistor of comparative example 2 is shown in FIG. 1 , where the horizontal axis represents the gate-source electrode voltage (V GS ), the ordinate is the current between the drain and source electrodes (ID ).

[0061] Fig.37 is the output characteristic curve of the p-channel GaN field effect transistor of comparative example 2, wherein the abscissa is the drain-source electrode voltage (V D ), the ordinate is the current between the drain and source electrodes (I D ).

[0062] In the figure, 1-epitaxial wafer, 110-p-GaN layer, 120-insulating layer, 130-buffer layer, 140-nucleation layer, 150-substrate, 2-source, 3-drain, 4-first connecting wall, 410-first side wall, 420-second side wall, 430-bottom wall of groove, 5-second connecting wall, 510-first partition wall, 520-second partition wall, 511-first wall surface of the first partition wall, 512-second wall surface of the first partition wall, 513-third wall surface of the first partition wall, 521-first wall surface of the second partition wall, 522 second wall surface of the second partition wall, 523-third wall surface of the second partition wall, 6-dielectric layer, 7-gate, 8-gap. DETAILED DESCRIPTION

[0063] The present invention will be described in detail below in conjunction with the embodiments. It should be noted that the embodiments and features of the embodiments of the present invention can be combined with each other without conflict. For the convenience of description, if the words "upper", "lower", "left" and "right" appear in the following, they only indicate that the upper, lower, left and right directions are consistent with the drawings themselves, and do not limit the structure.

[0064] Example 1

[0065] The p-channel GaN field effect transistor of this embodiment includes an epitaxial wafer 1, which includes a substrate 150 (a single crystal silicon substrate, the surface of which is a silicon (111) crystal plane, and the substrate thickness is 1 mm), a nucleation layer 140 (an aluminum nitride nucleation layer, with a thickness of about 250 nm), a buffer layer 130 (an AlGaN layer with a step-wise change in Al component, the proportion of Al component in the total molar amount of Al and Ga gradually changes from 80% to 12%, and the total thickness is about 2.8 μm), an insulating layer 120 (a carbon-doped gallium nitride high-resistance layer, with a thickness of about 1 μm), a p-GaN layer 110 (a magnesium-doped GaN layer, with a hole concentration of about 1e17 cm 3 The nucleation layer 140 , the buffer layer 130 , the insulating layer 120 and the p-GaN layer 110 are sequentially stacked on the substrate 150 .

[0066] In some other embodiments, an AlGaN layer and / or an AlN layer is disposed between the insulating layer 120 and the p-GaN layer 110 .

[0067] A source 2, a drain 3, a first connecting wall 4, a second connecting wall 5, a dielectric layer 6 and a gate 7 are provided on the surface of the p-GaN layer 110 away from the insulating layer 120; the first connecting wall 4 and the second connecting wall 5 are electrically connected to the source 2 and the drain 3 respectively; the second connecting wall 5 forms a certain angle with the first connecting wall 4. The first connecting wall 4 and the second connecting wall 5 serve as a conductive channel. Specifically, the source 2 and the drain 3 are electrically connected along a first direction through the first connecting wall 4, and the source 2, the drain 3 and the first connecting wall 4 jointly define a groove, the groove extends along a second direction perpendicular to the first direction, and the first side wall of the groove is located between the source 2 and the groove, the second side wall of the groove is located between the drain 3 and the groove, the bottom wall of the groove is located at the first connecting wall 4, the second connecting wall 5 is located in the groove, and the second connecting wall 5 is electrically connected to the source 2 and the drain 3 respectively, the dielectric layer 6 covers the first connecting wall 4 and the second connecting wall 5, and the gate 7 is laid on the dielectric layer 6.

[0068] The thickness of the first connecting wall 4 along the third direction is 10nm-50nm, preferably 15nm-25nm. The third direction is a direction perpendicular to the plane where the first direction and the second direction are located. The material of the first connecting wall is the same as that of the p-GaN layer.

[0069] The number of the second connecting walls 5 is at least one. When the number of the second connecting walls 5 is at least two, the second connecting walls are arranged at intervals along the second direction.

[0070] In this embodiment, there are two second connecting walls 5, which are defined as a first dividing wall 510 and a second dividing wall 520. The first dividing wall 510 and the second dividing wall 520 have the same thickness, which is 10nm-3μm, preferably 150nm-2.5μm, and more preferably 1μm. The length of the groove along the first direction (gate length) is 10nm-100μm, further 10nm-60μm, preferably 2-50μm, and more preferably 10μm; the length of the groove along the second direction perpendicular to the first direction (gate width) is 10nm-120μm, preferably 20nm-110μm, and more preferably 20μm.

[0071] The first connecting wall 4 and the second connecting wall 5 are arranged at an angle, and the second connecting wall 5 is provided with a first dividing wall 510 and a second dividing wall 520. The first dividing wall 510 is provided with a first wall surface 511, a second wall surface 512, and a third wall surface 513. The second dividing wall 520 is provided with a first wall surface 521, a second wall surface 522, and a third wall surface 523. The first wall surface 511 of the first dividing wall 510 of the second connecting wall 5 is respectively connected with the second wall surface 512 and the third wall surface 513 along the second direction, the first wall surface 511 and the first connecting wall 4 are not in the same plane, the second wall surface 512 intersects with the plane where the bottom wall 430 of the groove is located, and the third wall surface 513 intersects with the plane where the bottom wall 430 of the groove is located. The first wall surface 521 of the second dividing wall 520 of the second connecting wall 5 is connected to the second wall surface 522 and the third wall surface 523 along the second direction respectively, the first wall surface 521 and the first connecting wall 4 are not in the same plane, the second wall surface 522 intersects with the plane where the bottom wall 430 of the groove is located, and the third wall surface 523 intersects with the plane where the bottom wall 430 of the groove is located. The gate 7 covers the first connecting wall 4, the first wall surface 511, the second wall surface 512 and the third wall surface 513 of the first dividing wall 510 of the second connecting wall 5, and the first wall surface 521, the second wall surface 522 and the third wall surface 523 of the second dividing wall 520 of the second connecting wall 5.

[0072] Device cross-section Figure 4 In the figure, the second wall surface 512 and the third wall surface 513 of the first partition wall 510 are both perpendicular to the first connecting wall 4; the second wall surface 522 and the third wall surface 523 of the second partition wall 520 are both perpendicular to the first connecting wall 4. The cross-sections of the first wall surface 511, the second wall surface 512 and the third wall surface 513 of the first partition wall 510 along the second direction perpendicular to the first direction are all rectangular; the cross-sections of the first wall surface 521, the second wall surface 522 and the third wall surface 523 of the second partition wall 520 along the second direction perpendicular to the first direction are all rectangular.

[0073] The second wall surface 512 of the first partition wall 510 is connected to the first connecting wall 4 ; the second wall surface 522 of the second partition wall 520 is connected to the first connecting wall 4 .

[0074] Further, the substrate 150 is a heterogeneous substrate or a homogeneous substrate; the material of the heterogeneous substrate is one of sapphire, silicon, silicon carbide, and gallium arsenide. The sapphire surface can be a c-plane, an r-plane, or an m-plane, and can also have a bias angle, such as c biased to m-plane 0-4 degrees, c biased to a-plane 0-4 degrees. The silicon carbide surface can be a C-plane or a Si-plane.

[0075] Optionally, the structure of the heterogeneous substrate can be a flat substrate or a patterned substrate. Optionally, the flat substrate can be a single-sided polished substrate or a double-sided polished substrate. The patterned substrate can be a micron-patterned substrate or a nano-patterned substrate. The pattern of the patterned substrate can be a protrusion or a pit. The pattern material of the patterned substrate can be the same as that of the substrate, or a layer of other dielectric layer, such as silicon dioxide, can be coated on the surface.

[0076] Optionally, the heterogeneous substrate is a substrate such as sapphire, silicon, silicon carbide, gallium arsenide, etc., on which a new material such as molybdenum disulfide, graphene, etc. is covered.

[0077] Optionally, the heterogeneous substrate is a sapphire, silicon, silicon carbide, gallium arsenide or other substrate covered with an aluminum nitride buffer layer by physical vapor deposition or the like, and the thickness of the aluminum nitride buffer layer is generally 20 nm.

[0078] In some embodiments, the substrate 150 is a homogeneous substrate, and the homogeneous substrate of the p-channel GaN field effect transistor is GaN.

[0079] In this embodiment, the substrate 150 is a silicon substrate with a diameter of 6 inches and a thickness of 1 mm, and a surface with a (111) crystal plane.

[0080] The source electrode 2 includes a first structure layer A and a second structure layer A which are sequentially stacked on the p-GaN layer 110; the drain electrode 3 includes a first structure layer B and a second structure layer B which are sequentially stacked on the p-GaN layer 110; wherein the first structure layer A includes a metal layer A, the metal layer A is composed of one or more of Ni, Pt, Pd, Mg, and Mo, and the second structure layer A is composed of Au; the first structure layer B includes a metal layer, the metal layer B is composed of one or more of Ni, Pt, Pd, Mg, and Mo, and the second structure layer B is composed of Au.

[0081] Further, the source electrode 2 includes a metal compound layer A; the drain electrode 3 includes a metal compound layer B. The metal compound layer A is composed of one or more of NiO and TiN; the metal compound layer B is composed of one or more of NiO and TiN.

[0082] Further, the source electrode 2 includes a nickel (Ni) layer and a gold (Au) layer sequentially stacked on the p-GaN layer 110; the drain electrode 3 includes a nickel (Ni) layer and a gold (Au) layer sequentially stacked on the p-GaN layer 110. It can also be Pt / Au, Pd / Au, Mg / Au, Mo / Au, Mg / Ni / Au, etc. It can also be a metal compound such as NiO, TiN, etc.

[0083] Furthermore, the source electrode 2 is a Ni (20 nm) / Au (40 nm) metal stack, the drain electrode 3 is a Ni (20 nm) / Au (40 nm) metal stack, and the gate electrode 4 is a Ti (20 nm) / Al (550 nm) / Ni (20 nm) / Au (20 nm) metal stack.

[0084] Further, the source 2 and the drain 3 are annealed at 400°C-850°C. The annealing atmosphere can be nitrogen, oxygen, and a mixture of nitrogen and oxygen in any proportion. The annealing pressure can be normal pressure or low pressure. The annealing time is generally 30s-40min. Optionally, the annealing temperature is 400°C-850°C, preferably 500°C-570°C.

[0085] Furthermore, a single device is etched to form a mesa, and the mesas of different devices are electrically insulated from each other.

[0086] Optionally, the mesa edges can be ion implanted.

[0087] Further, the shapes of the first connecting wall 4 and the second connecting wall 5 are determined by photolithography and then formed by etching. Etching can be performed by dry etching, such as inductively coupled plasma etching (ICP), reactive ion etching (RIE), atomic layer etching (ALE), etc., or wet etching. A combination of dry etching and wet etching can also be used. The ICP etching conditions include etching gases using Cl2 and BCl3, a tray temperature of -5-5°C, a pressure of 6-10mtorr, a Cl2 flow rate of 55-65sccm, a BCl3 flow rate of 12-17sccm, an upper electrode power of 190-210W, and a lower electrode power of 40-60W. Optionally, the etching depth is controlled to ensure that the thickness of the first connecting wall along the third direction is 10nm-50nm. The etching mask can be a photoresist or a deposited dielectric layer hard mask, such as SiO2, SiNx, etc.

[0088] In some embodiments, after etching is completed, an in-situ oxygen plasma micro-implantation treatment is performed on the first connecting wall 4 and the second connecting wall 5 .

[0089] Furthermore, after the first connecting wall 4 and the second connecting wall 5 are etched, the sidewall etching damage is removed by soaking in a specific solution. The solution may be potassium hydroxide (KOH), dilute hydrochloric acid (HCl), tetramethylammonium hydroxide (TMAH), etc. The soaking solution may be heated to 100° C., preferably 80° C.

[0090] Furthermore, the surfaces of the first connecting wall 4 and the second connecting wall 5 are covered with a dielectric layer 6, such as Al2O3, SiO2, SiNx, HfO2, ZrO2, etc. The thickness is 5nm-100nm, and the deposition method can be atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, metal organic chemical vapor deposition (MOCVD), etc.

[0091] Further, a structural layer or a metal compound layer is deposited on the dielectric layer 6 as a gate 7. Optionally, the type of the structural layer is not limited. Optionally, the structural layer includes a Ti layer, an Au layer, or a Ti layer, an Al layer, a Ni layer, an Au layer, or a Ni layer, an Au layer, or a Ti layer, an Al layer, or a Cr layer, a Ti layer, an Al layer, or a Cr layer, an Au layer, or a Ti layer, an Al layer, or a Ti layer, an Al layer, or a Mo layer, or a Ti layer, an Al layer, a Mo layer, an Au layer, or a Ti layer, an Al layer, a Ni layer, which are sequentially stacked and coated on the first connecting wall 4 and the second connecting wall 5. Optionally, the metal compound layer is a NiO layer and / or a TiN layer. Generally, whether the structural layer is annealed is not limited.

[0092] Preferably, the source electrode 2 , the drain electrode 3 and the gate electrode 7 are deposited on the epitaxial wafer 1 by electron beam evaporation, thermal evaporation or magnetron sputtering.

[0093] The method for preparing the GaN field effect transistor as described above comprises the following steps:

[0094] Providing an epitaxial wafer 1;

[0095] The epitaxial wafer 1 was ultrasonically cleaned in acetone, isopropanol, and deionized water for 5 minutes each, with an ultrasonic power of 300 W. After cleaning, it was blown dry with a nitrogen gun. It was soaked in a 6 mol / L potassium hydroxide (KOH) solution heated to 80°C for 1 minute. Then it was rinsed in deionized water and blown dry with a nitrogen gun.

[0096] Spin-coat the photoresist AZ5214 on the surface of epitaxial wafer 1 with a coating machine at a speed of 4000 rpm for 1 minute. After the coating is completed, bake it on a 110°C hot plate for 90 seconds. Use a photolithography machine to perform UV exposure on the source 2 and drain 3 areas with an exposure dose of 20mj. Bake the exposed epitaxial wafer 1 on a 120°C hot plate for 120 seconds, and then perform a 20-second flood exposure. Then develop it in MIF300 developer for 85 seconds, and blow it dry with a nitrogen gun after fixing. Then soak it in BOE solution for 3 minutes.

[0097] The sample after photolithography is placed in an electron beam evaporation device, and 20 nm nickel (Ni) and 40 nm gold (Au) are evaporated in sequence to construct the source 2 and the drain 3.

[0098] The sample with the electrode deposited was peeled off to ensure that the photoresist was completely removed. The residual photoresist was then further removed in an oxygen plasma stripper.

[0099] The prepared source electrode 2 and drain electrode 3 are annealed at 550° C. for 5 minutes in an oxygen atmosphere and normal pressure to form an ohmic contact.

[0100] Use acetone, isopropanol and deionized water to clean epitaxial wafer 1 according to the above steps. Spin-coat photoresist AZ6130 using the above parameters. After spin coating, bake it on a 110°C hot plate for 90 seconds. Perform UV exposure with a photolithography machine, with an exposure dose of 40mj. Develop the exposed epitaxial wafer 1 in MIF300 developer for 75 seconds, blow dry with a nitrogen gun after fixing, and prepare a table top pattern. Then further remove the residual glue in the pattern area in an oxygen plasma degumming machine.

[0101] The mesas of a single device are etched by inductively coupled plasma etching (ICP) equipment. The device mesas are electrically insulated. The etching gases are chlorine (Cl2) and boron trichloride (BCl3), the tray temperature is 0°C, and the pressure is 8mtorr. The Cl2 flow rate is 60sccm, and the BCl3 flow rate is 15sccm. The upper electrode power is 200W, and the lower electrode power is 50W. The mesa etching depth is 500nm.

[0102] The epitaxial wafer 1 was ultrasonically cleaned with acetone, isopropanol, and deionized water, and then dried with a nitrogen gun after removing the residual glue. The surface etching damage was removed by soaking in a 25% tetramethylammonium hydroxide (TMAH) solution heated to 85°C for 10 minutes. After that, it was cleaned in deionized water and dried with a nitrogen gun. Then, 450nm SiO2 was deposited at 350°C in a plasma enhanced chemical vapor deposition (PECVD) device. After the deposition, the epitaxial wafer 1 was ultrasonically cleaned with acetone, isopropanol, and deionized water, and dried with a nitrogen gun. Then, hexamethyldisilazane (HMDS) was applied in a sealed box at 120°C. Then, the photoresist AZ5214 was spin-coated, with the speed of the coating machine at 4000 rpm and the spin coating for 1 minute. After the spin coating, it was baked on a hot plate at 110°C for 90 seconds. The photolithography machine was used for alignment and UV exposure, and the exposure dose was 20mj. After exposure, the epitaxial wafer 1 was baked on a 120°C hot plate for 120 seconds, and then subjected to 20 seconds of flood exposure. After that, it was developed in MIF300 developer for 85 seconds, and after fixing, it was blown dry with a nitrogen gun. The residual glue was further removed by oxygen plasma. Then, the SiO2 on the device table was removed by ICP dry etching. The etching gas was carbon tetrafluoride (CF4) and argon (Ar), the tray temperature was 0°C, and the pressure was 8mtorr. The CF4 flow rate was 25sccm, and the Ar flow rate was 25sccm. The upper electrode power was 100W, and the lower electrode power was 30W. The thickness of the etched SiO2 was 450nm.

[0103] The epitaxial wafer 1 is ultrasonically cleaned with acetone, isopropanol, and deionized water to remove residual glue, and then blown dry with a nitrogen gun. Spin-coat photoresist AZ5214, the speed of the glue spreader is 4000 rpm, and the spin coating is 1 minute. After the spin coating is completed, it is baked on a 110°C hot plate for 90 seconds. Aligned by the photolithography machine, ultraviolet exposure is performed, and the exposure dose is 20mj. The exposed epitaxial wafer 1 is baked on a 120°C hot plate for 120 seconds, and then exposed for 20 seconds. After that, it is developed in MIF300 developer for 85 seconds, and after fixing, it is blown dry with a nitrogen gun to develop the gate groove pattern on the photoresist. The residual glue is further removed by oxygen plasma. Then, the first connecting wall 4 and the second connecting wall 5 are etched on the p-GaN110 by ICP to form a groove structure. The second connecting wall 5 includes two upper and lower partition walls, which are defined as the first partition wall 510 and the second partition wall 520 respectively. The etching gas used was Cl2 and BCl3, the tray temperature was 0°C, and the pressure was 8 mtorr. The Cl2 flow rate was 60 sccm, and the BCl3 flow rate was 15 sccm. The upper electrode power was 200 W, and the lower electrode power was 50 W. The etching depth was 280 nm. The thickness of the first dividing wall 510 and the second dividing wall 520 of the second connecting wall 5 obtained by etching was 1 μm, and the length of the groove along the first direction was 10 μm, and the length along the second direction was 20 μm.

[0104] The epitaxial wafer 1 is cleaned with acetone, isopropanol and deionized water to remove the residual glue, and then blown dry with a nitrogen gun. The residual glue is further removed in an oxygen plasma degumming machine. The etching damage is removed by soaking in a 25% TMAH solution heated to 85°C for 10 minutes. After being cleaned with deionized water, it is placed in an atomic layer deposition (ALD) device and a 20nm aluminum oxide (Al2O3) is grown at 300°C by thermal oxidation as a dielectric layer 6.

[0105] The epitaxial wafer 1 was cleaned with acetone, isopropanol and deionized water, and dried with a nitrogen gun. Spin-coat the photoresist AZ5214, with the speed of the coating machine at 4000 rpm, and the coating was performed for 1 minute. After the coating was completed, it was baked on a 110°C hot plate for 90 seconds. The photolithography machine was aligned and UV exposure was performed, and the exposure dose was 20mj. The exposed epitaxial wafer 1 was baked on a 120°C hot plate for 120 seconds, and then a 20-second flood exposure was performed. After that, it was developed in MIF300 developer for 85 seconds, and after fixing, it was dried with a nitrogen gun to develop the gate 7 pattern. The residual glue in the pattern area was further removed by oxygen plasma. 20nm titanium (Ti), 550nm aluminum (Al), 20nm nickel (Ni), and 20nm gold (Au) were sequentially evaporated as gate 7 by electron beam evaporation equipment. After that, the residual photoresist was removed by stripping. The residual glue was further removed in an oxygen plasma stripper. A 3D / 2D composite structure p-channel GaN field effect transistor was prepared.

[0106] The performance of the prepared p-channel GaN field effect transistor was analyzed using a semiconductor parameter analyzer Keysight 4155C.

[0107] The transfer characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Figure 5 As shown, the drain 3 voltage is maintained at -1V. It can be seen that the GaN field effect transistor of this embodiment is an enhanced p-channel GaN field effect transistor, which has good gate control capability, a high switching ratio and a low subthreshold swing. Its threshold voltage is -1.1V.

[0108] The output characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Figure 6 As shown in FIG. 1 , it can be seen that the p-channel GaN field effect transistor of this embodiment has a saturated drain 3 current that increases as the gate 7 voltage decreases, and a GS = 10 at 0V -7 Leakage current of mA / mm.

[0109] In some other embodiments, the second wall surface 512 of the first partition wall 510 of the second connecting wall 5 is not connected to the first connecting wall 4 , and the second wall surface 522 of the second partition wall 520 of the second connecting wall 5 is not connected to the first connecting wall 4 . Figure 7 It is a cross-sectional view of one embodiment along a second direction perpendicular to the first direction, and a gap 8 is left between the second wall surface and the first connecting wall.

[0110] Example 2

[0111] Repeat Example 1, the main difference is that the second connecting wall 5 only has the first dividing wall 510, the thickness of the first dividing wall 510 of the second connecting wall 5 is 1 μm, and the position is Figure 8 upper side.

[0112] The transfer characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig. 9 As shown, the drain 3 voltage is maintained at -10V. It can be seen that the GaN field effect transistor of this embodiment is an enhanced p-channel GaN field effect transistor, which has good gate control capability, high switching ratio, low subthreshold swing and low voltage as low as 10 -10 The off-state leakage current is mA / mm. The threshold voltage is 0V.

[0113] The output characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.10 As shown, it can be seen that the saturated drain current of this embodiment also increases significantly as the gate voltage decreases, indicating that it has good gate control capability. Since there is only one second dividing wall 510 as a conductive channel, the p-channel GaN field effect transistor of this embodiment has a lower saturated drain current than that of embodiment 1.

[0114] Example 3

[0115] Repeat Example 1, the main difference is that the second connecting wall 5 only has a second dividing wall 520, the thickness of the second dividing wall 520 of the second connecting wall 5 is 1 μm, and the position is Fig.11 The lower side.

[0116] The transfer characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.12 As shown, the drain 3 voltage is maintained at -10V. It can be seen that the GaN field effect transistor of this embodiment is an enhanced p-channel GaN field effect transistor, which has good gate control capability, high switching ratio, low subthreshold swing and low voltage as low as 10 -10 The off-state leakage current is mA / mm and the threshold voltage is -2.5V.

[0117] The output characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.13 As shown, it can be seen that the p-channel GaN field effect transistor of this embodiment has a saturated drain current that increases as the gate voltage decreases. Since there is only one conductive channel of the second dividing wall 520, the saturated drain current is reduced.

[0118] Example 4

[0119] Repeat Example 1, the main difference is that the second connecting wall 5 includes a first partition wall 510 and a second partition wall 520, and the thickness of the first partition wall 510 is greater than the thickness of the second partition wall 520. Fig.14 In the embodiment, the thickness of the first partition wall 510 (upper side) is 3 μm, and the thickness of the second partition wall 520 (lower side) is 1 μm.

[0120] The transfer characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.15 As shown, the drain 3 voltage is kept at -1V. It can be seen that the GaN field effect transistor of this embodiment is an enhanced p-channel GaN field effect transistor, which has good gate control capability, high switching ratio, low subthreshold swing and low voltage as low as 10 -10 mA / mm off-state leakage current. The on / off ratio is 1.4×10 6 , the threshold voltage is -3.9V.

[0121] The output characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.16 As shown, it can be seen that the p-channel GaN field effect transistor of this embodiment has a saturated drain current that increases as the gate voltage decreases. The two asymmetric partition walls of the second connecting wall 5 further increase the conductivity, so that the saturated drain current of this embodiment exceeds the level of embodiment 1 at a gate voltage of -7V.

[0122] Example 5

[0123] Repeat Example 1, the main difference is that the second connecting wall 5 includes a first partition wall 510 and a second partition wall 520, and the thickness of the second partition wall 520 is greater than the thickness of the first partition wall 510. Fig.17 In the embodiment, the thickness of the first partition wall 510 (upper side) is 1 μm, and the thickness of the second partition wall 520 (lower side) is 3 μm.

[0124] The transfer characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.18 As shown, the drain 3 voltage is kept at -1V. It can be seen that the GaN field effect transistor of this embodiment is an enhanced p-channel GaN field effect transistor, which has good gate control capability, high switching ratio, low subthreshold swing and low voltage as low as 10 -10 mA / mm off-state leakage current. On / off ratio is 2.0×10 6 , the threshold voltage is -3.4V.

[0125] The output characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.19 As shown, it can be seen that the p-channel GaN field effect transistor of this embodiment has a saturated drain current that increases as the gate voltage decreases and a good gate control capability. The two asymmetric partition walls of the second connecting wall 5 further increase the conductivity, so that the saturated drain current of this embodiment exceeds the level of embodiment 1 at a gate voltage of -7V.

[0126] Example 6

[0127] Example 1 is repeated, with the main difference being that the second wall surface 512 and the third wall surface 513 of the first dividing wall 510 of the second connecting wall 5 are not perpendicular to the first connecting wall 4; the second wall surface 522 and the third wall surface 523 of the second dividing wall 520 of the second connecting wall 5 are not perpendicular to the first connecting wall 4. Fig. 20 In the figure, the second wall surface 512 and the third wall surface 513 of the first partition wall 510 of the second connecting wall 5 are trapezoidal in cross-sectional view along the second direction perpendicular to the first direction; the second wall surface 522 and the third wall surface 523 of the second partition wall 520 of the second connecting wall 5 are trapezoidal in cross-sectional view along the second direction perpendicular to the first direction.

[0128] The transfer characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig. 22 As shown, the drain 3 voltage is kept at -1V. It can be seen that the GaN field effect transistor of this embodiment is an enhanced p-channel GaN field effect transistor, which has good gate control capability, high switching ratio, low subthreshold swing and low voltage as low as 10 -8 The off-state leakage current is mA / mm and the threshold voltage is -1.2V.

[0129] The output characteristic curve of the p-channel GaN field effect transistor of this embodiment is as follows: Fig.23 As shown, it can be seen that the p-channel GaN field effect transistor of this embodiment has a saturated drain current that increases as the gate voltage decreases and good gate control capability. Due to the two second connecting walls 5 (the first dividing wall 510 and the second dividing wall 520), the saturated drain current of this embodiment is relatively high.

[0130] In some other embodiments, the second wall surface 512 of the first partition wall 510 of the second connecting wall 5 is not connected to the first connecting wall 4 , and the second wall surface 522 of the second partition wall 520 of the second connecting wall 5 is not connected to the first connecting wall 4 . Fig.21 It is a cross-sectional view of one embodiment along a second direction perpendicular to the first direction, and a gap 8 is left between the second wall surface and the first connecting wall.

[0131] In some other embodiments, the second wall surface 512 of the first dividing wall 510 of the second connecting wall 5 is not perpendicular to the first connecting wall 4, and the third wall surface 513 is perpendicular to the first connecting wall 4; the second wall surface 522 of the second dividing wall 520 of the second connecting wall 5 is not perpendicular to the first connecting wall 4, and the third wall surface 523 is perpendicular to the first connecting wall 4. Fig.24 In the figure, the second wall surface 512 and the third wall surface 513 of the first partition wall 510 of the second connecting wall 5 are in a cross-sectional view along the second direction perpendicular to the first direction and are a right-angled trapezoid; the second wall surface 522 and the third wall surface 523 of the second partition wall 520 of the second connecting wall 5 are in a cross-sectional view along the second direction perpendicular to the first direction and are a right-angled trapezoid.

[0132] In some other embodiments, the second wall surface 512 of the first partition wall 510 of the second connecting wall 5 is not connected to the first connecting wall 4 , and the second wall surface 522 of the second partition wall 520 of the second connecting wall 5 is not connected to the first connecting wall 4 . Fig.25 It is a cross-sectional view of one embodiment along a second direction perpendicular to the first direction, and a gap 8 is left between the second wall surface and the first connecting wall.

[0133] In some other embodiments, the second wall surface 512 of the first dividing wall 510 of the second connecting wall 5 is perpendicular to the first connecting wall 4, and the third wall surface 513 is not perpendicular to the first connecting wall 4; the second wall surface 522 of the second dividing wall 520 of the second connecting wall 5 is perpendicular to the first connecting wall 4, and the third wall surface 523 is not perpendicular to the first connecting wall 4. Fig.26 In the figure, the second wall surface 512 and the third wall surface 513 of the first partition wall 510 of the second connecting wall 5 are in a cross-sectional view along the second direction perpendicular to the first direction and are a right-angled trapezoid; the second wall surface 522 and the third wall surface 523 of the second partition wall 520 of the second connecting wall 5 are in a cross-sectional view along the second direction perpendicular to the first direction and are a right-angled trapezoid.

[0134] In some other embodiments, the second wall surface 512 of the first partition wall 510 of the second connecting wall 5 is not connected to the first connecting wall 4 , and the second wall surface 522 of the second partition wall 520 of the second connecting wall 5 is not connected to the first connecting wall 4 . Fig. 27 It is a cross-sectional view of one embodiment along a second direction perpendicular to the first direction, and a gap 8 is left between the second wall surface and the first connecting wall.

[0135] In some other embodiments, the second wall surface 512 of the first dividing wall 510 of the second connecting wall 5 is not perpendicular to the first connecting wall 4, and the third wall surface 513 is not perpendicular to the first connecting wall 4; the second wall surface 522 of the second dividing wall 520 of the second connecting wall 5 is not perpendicular to the first connecting wall 4, and the third wall surface 523 is not perpendicular to the first connecting wall 4. Fig.28 In the figure, the second wall surface 512 and the third wall surface 513 of the first partition wall 510 of the second connecting wall 5 are quadrilateral in cross-sectional view along the second direction perpendicular to the first direction; the second wall surface 522 and the third wall surface 523 of the second partition wall 520 of the second connecting wall 5 are quadrilateral in cross-sectional view along the second direction perpendicular to the first direction.

[0136] In some other embodiments, the second wall surface 512 of the first partition wall 510 of the second connecting wall 5 is not connected to the first connecting wall 4 , and the second wall surface 522 of the second partition wall 520 of the second connecting wall 5 is not connected to the first connecting wall 4 . Fig.29 It is a cross-sectional view of one embodiment along a second direction perpendicular to the first direction, and a gap 8 is left between the second wall surface and the first connecting wall.

[0137] In some other embodiments, the second wall surface 512 of the first dividing wall 510 of the second connecting wall 5 is not perpendicular to the first connecting wall 4, and the third wall surface 513 is perpendicular to the first connecting wall 4; the second wall surface 522 of the second dividing wall 520 of the second connecting wall 5 is not perpendicular to the first connecting wall 4, and the third wall surface 523 is perpendicular to the first connecting wall 4. Fig.30 In the figure, the second wall surface 512 and the third wall surface 513 of the first dividing wall 510 of the second connecting wall 5 are, in a cross-sectional view along the second direction perpendicular to the first direction, a right-angled trapezoid whose upper base is longer than the lower base; the second wall surface 522 and the third wall surface 523 of the second dividing wall 520 of the second connecting wall 5 are, in a cross-sectional view along the second direction perpendicular to the first direction, a right-angled trapezoid whose upper base is longer than the lower base.

[0138] In some other embodiments, the second wall surface 512 of the first partition wall 510 of the second connecting wall 5 is not connected to the first connecting wall 4 , and the second wall surface 522 of the second partition wall 520 of the second connecting wall 5 is not connected to the first connecting wall 4 . Fig.31It is a cross-sectional view of one embodiment along a second direction perpendicular to the first direction, and a gap 8 is left between the second wall surface and the first connecting wall.

[0139] In some other embodiments, the second connecting wall 5 has only one first partition wall 510 , and the second wall surface 512 and the third wall surface 513 of the first partition wall 510 are both connected to the first connecting wall 4 . Fig.32 It is a cross-sectional view of one embodiment along a second direction perpendicular to the first direction, and the cross-sectional view of the second connecting wall and the first connecting wall along the second direction perpendicular to the first direction is an inverted T shape.

[0140] Comparative Example 1

[0141] Comparative Example 1: A top view of a p-channel GaN field effect transistor device constructed using a conventional groove gate is shown in FIG. Fig.33 The device only has the first connecting wall 4, and the constructed field effect tube only has a conductive channel at the bottom. The device manufacturing process is the same as that of embodiment 1, except that the groove gate does not have the second connecting wall 5.

[0142] The transfer characteristic curve of the p-channel GaN field effect transistor of comparative example 1 is as follows: Fig.34 As shown, the drain 3 voltage is maintained at -10V. It can be seen that the GaN field effect transistor of this embodiment is an enhanced p-channel GaN field effect transistor with good gate control capability and low voltage of 10 -10 The off-state leakage current is 2.5 mA / mm. The threshold voltage is -3.5 V, but the output current is relatively low, and the on / off ratio is only 3.0×10 5 .

[0143] The output characteristic curve of the p-channel GaN field effect transistor of comparative example 1 is as follows: Fig.35 As shown, it can be seen that the p-channel GaN field effect transistor of this embodiment has a saturated drain current that increases as the gate voltage decreases and a good gate control capability. Since there is only one conductive channel at the bottom (the first connecting wall 4), the saturated output current of the comparative example 1 is significantly lower than the saturated output current of other embodiments using a 3D / 2D composite conductive channel (both the first connecting wall 4 and the second connecting wall 5).

[0144] Comparative Example 2

[0145] Example 1 is repeated, with the main difference being that the thickness of the two partition walls of the second connecting wall 5 is both 3.5 μm.

[0146] The transfer characteristic curve of the p-channel GaN field effect transistor of comparative example 2 is as follows: Fig.36 As shown, the voltage of the drain 3 is maintained at -0.2 V. Since the thickness of the second connecting wall 5 is too thick, the gate control capability of the comparative example 2 is weakened, the off-state current is significantly increased, and the switching ratio is reduced.

[0147] The output characteristic curve of the p-channel GaN field effect transistor of comparative example 2 is as follows: Fig.37 As shown in the figure, the drain 3 current changes with the gate voltage regulation, but does not reach saturation. At the same time, the drain 3 current under the gate voltage of 0V is still very large, the device leakage current is very large, and it is impossible to achieve complete shutdown.

[0148] The contents explained in the above embodiments should be understood as these embodiments are only used to more clearly illustrate the present invention, and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

Claims

1. A p-channel GaN field effect transistor, characterized in that: The invention comprises an epitaxial wafer, wherein the epitaxial wafer comprises a p-GaN layer, a source electrode, a drain electrode, a first connecting wall, a second connecting wall, a dielectric layer and a gate electrode are arranged on the p-GaN layer, the source electrode and the drain electrode are electrically connected along a first direction through the first connecting wall, and the source electrode, the drain electrode and the first connecting wall jointly define a groove, the groove extends along a second direction perpendicular to the first direction, and the first side wall of the groove is located between the source electrode and the groove, the second side wall of the groove is located between the drain electrode and the groove, the bottom wall of the groove is located at the first connecting wall, the first connecting wall and the second connecting wall are arranged at an angle, the second connecting wall is located in the groove, and the second connecting wall is electrically connected to the source electrode and the drain electrode respectively, the dielectric layer covers the first connecting wall and the second connecting wall, and the gate electrode is laid on the dielectric layer.

2. The epitaxial wafer according to claim 1, characterized in that: The second connecting wall is provided with a first wall surface, a second wall surface, and a third wall surface. The first wall surface is respectively connected to the second wall surface and the third wall surface along the second direction. The first wall surface and the bottom wall of the groove are not in the same plane. The second wall surface intersects with the plane where the bottom wall of the groove is located. The third wall surface intersects with the plane where the bottom wall of the groove is located. The gate covers the first connecting wall, the first wall surface, the second wall surface, and the third wall surface.

3. The p-channel GaN field effect transistor according to claim 2, characterized in that: The second wall surface is perpendicular to the first connecting wall.

4. The p-channel GaN field effect transistor according to claim 2, characterized in that: The third wall surface is perpendicular to the first connecting wall.

5. The p-channel GaN field effect transistor according to claim 2, characterized in that: The second wall surface is connected to the first connecting wall, or a gap is left between the second wall surface and the first connecting wall.

6. The p-channel GaN field effect transistor according to claim 2, characterized in that: The number of the second connecting walls is at least one; when the number of the second connecting walls is at least two, the second connecting walls are spaced apart along the second direction.

7. The p-channel GaN field effect transistor according to claim 6, characterized in that: The thicknesses of the second connecting walls are equal.

8. The p-channel GaN field effect transistor according to any one of claims 1 to 7, characterized in that: The epitaxial wafer also includes a substrate, a nucleation layer, a buffer layer, and an insulating layer. The nucleation layer, the buffer layer, the insulating layer, and the p-GaN layer are sequentially stacked on the substrate, and the first connecting wall and the second connecting wall are located on the surface of the p-GaN layer away from the insulating layer.

9. The p-channel GaN field effect transistor according to claim 8, characterized in that: An AlGaN layer and / or an AlN layer is further disposed between the insulating layer and the p-GaN layer.

10. The method for preparing a p-channel GaN field effect transistor according to any one of claims 1 to 9, characterized in that: The steps include: Providing epitaxial wafers; Depositing a source electrode and a drain electrode on the epitaxial wafer and performing annealing in an oxygen atmosphere; forming a first connecting wall and a second connecting wall on the epitaxial wafer by photolithography and etching; growing a dielectric layer on the surfaces of the first connecting wall and the second connecting wall; A gate is evaporated on the dielectric layer.

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