Super junction trench gate MOSFET structure and forming method thereof

Abstract

The invention relates to a super-junction trench gate MOSFET structure and a forming method thereof, the super-junction trench gate MOSFET structure comprises a substrate, the surface of the substrate is provided with a first drift region, the surface of the first drift region is provided with a second drift region, the surface of the second drift region is provided with a body region, the first drift region and the second drift region are internally provided with first doped ions, and the body region is provided with second doped ions; the concentration of first doped ions in the first drift region is greater than that of first doped ions in the second drift region, second doped ions are arranged in the body region, and the type of the second doped ions is opposite to that of the first doped ions; the groove penetrates through the body region and the second drift region, and the bottom of the groove exposes the first drift region; the doped column is located in the first drift region at the bottom of the groove, and second doped ions are arranged in the doped column; the dielectric layer is located in part of the groove, the top surface of the dielectric layer is lower than the bottom surface of the body region, and the bottom surface of the dielectric layer is in contact with the top surface of the doped column; the trench gate is positioned in the residual trench and is positioned above the dielectric layer; the performance of the finally formed super-junction trench gate MOSFET structure can be effectively improved, so that the formed super-junction trench gate MOSFET structure has a wider application range.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a super junction trench gate MOSFET structure and a forming method thereof. Background Art

[0002] Trench gate MOSFET device is a common MOFET device variant, which includes a gate, source and drain. The flow of current is controlled by adjusting the gate voltage. The core principle is to use the gate electric field to control the electrons in the channel. When there is a positive voltage between the gate and the source, an electron gas is formed in the channel, allowing current to pass. When the gate voltage is zero or negative, the channel becomes an insulator and the current stops.

[0003] Trench gate MOSFET devices are widely used in power conversion circuits and are often used in power switching devices. In order to improve the on-resistance of medium and high voltage (50V~200V) trench gates, the concept of super junction-trench gate has been proposed. The on-resistance Rsp and breakdown voltage BV of trench gates are one of its important parameter indicators. Obtaining higher breakdown voltage and lower on-resistance can improve the competitiveness of products.

[0004] However, the performance of existing superjunction trench gate MOSFET devices is poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a super junction trench gate MOSFET structure and a method for forming the same, which can effectively improve the performance of the ultimately formed super junction trench gate MOSFET structure, so that the formed super junction trench gate MOSFET structure has a wider range of applications.

[0006] To solve the above problems, the present invention provides a super junction trench gate MOSFET structure, comprising: a substrate, a first drift region on the surface of the substrate, a second drift region on the surface of the first drift region, a body region on the surface of the second drift region, first doping ions in the first drift region and the second drift region, the concentration of the first doping ions in the first drift region is greater than the concentration of the first doping ions in the second drift region, the body region has second doping ions, and the type of the second doping ions is opposite to the type of the first doping ions; a trench running through the body region and the second drift region, the bottom of the trench exposing the first drift region; a doping column in the first drift region at the bottom of the trench, the doping column having second doping ions; a dielectric layer in a portion of the trench, the top surface of the dielectric layer being lower than the bottom surface of the body region, the bottom surface of the dielectric layer being in contact with the top surface of the doping column; and a trench gate in the remaining trench and above the dielectric layer.

[0007] Optionally, the concentration range of the second doping ion in the doping column is 1e12 cm -2 to 1e13cm-2 , the implantation energy range is 50Kev to 4000Kev.

[0008] Optionally, the trench gate includes a gate dielectric layer located on the top surface of the dielectric layer; and a gate polysilicon layer located on the gate dielectric layer, wherein the gate polysilicon layer fully fills the trench.

[0009] Optionally, it also includes: a source end heavily doped region in the body region on both sides of the trench gate, the source end heavily doped region has third doping ions, and the type of the third doping ions is the same as the type of the first doping ions.

[0010] Optionally, it also includes: an interlayer dielectric layer located on the surface of the body region, a plug located in the interlayer dielectric layer, the bottom of the plug extends into the body region, and the plug penetrates the heavily doped source region on both sides of the trench gate.

[0011] Optionally, it also includes: a heavily doped region located at the bottom of the plug, the heavily doped region is located in the body region, and has fourth doping ions in the heavily doped region, and the type of the fourth doping ions is opposite to the type of the third doping ions.

[0012] Optionally, it further includes a source metal layer located on the top surface of the interlayer dielectric layer, and the source metal layer is also located on the top surface of the plug.

[0013] Optionally, it also includes: a drain metal layer located on the surface of the substrate, and the drain metal layer and the drift region are respectively located on two sides of the substrate.

[0014] Optionally, the bottom of the trench exposes the top surface of the first drift region or the bottom of the trench extends into the first drift region.

[0015] Correspondingly, the present invention also provides a method for forming a super junction trench gate MOSFET structure, comprising the steps of: providing a substrate, forming a first drift region on the surface of the substrate, forming a second drift region on the surface of the first drift region, forming a body region on the surface of the second drift region, having first doping ions in the first drift region and the second drift region, the concentration of the first doping ions in the first drift region is greater than the concentration of the first doping ions in the second drift region, having second doping ions in the body region, and the type of the second doping ions is opposite to the type of the first doping ions; etching the body region and part of the drift region to form a groove running through the body region and the second drift region, wherein the bottom of the groove exposes the first drift region; forming a doping column in the first drift region at the bottom of the groove, wherein the doping column has second doping ions; forming a dielectric layer in part of the groove, wherein the top surface of the dielectric layer is lower than the bottom surface of the body region, and the bottom surface of the dielectric layer is in contact with the top surface of the doping column; forming a trench gate in the remaining trench, wherein the trench gate is located above the dielectric layer.

[0016] Optionally, the method for forming the trench includes: forming an etch stop layer on the surface of the body region;

[0017] A hard mask layer is formed on the surface of the etch stop layer; a photoresist layer is formed on the surface of the hard mask layer, wherein the photoresist layer has an opening exposing a portion of the surface of the hard mask layer; the hard mask layer is etched using the photoresist layer as a mask to form a hard mask opening exposing a portion of the etch stop layer in the hard mask layer; the photoresist layer is removed; and the etch stop layer, the body region, and the second drift region are etched using the hard mask layer as a mask to form a groove, wherein the bottom of the groove exposes the first drift region.

[0018] Optionally, the bottom of the trench exposes the top surface of the first drift region or the bottom of the trench extends into the first drift region.

[0019] Optionally, the method for forming the doped column and the dielectric layer includes: forming a sacrificial oxide layer on the sidewall of the trench; using the hard mask layer as a mask, ion implanting the first drift region at the bottom of the trench to form a doped column, wherein the doped column has second doped ions, and the concentration range of the second doped ions in the doped column is 1e12cm -2 to 1e13cm -2 , the injection energy range is 50Kev to 4000Kev; the hard mask layer, the sacrificial oxide layer and the etch stop layer are removed; an initial dielectric layer is formed in the groove, and the initial dielectric layer fills the groove; the initial dielectric layer is etched back to a surface lower than the bottom surface of the body region, and a dielectric layer is formed in part of the groove.

[0020] Optionally, the method for forming a trench gate includes: after forming a dielectric layer, forming a gate dielectric layer on the sidewalls of the remaining trench and the surface of the dielectric layer; forming a gate polysilicon layer on the gate dielectric layer, and the gate polysilicon layer fully fills the trench.

[0021] Optionally, after forming the trench gate, the method further includes: performing ion implantation on the body region on both sides of the trench gate to form a source end heavily doped region, wherein the source end heavily doped region has a third doping ion, and the type of the third doping ion is the same as the type of the first doping ion; forming an interlayer dielectric layer on the surface of the body region; forming a plug in the interlayer dielectric layer, wherein the bottom of the plug extends into the body region, and the plug penetrates the source end heavily doped region on both sides of the trench gate; forming a heavily doped region in the body region at the bottom of the plug, wherein the heavily doped region has a fourth doping ion, and the type of the fourth doping ion is opposite to the type of the third doping ion; forming a source end metal layer on the top surface of the interlayer dielectric layer, wherein the source end metal layer is formed on the top surface of the plug; forming a drain end metal layer on the surface of the substrate, wherein the drain end metal layer and the drift region are respectively located on both sides of the substrate.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the technical solution of the super junction trench gate MOSFET structure of the present invention, the surface of the substrate has a first drift region, the surface of the first drift region has a second drift region, the surface of the second drift region has a body region, the first drift region and the second drift region both have first doping ions, wherein the concentration of the first doping ions in the first drift region is greater than the concentration of the first doping ions in the second drift region, the body region has second doping ions, and the type of the first doping ions is opposite to the type of the second doping ions; a groove runs through the body region and the second drift region, the bottom of the groove exposes the first drift region, the doping column is located at the bottom of the groove, and the first drift region is exposed. The doped column also has second doped ions in the region, a dielectric layer is located in part of the trench, the top surface of the dielectric layer is lower than the bottom surface of the body region, the bottom surface of the dielectric layer is in contact with the top surface of the doped column, and the trench gate is located in the remaining trench; the doped column is used to assist the depletion of the first drift region, and the body region assists the depletion of the second drift region, thereby increasing the length of the entire (first drift region and second drift region), which helps to improve the breakdown voltage. At the same time, the body region assists in depleting the second drift region, increases the doping concentration of the second drift region, and reduces the on-resistance of the super junction trench gate MOSFET, which has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a superjunction trench gate MOSFET structure in one embodiment;

[0025] Figures 2 to 10 It is a structural schematic diagram of a formation process of a super junction trench gate MOSFET structure according to an embodiment of the present invention;

[0026] Fig.11 Schematic diagram of the id-vd relationship curve of the super junction trench gate MOSFET in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] The electrical performance of the super junction trench gate MOSFET structure in the prior art still needs to be improved.

[0028] Figure 1 It is a schematic structural diagram of a super junction trench gate MOSFET structure in one embodiment.

[0029] Please refer to Figure 1The super junction trench gate MOSFET includes: a substrate 1, an epitaxial layer 2, a doped column 3, a gate dielectric layer 4, a trench gate 5, a body region 6, a first heavily doped region 8, an interlayer insulating dielectric layer 10, a second heavily doped region 7, a conductive plug 9, a source metal layer 11 and a drain metal layer 12, wherein the epitaxial layer 2 covers the front surface of the substrate 1; the doped column 3 is located in the epitaxial layer 2; an array of trenches is formed in the epitaxial layer 2 between the doped columns 3, the gate dielectric layer 4 covers the bottom wall and side wall of the trench, and the trench gate 5 covers the gate The dielectric layer 4 and the remaining space filling the trench; the body region 6 is located in the epitaxial layer 2 between the trench gates 5; the first heavily doped region 8 is located in the body region 6; the interlayer insulating dielectric layer 10 covers the first heavily doped region 8 and the trench gate 5; the conductive plug 9 is located in the interlayer insulating dielectric layer 10, the first heavily doped region 8 and a partial thickness of the body region 6; the second heavily doped region 7 is located at the bottom of the conductive plug 9; the source metal layer 11 covers the interlayer insulating dielectric layer 10 and the conductive plug 9; the drain metal layer 12 covers the back side of the substrate 1.

[0030] The inventors found that in the above embodiment, the doped column 3 is formed by ion implantation. Since the ion implantation energy is limited, the process is restricted when the ion implantation energy is greater than 3500Kev, especially for the requirement of BV>80V (the thickness of the epitaxial layer 2 is greater than 5um). The ion implantation energy is greater than 2500Kev, which makes the bottom of the doped column 3 as close to the highly doped substrate 1 as possible. However, the high-energy ion implantation brings great difficulties to the process integration.

[0031] The inventor has found through research that the surface of the substrate has a first drift region, the surface of the first drift region has a second drift region, the surface of the second drift region has a body region, the first drift region and the second drift region both have first doping ions, wherein the concentration of the first doping ions in the first drift region is greater than the concentration of the first doping ions in the second drift region, the body region has second doping ions, and the type of the first doping ions is opposite to the type of the second doping ions; a groove runs through the body region and the second drift region, the bottom of the groove exposes the first drift region, the doping column is located in the first drift region at the bottom of the groove, and the same doping ions in the doping column The method comprises a dielectric layer having second doping ions and located in a part of the trench, wherein the top surface of the dielectric layer is lower than the bottom surface of the body region, the bottom surface of the dielectric layer contacts the top surface of the doped column, and the trench gate is located in the remaining trench; the doped column is used to assist the depletion of the first drift region, and the body region assists the depletion of the second drift region, thereby increasing the length of the entire (first drift region and second drift region), which helps to improve the breakdown voltage; at the same time, the body region assists the depletion of the second drift region, which can increase the doping concentration of the second drift region and reduce the on-resistance of the super junction trench gate MOSFET, and has a wider range of applications.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] First, please refer to Figure 2 A substrate 101 is provided, a first drift region 102 - 1 is formed on a surface of the substrate 101 , a second drift region 102 - 2 is formed on a surface of the first drift region 102 - 1 , and a body region 106 is formed on a surface of the second drift region 102 - 2 .

[0034] In this embodiment, the first drift region 102-1 and the second drift region 102-2 have first doping ions, the concentration of the first doping ions in the first drift region 102-1 is greater than the concentration of the first doping ions in the second drift region 102-2, and the body region 106 has second doping ions, and the type of the second doping ions is opposite to the type of the first doping ions.

[0035] In this embodiment, taking an N-type channel SJ-TGMOSFET as an example, the substrate 101 is a highly doped N-type substrate 101 .

[0036] It should be noted that all subsequent doping ion types are described using an N-type channel as an example; if the channel type changes, all doping ion types will be changed accordingly according to actual application needs.

[0037] In some embodiments, the substrate 101 may also be a highly doped P-type substrate 101 .

[0038] In this embodiment, the material of the substrate 101 is silicon.

[0039] In some embodiments, the material of the substrate 101 may also be other semiconductor materials such as silicon germanium.

[0040] In this embodiment, epitaxial growth is performed on the substrate 101 to form an epitaxial layer, and the epitaxial layer is in-situ doped to form a drift region, wherein the drift region includes a first drift region 102-1 located on the surface of the substrate 101 and a second drift region 102-2 located on the surface of the first drift region 102-1. The first drift region 102-1 and the second drift region 102-2 both have first doping ions, the first doping ions are N-type, and the concentration of the first doping ions in the first drift region 102-1 is between 5e15 cm -2 -1e17cm -2 The concentration of the first doping ion in the second drift region 102-2 is between 1e15 cm -2 -1e16cm -2 .

[0041] In other embodiments, the type of the first doping ion is P-type, and the type of the second doping ion is N-type.

[0042] In this embodiment, the depth d1 of the first drift region 102-1 ranges from 2.0 μm to 5.0 μm, the depth d2 of the second drift region 102-2 ranges from 3.0 μm to 7.0 μm, and the ratio of the depth d1 of the first drift region 102-1 to the depth d2 of the second drift region 102-2 ranges from 0.3 to 3.0.

[0043] In this embodiment, second doping ions are implanted into the surface of the second drift region 102 - 2 to form a body region 106 .

[0044] In this embodiment, the type of the second doping ions is opposite to the type of the first doping ions, and specifically the second doping ion type is P type.

[0045] In this embodiment, the process parameters of epitaxial growth include the gases used, including hydrogen, HCl gas, SiH2Cl2, PH3 and CH3SiH3 gas, the flow rate of hydrogen is 2000sccm~20000sccm, the flow rate of HCl gas is 30sccm~150sccm, the flow rate of SiH2Cl2 is 50sccm~1000sccm, the flow rate of PH3 is 10sccm~2000sccm, the flow rate of CH3SiH3 is 50sccm~5000sccm, the chamber pressure is 10torr~600torr, and the temperature is 650 degrees Celsius~850 degrees Celsius.

[0046] The body region 106 and part of the drift region are etched to form a trench penetrating the body region 106 and the second drift region 102-2. The bottom of the trench exposes the first drift region 102-1. Figure 3 to Figure 4 .

[0047] Please refer to Figure 3 , an etch stop layer 201 is formed on the surface of the body region 106; a hard mask layer 502 is formed on the surface of the etch stop layer 201; a photoresist layer 501 is formed on the surface of the hard mask layer 502, and the photoresist layer 501 has an opening that exposes a portion of the surface of the hard mask layer 502; using the photoresist layer 501 as a mask, the hard mask layer 502 is etched to form a hard mask opening that exposes a portion of the etch stop layer 201 in the hard mask layer 502.

[0048] In this embodiment, the material of the etch stop layer 201 is a silicon nitride layer.

[0049] In some embodiments, the material of the etch stop layer 201 may also be silicon carbonitride, silicon carbide, etc.

[0050] In this embodiment, the material of the hard mask layer 502 is silicon oxide.

[0051] In some embodiments, the material of the hard mask layer 502 may also be silicon oxynitride, silicon oxycarbide, etc.

[0052] Please refer to Figure 4 , remove the photoresist layer 501, and use the hard mask layer 502 as a mask to etch the etch stop layer 201, the body region 106, and the second drift region 102-2 to form a trench 203, and the bottom of the trench 203 exposes the first drift region 102-1.

[0053] In this embodiment, the bottom of the trench 203 extends into the first drift region 102 - 1 .

[0054] In some embodiments, the bottom of the trench 203 only exposes the top surface of the first drift region 102 - 1 .

[0055] In this embodiment, the method for forming the groove 203 is a dry etching process, and the specific parameters include: the gases used include CF4 and CH3F, the flow rate of CF4 is 20sccm~200sccm, the flow rate of CH3F is 20sccm~50sccm, the source RF power is 200W~500W, and the chamber pressure is 1torr~10torr.

[0056] A doped column is formed in the first drift region 102-1 at the bottom of the trench 203, and a dielectric layer is formed in part of the trench 203. The top surface of the dielectric layer is lower than the bottom surface of the body region 106, and the bottom surface of the dielectric layer contacts the top surface of the doped column. The process of having the second doping ion in the doped column can be referred to Figures 5 to 7 .

[0057] Please refer to Figure 5 , a sacrificial oxide layer 202 is formed on the sidewall of the trench 203 .

[0058] In this embodiment, the substrate 101 with the hard mask layer 502 is placed in a furnace tube to grow a sacrificial oxide layer 202, and defects formed by etching the trench 203 are repaired by a thermal oxidation process, which helps to improve the quality of subsequently formed devices.

[0059] Please refer to Figure 6 , using the hard mask layer 502 as a mask, ion implantation is performed into the first drift region 102-1 at the bottom of the trench 203 to form a doped column 103, wherein the doped column 103 has second doped ions, and the concentration range of the second doped ions in the doped column 103 is 1e12cm -2 to 1e13cm -2 , the implantation energy range is 50Kev to 4000Kev.

[0060] In this embodiment, the sacrificial oxide layer 202 is used as an implantation liner layer, and implantation is performed using the hard mask layer 502 as a mask to form the doped pillars 103 .

[0061] In this embodiment, the doping column 103 is located in the first drift region 102-1 directly below the bottom of the trench 203. The injection energy of the doping column 103 is 50Kev to 4000Kev, and the injection angle is greater than or equal to 0° and less than 7°. The doping column 103 has a second doping ion, and the second doping ion is P-type and opposite to the first doping ion type, such as B, with a concentration of 1e12-1e13cm -2 .

[0062] In this embodiment, the angle range of the ion implantation is greater than or equal to 0° and less than 7°.

[0063] Please refer to Figure 7 , remove the hard mask layer 502 , the sacrificial oxide layer 202 and the etch stop layer 201 ; form an initial dielectric layer (not shown in the figure) in the groove 203 , and the initial dielectric layer fills the groove 203 ; etch back the initial dielectric layer until the surface is lower than the bottom surface of the body region 106 , and form a dielectric layer 204 in part of the groove 203 .

[0064] In this embodiment, the material of the dielectric layer 204 is silicon oxide.

[0065] In this embodiment, the hard mask layer 502 and the sacrificial oxide layer 202 share the same wet etching removal process, which can further save manufacturing costs.

[0066] A trench gate is formed in the remaining trench 203, and the trench gate is located above the dielectric layer 204. Please refer to Figure 8 .

[0067] Please refer to Figure 8 After forming the dielectric layer 204, a gate dielectric layer 104 is formed on the sidewalls of the remaining trench 203 and the surface of the dielectric layer 204; a gate polysilicon layer 105 is formed on the gate dielectric layer 104, and the gate polysilicon layer 105 fills the trench 203. The gate dielectric layer 104 and the gate polysilicon layer 105 constitute a trench gate.

[0068] In this embodiment, a first gate silicon oxide layer (not shown in the figure) of 100 to 400 angstroms is grown by a low-temperature thermal oxidation growth process, the oxidation temperature is 800 to 930°C, and the time is less than 30 minutes; then a TEOS silicon oxide layer is deposited as a second gate oxide layer and rapid annealing is performed to densify the TEOS, a gate polysilicon layer 105 is deposited, and chemical mechanical polishing is performed to form a gate structure.

[0069] In this embodiment, the gate dielectric layer 104 is grown in a low-temperature oxidation and deposition manner, which reduces the heat process introduced by thermal growth and allows the doped pillars 103 to diffuse laterally.

[0070] Please refer to Fig. 9 After forming the trench gate, the method further includes: performing ion implantation on the body region 106 on both sides of the trench gate to form a source end heavily doped region 108, wherein the source end heavily doped region 108 has a third doping ion, and the type of the third doping ion is the same as the type of the first doping ion; forming an interlayer dielectric layer 110 on the surface of the body region 106; forming a plug 109 in the interlayer dielectric layer 110, wherein the bottom of the plug 109 extends into the body region 106, and the plug 109 penetrates the source end heavily doped region 108 on both sides of the trench gate; forming a heavily doped region 107 in the body region 106 at the bottom of the plug 109, wherein the heavily doped region 107 has a fourth doping ion, and the type of the fourth doping ion is opposite to the type of the third doping ion.

[0071] In this embodiment, the third doping ion is N-type, and the fourth doping ion is P-type.

[0072] Please refer to Fig.10 A source metal layer 111 is formed on the top surface of the interlayer dielectric layer 110 , and the source metal layer 111 is formed on the top surface of the plug 109 ; a drain metal layer 112 is formed on the surface of the substrate 101 , and the drain metal layer 112 and the drift region are respectively located on both sides of the substrate 101 .

[0073] Accordingly, please refer to Fig.10 The present invention also provides a super junction trench gate MOSFET structure, including a substrate 101, a first drift region 102-1 is provided on the surface of the substrate 101, a second drift region 102-2 is provided on the surface of the first drift region 102-1, a body region 106 is provided on the surface of the second drift region 102-2, first doping ions are provided in the first drift region 102-1 and the second drift region 102-2, the concentration of the first doping ions in the first drift region 102-1 is greater than the concentration of the first doping ions in the second drift region 102-2, the body region 106 has second doping ions, and the type of the second doping ions is The type of the doping ions is opposite to that of the first doping ion; a trench 203 that runs through the body region 106 and the second drift region 102-2, the bottom of the trench 203 exposing the first drift region 102-1; a doping column 103 located in the first drift region 102-1 at the bottom of the trench 203, the doping column 103 having the second doping ions; a dielectric layer 204 located in a portion of the trench 203, the top surface of the dielectric layer 204 being lower than the bottom surface of the body region 106, the bottom surface of the dielectric layer 204 being in contact with the top surface of the doping column 103; a trench gate located in the remaining trench 203 and above the dielectric layer 204.

[0074] In this embodiment, the doping column 103 is used to assist the depletion of the first drift region 102-1, and the body region 106 assists the depletion of the second drift region 102-2, thereby increasing the length of the entire drift region (the first drift region 102-1 and the second drift region 102-2), which helps to improve the breakdown voltage. At the same time, the body region 106 assists in depleting the second drift region 102-2, increases the doping concentration of the second drift region 102-2, and reduces the on-resistance of the super junction trench gate MOSFET, which has a wider range of applications.

[0075] In this embodiment, from the simulation point of view ( Fig.11 ), the super junction trench gate MOSFET structure can withstand voltage over 170V, Rsp is 85mOhm*mm 2 .

[0076] In this embodiment, the concentration range of the second doping ion in the doping column 103 is 1e12 cm -2 to 1e13cm -2 , the implantation energy range is 50Kev to 4000Kev.

[0077] In this embodiment, the trench gate includes a gate dielectric layer 104 located on the top surface of the dielectric layer 204 ; a gate polysilicon layer 105 located on the gate dielectric layer 104 , and the gate polysilicon layer 105 fully fills the trench 203 .

[0078] In this embodiment, it also includes: a source end heavily doped region 108 located in the body region 106 on both sides of the trench gate, wherein the source end heavily doped region 108 has a third doping ion, and the type of the third doping ion is the same as the type of the first doping ion.

[0079] In this embodiment, it also includes: an interlayer dielectric layer 110 located on the surface of the body region 106, a plug 109 located in the interlayer dielectric layer 110, the bottom of the plug 109 extends into the body region 106, and the plug 109 penetrates the source end heavily doped region 108 on both sides of the trench gate.

[0080] In this embodiment, it also includes: a heavily doped region 107 located at the bottom of the plug 109, the heavily doped region 107 is located in the body region 106, and the heavily doped region 107 has fourth doping ions, and the type of the fourth doping ions is opposite to the type of the third doping ions.

[0081] In this embodiment, a source metal layer 111 is further included and is located on the top surface of the interlayer dielectric layer 110 . The source metal layer 111 is also located on the top surface of the plug 109 .

[0082] In this embodiment, it further includes: a drain metal layer 112 located on the surface of the substrate 101 , and the drain metal layer 112 and the drift region are located on two sides of the substrate 101 respectively.

[0083] In the present embodiment, the bottom of the trench 203 exposes the top surface of the first drift region 102 - 1 or the bottom of the trench 203 extends into the first drift region 102 - 1 .

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A super junction trench gate MOSFET structure, characterized in that: include: A substrate, wherein a first drift region is provided on a surface of the substrate, a second drift region is provided on a surface of the first drift region, a body region is provided on a surface of the second drift region, first doping ions are provided in the first drift region and the second drift region, a concentration of the first doping ions in the first drift region is greater than a concentration of the first doping ions in the second drift region, and second doping ions are provided in the body region, and a type of the second doping ions is opposite to a type of the first doping ions; a trench penetrating the body region and the second drift region, wherein the bottom of the trench exposes the first drift region; a doped column located in the first drift region at the bottom of the trench, wherein the doped column has the second doping ions; A dielectric layer located in a portion of the trench, wherein a top surface of the dielectric layer is lower than a bottom surface of the body region, and the bottom surface of the dielectric layer contacts a top surface of the doped column; A trench gate is located in the remaining trench and above the dielectric layer.

2. The super junction trench gate MOSFET structure according to claim 1, characterized in that: The concentration range of the second doping ion in the doping column is 1e12cm -2 to 1e13cm -2 , the implantation energy range is 50Kev to 4000Kev.

3. The super junction trench gate MOSFET structure according to claim 1, characterized in that: The trench gate comprises a gate dielectric layer located on the top surface of the dielectric layer; and a gate polysilicon layer located on the gate dielectric layer, wherein the gate polysilicon layer fully fills the trench.

4. The super junction trench gate MOSFET structure according to claim 1, characterized in that: Also includes: The source end heavily doped region in the body region at both sides of the trench gate has third doping ions in the source end heavily doped region, and the type of the third doping ions is the same as the type of the first doping ions.

5. The super junction trench gate MOSFET structure according to claim 4, characterized in that: Also includes: An interlayer dielectric layer is located on the surface of the body region, and a plug is located in the interlayer dielectric layer. The bottom of the plug extends into the body region, and the plug penetrates the heavily doped source region on both sides of the trench gate.

6. The super junction trench gate MOSFET structure according to claim 5, characterized in that: Also includes: A heavily doped region is located at the bottom of the plug, the heavily doped region is located in the body region, and has fourth doping ions in the heavily doped region, and the type of the fourth doping ions is opposite to the type of the third doping ions.

7. The super junction trench gate MOSFET structure according to claim 6, characterized in that: It also includes a source metal layer located on the top surface of the interlayer dielectric layer, and the source metal layer is also located on the top surface of the plug.

8. The super junction trench gate MOSFET structure according to claim 1, characterized in that: Also includes: A drain metal layer is located on the surface of the substrate, and the drain metal layer and the drift region are respectively located on two sides of the substrate.

9. The super junction trench gate MOSFET structure according to claim 1, characterized in that: The bottom of the trench exposes the top surface of the first drift region or the bottom of the trench extends into the first drift region.

10. A method for forming a super junction trench gate MOSFET structure, characterized in that: Includes steps: Providing a substrate, forming a first drift region on a surface of the substrate, forming a second drift region on a surface of the first drift region, forming a body region on a surface of the second drift region, wherein first doping ions are present in the first drift region and the second drift region, the concentration of the first doping ions in the first drift region is greater than the concentration of the first doping ions in the second drift region, and the body region is provided with second doping ions, the type of the second doping ions being opposite to the type of the first doping ions; Etching the body region and a portion of the drift region to form a trench penetrating the body region and the second drift region, wherein the bottom of the trench exposes the first drift region; forming a doped column in the first drift region at the bottom of the trench, wherein the doped column has the second doping ions; forming a dielectric layer in a portion of the trench, wherein a top surface of the dielectric layer is lower than a bottom surface of the body region, and the bottom surface of the dielectric layer contacts a top surface of the doped column; A trench gate is formed in the remaining trench, and the trench gate is located above the dielectric layer.

11. The method for forming a super junction trench gate MOSFET structure according to claim 10, wherein: The method for forming the groove comprises: forming an etch stop layer on a surface of the body region; forming a hard mask layer on a surface of the etch stop layer; forming a photoresist layer on the surface of the hard mask layer, wherein the photoresist layer has an opening exposing a portion of the surface of the hard mask layer; Using the photoresist layer as a mask, etching the hard mask layer to form a hard mask opening in the hard mask layer that exposes a portion of the etch stop layer; removing the photoresist layer; The etch stop layer, the body region, and the second drift region are etched using the hard mask layer as a mask to form the trench, and the bottom of the trench exposes the first drift region.

12. The method for forming a super junction trench gate MOSFET structure according to claim 10 or 11, characterized in that: The bottom of the trench exposes the top surface of the first drift region or the bottom of the trench extends into the first drift region.

13. The method for forming a super junction trench gate MOSFET structure according to claim 11, characterized in that: The method for forming the doped column and the dielectric layer comprises: forming a sacrificial oxide layer on the sidewalls of the trench; Using the hard mask layer as a mask, ion implantation is performed into the first drift region at the bottom of the trench to form the doped column, wherein the doped column contains second doped ions, and the concentration range of the second doped ions in the doped column is 1e12 cm -2 to 1e13cm -2 , the implantation energy range is 50Kev to 4000Kev; removing the hard mask layer, the sacrificial oxide layer and the etch stop layer; forming an initial dielectric layer in the groove, wherein the initial dielectric layer completely fills the groove; The initial dielectric layer is etched back until the surface is lower than the bottom surface of the body region, so as to form the dielectric layer in a portion of the trench.

14. The method for forming a super junction trench gate MOSFET structure according to claim 13, wherein: The method for forming the trench gate includes: After forming the dielectric layer, forming a gate dielectric layer on the remaining sidewalls of the trench and the surface of the dielectric layer; A gate polysilicon layer is formed on the gate dielectric layer, and the gate polysilicon layer fully fills the trench.

15. The method for forming a super junction trench gate MOSFET structure according to claim 14, wherein: After forming the trench gate, the method further includes: Performing ion implantation on the body region at both sides of the trench gate to form a source end heavily doped region, wherein the source end heavily doped region has a third doping ion, and the type of the third doping ion is the same as the type of the first doping ion; forming an interlayer dielectric layer on the surface of the body region; forming a plug in the interlayer dielectric layer, wherein the bottom of the plug extends into the body region, and the plug penetrates the heavily doped source regions on both sides of the trench gate; forming a heavily doped region in the body region at the bottom of the plug, wherein the heavily doped region has fourth doping ions, and the type of the fourth doping ions is opposite to the type of the third doping ions; forming a source metal layer on the top surface of the interlayer dielectric layer, wherein the source metal layer is formed on the top surface of the plug; A drain metal layer is formed on the surface of the substrate, and the drain metal layer and the drift region are respectively located on two sides of the substrate.

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