Contour of gate structure in semiconductor device

Abstract

The invention relates to a profile of a gate structure in a semiconductor device. The invention discloses a semiconductor device and a method of manufacturing the same. A semiconductor device includes a substrate, a semiconductor layer disposed on the substrate, a source / drain region disposed adjacent to the semiconductor layer, a gate structure disposed on the semiconductor layer, an interface spacer layer having a triangular cross-sectional profile disposed along sidewalls of the gate structure, and a gate spacer. The gate spacer includes a first spacer portion including a first bottom surface having a substantially linear profile disposed on the semiconductor layer and a second spacer portion including a second bottom surface having an inclined profile disposed on the interface spacer layer.

Description

Technical Field

[0001] The present disclosure relates to profiling of gate structures in semiconductor devices. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs has increased. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and gate-all-around field effect transistors (GAA FETs). This shrinking increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a semiconductor layer disposed on the substrate; a source / drain region disposed adjacent to the semiconductor layer; a gate structure disposed on the semiconductor layer; an interface spacer layer disposed along a sidewall of the gate structure and comprising a triangular cross-sectional profile; and a gate spacer comprising: a first spacer portion comprising a first bottom surface having a substantially linear profile disposed on the semiconductor layer; and a second spacer portion comprising a second bottom surface having an inclined profile disposed on the interface spacer layer.

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; a gate spacer disposed along a side wall of the gate structure; and an interface spacer layer, comprising: a first side wall having an inclined profile facing the gate spacer; a second side wall facing the side wall of the gate structure; and a bottom surface facing the top surface of the fin structure.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming an oxide layer on a semiconductor layer; forming a polysilicon structure on the oxide layer; forming a gate spacer on the oxide layer and the polysilicon structure; forming a gate opening by removing the polysilicon structure; forming an interface spacer layer between a bottom surface of the gate spacer and a top surface of the semiconductor layer; and forming a gate structure in the gate opening and in contact with the interface spacer layer and the gate spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1AAn isometric view of a semiconductor device in accordance with some embodiments is shown.

[0008] Figure 1B-Figure 1E and Figure 2 Different cross-sectional views of a semiconductor device having an interface spacer layer in accordance with some embodiments are shown.

[0009] Figure 3 is a flow chart of a method of fabricating a semiconductor device having an interface spacer layer according to some embodiments.

[0010] Figure 4-Figure 20 Cross-sectional views of a semiconductor device having an interface spacer layer at different stages of its fabrication process are shown in accordance with some embodiments.

[0011] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the process of forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature refers to forming the first feature in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] It should be noted that the phrases "one embodiment", "embodiment", "example embodiment", "exemplary", etc. mentioned in the specification indicate that the described embodiment may include a particular feature, structure or characteristic, but not every embodiment necessarily includes the particular feature, structure or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in conjunction with one embodiment, it is within the knowledge of those skilled in the art to combine such feature, structure or characteristic with other embodiments, whether or not explicitly described.

[0015] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, and thus the phraseology or terminology of this specification should be interpreted by persons skilled in the relevant art(s) based on the teachings herein.

[0016] In some embodiments, the terms "about" and "substantially" may mean that the value of a given amount varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20%). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0017] The GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. The double patterning process or the multi-patterning process can combine a photolithography process and a self-aligned process, allowing the manufacture of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate using a photolithography process and patterned. A spacer is formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0018] The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. The double patterning process or the multi-patterning process may combine a photolithography process and a self-alignment process, allowing for the manufacture of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure.

[0019] The present disclosure provides an example structure and method for improving the bottom angle profile of the gate structure in the FET to prevent the current leakage between the gate structure and the source / drain (S / D) region in the FET. In some embodiments, the FET may have a nanostructure channel region disposed on a substrate, a gate structure disposed around the nanostructure channel region, an S / D region disposed adjacent to the nanostructure channel region, and an external gate spacer disposed along the sidewall of the gate structure to electrically isolate the gate structure from the adjacent source / drain region. In some embodiments, there may be an interface gap between the external gate spacer and the topmost nanostructure channel region. These interface gaps can be filled with an interface spacer layer having an insulating material. The interface spacer layer can prevent the bottom angle portion of the gate structure from being formed in the interface gap during the formation of the gate structure. Preventing the bottom angle portion of the gate structure from extending below the external gate spacer can increase the spacing between the gate structure and the adjacent S / D region, prevent the current leakage between the gate structure and the adjacent S / D region or minimize the probability of current leakage, and improve device performance. Therefore, by using an interface spacer layer, the bottom angle profile of the gate structure can be controlled. According to the sidewall profile of the interface spacer layer, the gate structure may have a U-shaped cross-sectional profile with a bottom corner having a right-angle corner profile, a beveled corner profile, or a rounded corner profile.

[0020] Figure 1A An isometric view of a semiconductor device 100 is shown, which may represent a GAA FET 100 , in accordance with some embodiments. Figure 1B The GAA FET 100 is shown along the Figure 1A The cross-sectional view of line AA, Figure 1A Additional structures are not shown for simplicity. Figure 1C-1E FIG. 1 shows an exemplary embodiment of the present invention. Figure 1B Different enlarged cross-sectional views of the region 101, Figure 1B Additional details are not shown for the sake of brevity. Figure 1A-1E Discussions of elements with the same annotation apply to each other.

[0021] refer to Figure 1A-1EIn some embodiments, the GAA FET 100 may include: (i) a substrate 102, (ii) a shallow trench isolation (STI) region 104 disposed on the substrate 102, (iii) a fin-shaped base structure 106 (also referred to as a "sheet base 106" or a "fin base 106") disposed on the substrate 102, (iv) a nanostructure channel region 108 disposed on the base structure 106, (v) an S / D region 110 disposed adjacent to the nanostructure channel region 108, (vi) a gate structure 112 surrounding the nanostructure channel region 108, (vii) an external gate spacer 114, (viii) an interface spacer layer 116, (ix) an internal gate spacer 118, (x) an etch stop layer (ESL) 120 disposed directly on the S / D region 110, (xi) an interlayer dielectric (ILD) layer 122 disposed directly on the ESL 120, and (xii) a contact structure 124 disposed on the S / D region 110.

[0022] In some embodiments, the substrate 102 may be a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 102 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, the STI region 104 may include an insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeO2). x ). In some embodiments, base structure 106 may include a material similar to substrate 102. Base structure 106 may have an elongated side extending along the X-axis.

[0023] In some embodiments, the nanostructure channel region 108 may be in the form of a nanosheet, nanowire, nanorod, nanotube, or other suitable nanostructure shape. As used herein, the term "nanostructure" defines a structure, layer, and / or region as having a horizontal dimension (such as along the X-axis and / or Y-axis) and / or a vertical dimension (such as along the Z-axis) less than about 100 nm, for example, about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. The nanostructure channel region 108 may include a semiconductor material similar to or different from the substrate 102. In some embodiments, the nanostructure channel region 108 may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium strontium boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. In some embodiments, the thickness of each nanostructure channel region 108 along the Z-axis may be about 3 nm to about 15 nm. Although two nanostructure channel regions 108 are shown below the gate structure 112, the GAA FET 100 may have any number of nanostructure channel regions 108. Although rectangular cross-sections of the nanostructure channel regions 108 are shown, the nanostructure channel regions 108 may have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal).

[0024] In some embodiments, the S / D region 110 may include an epitaxially grown semiconductor material such as Si and an n-type dopant, for example, phosphorus and other suitable n-type dopants for n-type GAA FETs 100. The S / D region 110 may include an epitaxially grown semiconductor material such as Si and SiGe and a p-type dopant, for example, boron and other suitable p-type dopants for p-type GAA FETs 100. Each S / D region 110 may be referred to individually or collectively as a source or a drain, depending on the context.

[0025] In some embodiments, each gate structure 112 may have an outer gate portion 113A and an inner gate portion 113B. In some embodiments, the outer gate portion 113A may be disposed on and in physical contact with the topmost nanostructure channel region 108. In some embodiments, the inner gate portion 113B may be disposed between adjacent nanostructure channel regions 108 and between adjacent inner gate spacers 118.

[0026] Each gate structure may be a multi-layer structure and may include: (i) an interface oxide (IL) layer 112A, (ii) a high-K (HK) gate dielectric layer 112B, (iii) a conductive layer 112C, and (iv) a gate cap layer 112D. In some embodiments, the IL layer 112A may be disposed directly on the topmost nanostructure channel region 108. In some embodiments, the IL layer 112A may include SiO2, SiGeO x or germanium oxide (GeO x ), and has a thickness H1 of about 0.5 nm to about 1 nm. In some embodiments, the HK gate dielectric layer 112B may be directly disposed on the IL layer 112A and may include a high-K dielectric material, for example, hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, a sidewall of the HK gate dielectric layer 112B may contact a sidewall of the external gate spacer 114.

[0027] In some embodiments, the conductive layer 112C may be disposed on the HK gate dielectric layer 112B and may be a multilayer structure. For simplicity, the different layers of the conductive layer 112C are not shown. In some embodiments, the conductive layer 112C may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 112B and a gate metal filling layer disposed on the WFM layer. In some embodiments, the WFM layer may include a Ti-based or Ta-based nitride or metal that is substantially free of Al (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu) alloy. In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal fill layer may include a suitable conductive material, for example, tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys and combinations thereof.

[0028] In some embodiments, the gate cap layer 112D may be disposed directly on the HK gate dielectric layer 112B and the conductive layer 112C. The gate cap layer 112D may protect the underlying layers from structural and / or compositional degradation during subsequent processing of the GAA FET 100. In some embodiments, the gate cap layer 112D may include a nitride material, such as SiN, and may have a thickness of about 5 nm to about 10 nm to adequately protect the underlying layers.

[0029] The external gate spacers 114 can electrically isolate the external gate portion 113A from the adjacent S / D regions 110 and the adjacent contact structures 124. In some embodiments, each external gate spacer 114 can include a horizontal spacer portion 114h and an inclined spacer portion 114s. The horizontal spacer portion 114h can have a bottom surface 114hb having a substantially linear profile and in direct contact with the top surface of the topmost nanostructure channel region 108. The inclined spacer portion 114s can have a bottom surface 114sb having an inclined profile and in direct contact with the interface spacer layer 116. The interface between the inclined spacer portion 114s and the interface spacer layer 116 can have an inclined profile. In some embodiments, the external gate spacer 114 can include an undoped dielectric layer, for example, an undoped SiO2 layer, an undoped SiN layer, an undoped SiON layer, an undoped SiOC layer, an undoped SiCN layer, an undoped SiOCN layer, and any other suitable undoped dielectric layer.

[0030] In some embodiments, each interface spacer layer 116 may include a dielectric material, such as SiO2, SiN, SiON, SiCN, and SiOCN. In some embodiments, each interface spacer layer 116 may include an oxide layer (e.g., SiO2) of a semiconductor element (e.g., Si) in the outer gate spacer 114 and / or the nanostructure channel region 108. The interface spacer layer 116 may be disposed between the inclined spacer portion 114s and the topmost nanostructure channel region 108. This arrangement of the interface spacer layer 116 fills the interface gap 1316 ( Figure 1A-1E Not shown, Fig.13), as explained in detail below. Therefore, during the formation of the gate structure 112, the bottom corner region 112cr of the external gate portion 113A can be prevented from extending into the interface gap 1316 and prevented from being formed under the external gate spacer 114. Preventing the external gate portion 113A from extending under the external gate spacer 114 can increase the spacing between the external gate portion 113A and the adjacent S / D region 110, prevent current leakage between the external gate portion 113A and the adjacent S / D region 110 or minimize the probability of current leakage, and improve device performance. Therefore, by using the interface spacer layer 116, the bottom angle profile of the external gate portion 113A can be controlled. According to the sidewall profile of the interface spacer layer 116, the external gate portion 113A can have a U-shaped cross-sectional profile with a different bottom angle profile, as described below with reference to Figure 1C , Figure 1D and Figure 1E described.

[0031] refer to Figure 1C In some embodiments, each interface spacer layer 116 on either side of the external gate portion 113A may have: (i) a triangular cross-sectional profile, (ii) a substantially vertical sidewall 116s1 facing and in contact with the external gate portion 113A, whose height H2 is about 2 nm to about 5 nm, (iii) the sidewall 116s1 is substantially aligned with the sidewall 114sw of the external gate spacer 114, (iv) an inclined sidewall facing and in contact with the external gate spacer 114, (v) a substantially right-angled corner (e.g., about 85 degrees to about 90 degrees) between the sidewall 116s1 and the bottom surface of the interface spacer layer 116, and (vi) an acute-angled corner (e.g., about 35 degrees to about 75 degrees) between the inclined sidewall and the bottom surface of the interface spacer layer 116.

[0032] In some embodiments, due to Figure 1C In the embodiment of the present invention, with respect to the structural profile of the interface spacer layer 116 on either side of the external gate portion 113A, (i) the external gate portion 113A can be formed with a U-shaped cross-sectional profile, (ii) the bottom corner region 112cr can be formed with a substantially right-angled corner profile (e.g., about 90 degrees to about 95 degrees), (iii) the sidewall 112s of the external gate portion 113A can form angles A and B of about 90 degrees to about 95 degrees with the bottom surface 112b of the external gate portion 113A, (iv) the sidewall of the IL layer 112A can form an angle of about 90 degrees to about 95 degrees with the bottom surface of the IL layer 112A, (v) the sidewall of the HK gate dielectric layer 112B can form an angle of about 90 degrees to about 95 degrees with the bottom surface of the HK gate dielectric layer 112B, and (vi) the sidewall of the conductive layer 112C can form an angle of about 90 degrees to about 95 degrees with the bottom surface of the conductive layer 112C.

[0033] In some embodiments, the ratio between dimensions H1 and H2 may be about 0.1 to about 0.5. In some embodiments, the interface between the interface spacer layer 116 and the IL layer 112A and the interface between the interface spacer layer 116 and the HK gate dielectric layer 112B may have a linear profile. Figure 1C The structural profile and dimensions of the interface spacer layer 116 and the external gate portion 113A in the embodiment can prevent or minimize the probability of current leakage between the external gate portion 113A and the adjacent S / D region 110, thereby improving device performance.

[0034] In some embodiments, the interface spacer layer 116 may have a Figure 1D The structural outline shown is not Figure 1C The structural outline is shown. Figure 1D In some embodiments, each of the interface spacer layers 116 on either side of the external gate portion 113A may have: (i) a triangular cross-sectional profile, (ii) a first inclined sidewall 116s2 facing and contacting the external gate portion 113A, (iii) a second inclined sidewall facing and contacting the external gate spacer 114, and (iv) an acute corner (e.g., about 45 degrees to about 85 degrees) between the sidewall 116s2 and the bottom surface of the interface spacer layer 116. In some embodiments, due to Figure 1D In the structure profile of the interface spacer layer 116 on either side of the external gate portion 113A, (i) the external gate portion 113A can be formed with a U-shaped cross-sectional profile, (ii) the bottom corner region 112cr can be formed with a beveled corner profile, (iii) the sidewall of the IL layer 112A can be formed with an inclined profile, (iv) the bottom corner of the HK gate dielectric layer 112B can be formed with a beveled corner profile, and (v) the bottom corner of the conductive layer 112C can be formed with a beveled corner profile. In some embodiments, the interface between the interface spacer layer 116 and the IL layer 112A and the interface between the interface spacer layer 116 and the HK gate dielectric layer 112B can have an inclined profile. The above-discussed Figure 1D The structural profile and dimensions of the interface spacer layer 116 and the external gate portion 113A in the embodiment can prevent or minimize the probability of current leakage between the external gate portion 113A and the adjacent S / D region 110, thereby improving device performance.

[0035] In some embodiments, the interface spacer layer 116 may have a Figure 1E The structural outline shown is not Figure 1C or Figure 1D The structural outline is shown. Figure 1EIn some embodiments, each of the interface spacer layers 116 on either side of the external gate portion 113A may have: (i) a triangular cross-sectional profile, (ii) a curved sidewall 116s3 facing and contacting the external gate portion 113A, (iii) an inclined sidewall facing and contacting the external gate spacer 114, and (iv) an acute corner (e.g., about 35 degrees to about 75 degrees) between the inclined sidewall and the bottom surface of the interface spacer layer 116. In some embodiments, due to Figure 1E In the structure profile of the interface spacer layer 116 on either side of the external gate portion 113A, (i) the external gate portion 113A can be formed with a U-shaped cross-sectional profile, (ii) the bottom corner region 112cr can be formed with a rounded corner profile, (iii) the sidewall of the IL layer 112A can be formed with a curved profile, (iv) the bottom corner of the HK gate dielectric layer 112B can be formed with a rounded corner profile, and (v) the bottom corner of the conductive layer 112C can be formed with a rounded corner profile. In some embodiments, the interface between the interface spacer layer 116 and the IL layer 112A and the interface between the interface spacer layer 116 and the HK gate dielectric layer 112B can have a curved profile. The above-discussed Figure 1E The structural profile and dimensions of the interface spacer layer 116 and the external gate portion 113A in the embodiment can prevent or minimize the probability of current leakage between the external gate portion 113A and the adjacent S / D region 110, thereby improving device performance.

[0036] refer to Figure 1A and Figure 1B , the internal gate spacers 118 can electrically isolate the internal gate portion 113B from the adjacent S / D region 110. In some embodiments, each internal gate spacer 118 can have a height of about 3 nm to about 20 nm and a thickness of about 1 nm to about 10 nm. Within these ranges of height and thickness, the internal gate spacers 118 can sufficiently electrically isolate the internal gate portion 113B from the adjacent S / D region 110 without affecting device size and manufacturing cost.

[0037] In some embodiments, the ESL 120 may be disposed directly on the S / D region 110. In some embodiments, the ESL 120 may have a dielectric constant of about 4 to about 7, and may include dielectric materials such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, SiN, and zinc oxide (ZnO). In some embodiments, the ILD layer 122 may be disposed directly on the ESL 120. In some embodiments, the ILD layer 122 may include insulating materials such as SiO2, SiN, SiON, SiCN, and SiOCN.

[0038] In some embodiments, each contact structure 124 may include (i) a silicide layer 124A, and (ii) a contact plug 124B disposed on the silicide layer 124A. In some embodiments, the silicide layer 124A in the n-type GAA FET 100 may include titanium silicide (Ti x Si y ), Tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr x Si y ), Hafnium Silicide (Hf x Si y ), Scandium Silicate (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium Silicide (Er x Si y ), Ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), Thorium Silicide (Th x Si y ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the silicide layer 124A in the p-type GAA FET 100 may include nickel silicide (Ni x Si y ), cobalt silicide (Cox Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), iridium silicide (Ir x Si y ), Os x Si y ), other suitable metal silicide materials, or combinations thereof. In some embodiments, the contact plug 124B may include a conductive material, for example, Co, W, Ru, Al, Mo, Ir, Ni, osmium (Os), rhodium (Rh), other suitable conductive materials, and combinations thereof.

[0039] In some embodiments, the semiconductor device 100 may represent a FinFET 100 rather than a GAA FET 100 and may have a cross Figure 1A Line AA Figure 2 Unless otherwise mentioned, Figure 1A-1E and Figure 2 Discussions of elements with the same annotation apply to each other. Unless otherwise noted, references to Figure 1B-Figure 1E The discussion of the external gate portion 113A of the GAA FET 100 applies to Figure 2 The gate structure 112 of the FinFET 100 in FIG. Figure 2 Unlike the GAA FET 100, the FinFET 100 may have: (i) a fin structure 106, replacing the nanostructure channel region 108 and the base structure 106, (ii) a gate structure 112 directly disposed on the fin structure 106, (iii) a fin region of the fin structure 106, located below the gate structure 112 and adjacent to the S / D region 110 as the channel region, (iv) a horizontal spacer portion 114h of the external gate spacer 114 directly disposed on the fin structure 106, and (v) an interface spacer layer 116 disposed on the fin region of the fin structure 106 directly below the external gate spacer 114.

[0040] Figure 3 According to some embodiments, a method for manufacturing a Figure 1B-Figure 1E 1. A flow chart of an example method 300 of a GAA FET 100 is shown in FIG. 1. For illustrative purposes, reference will be made to FIG. Figure 4-Figure 20 An example manufacturing process for manufacturing the GAA FET 100 is shown to describe Figure 3 The operation shown. Figure 4-Figure 20 The GAA FET 100 is shown in FIG. 1 at different stages of manufacturing the GAA FET 100 according to some embodiments. Figure 1A AA cross-sectional view of the method 300. The operations may be performed in a different order or not performed depending on the specific application. It should be noted that the method 300 may not produce a complete GAA FET 100. Therefore, it will be understood that other processes may be provided before, during, and after the method 300, and some of the other processes may only be briefly described here. Unless otherwise mentioned, the method 300 is described in detail. Figure 1A-1E , Figure 2 and Figure 11-Figure 16 Discussions of elements with the same annotation apply to each other.

[0041] refer to Figure 3 In operation 305, a superlattice structure having a nanostructure layer and a nanostructure sacrificial layer is formed on the base structure. Figure 4 As shown, a superlattice structure 111 (also referred to as a "nanosheet stack 111") is formed on a fin-shaped base structure 106, which is formed on a substrate 102. The superlattice structure 111 may include nanostructure layers 108 and nanostructure sacrificial layers 109 arranged in an alternating configuration. In some embodiments, the nanostructure layers 108 may include Si, and the nanostructure sacrificial layers 109 may include SiGe.

[0042] refer to Figure 3 In operation 310, an oxide layer is formed on the superlattice structure, and a polysilicon structure is formed on the oxide layer. Figure 4 and Figure 5 As described above, an oxide layer 516 is formed on the topmost nanostructure layer 108 of the superlattice structure 111, and a polysilicon structure 512 is formed on the oxide layer 516. In some embodiments, the formation of the oxide layer 516 may include: (i) performing an oxidation process on the superlattice structure 111 to form a thermal oxide layer 416, such as Figure 4 and (ii) after forming the polysilicon structure 512, performing an etching process on the thermal oxide layer 416 to form an oxide layer 516, such as Figure 5As shown. In such an embodiment, the oxide layer 516 may include an oxide (e.g., SiO2) of the material (e.g., Si) of the topmost nanostructure layer 108 of the superlattice structure 111. In some embodiments, the formation of the oxide layer 516 may include: (i) exposing the topmost nanostructure layer 108 of the superlattice structure 111 to a precursor, such as tetraethylorthosilicate (TEOS), at a temperature of about 650° C. to about 750° C. in a chemical vapor deposition (CVD) process to deposit the chemical oxide layer 416 (e.g., SiO2), such as Figure 4 and (ii) after forming the polysilicon structure 512, the chemical oxide layer 416 is subjected to an etching process to form an oxide layer 516, such as Figure 5 shown.

[0043] In some embodiments, the formation of the polysilicon structure 512 may include the following sequential operations: (i) depositing an amorphous, polycrystalline or single-crystalline polysilicon layer 412 on the thermal oxide layer or chemical oxide layer 416, such as Figure 4 and (ii) performing a patterning process (eg, a photolithography process) and an etching process on the polysilicon layer 412 to form a polysilicon structure 512, such as Figure 5 As shown. In some embodiments, the same etching process can be used to etch the oxide layer 416 and the polysilicon layer 412. Therefore, the oxide layer 516 can be formed with inclined sidewalls and extended oxide regions 516ex, and due to the difference in etching selectivity between the materials of the oxide layer 416 and the polysilicon layer 412, the extended oxide regions 516ex extend laterally beyond the sidewalls of the polysilicon structure 512. In the process of replacing the polysilicon structure 512 and the oxide layer 516 with the gate structure 112, these extended oxide regions 516ex can cause interface gaps to be formed between the external gate spacers 114 and the topmost nanostructure layer 108. In order to avoid the gate structure 112 from extending into these interface gaps and avoiding being formed under the external gate spacers 114 (which may cause current leakage between the gate structure 112 and the S / D region 110), the interface gaps are filled with an interface spacer layer 116, as described below with reference to Figure 9-Figure 17 described.

[0044] refer to Figure 3 In operation 315, an outer gate spacer and an inner gate spacer are formed on the superlattice structure. Figure 6 and Figure 7 As described above, an external gate spacer 614 and an internal gate spacer 118 are formed on the superlattice structure 111. In some embodiments, the formation of the external gate spacer 614 may include the following sequential operations: (i) Figure 5(ii) performing an annealing process to densify the dielectric material layer; and (iii) etching a horizontal portion of the densified dielectric material layer on the superlattice structure 111 to form an external gate spacer 614 with a thickness of T1, such as Figure 6 In a subsequent operation, the external gate spacer 614 is thinned to a thickness T7 to form an external gate spacer 114, as shown in FIG. Fig.17 shown.

[0045] The formation of the internal gate spacer 118 may include the following sequential operations: (i) Figure 6 The structure of FIG. 1 is subjected to an etching process to etch the portion of the superlattice structure 111 that is not covered by the polysilicon structure 512 and the external gate spacer 614 and form an opening 710, as shown in FIG. Figure 7 (ii) performing an etching process on the sidewalls of the nanostructure sacrificial layer 109 facing the opening 710 to form an inner gate spacer opening (not shown); (iii) depositing a dielectric material layer (not shown) on the sidewalls of the outer gate spacer 614 and the nanostructure layer 108, and on the top surfaces of the polysilicon structure 512, the outer gate spacer 614, and the base structure 106 to fill the inner gate spacer opening; and (iv) performing an etching process on the dielectric material layer to form Figure 7 structure.

[0046] In some embodiments, etching the superlattice structure 111 to form the opening 710 may include a plasma-based dry etching process using an etching gas (e.g., carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr)) and a mixed gas (e.g., hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar)). The etching may be performed at a temperature of about 25°C to about 200°C and a pressure of about 5mTorr to about 50mTorr. The flow rate of the etching gas may be about 5 standard cubic centimeters per minute (sccm) to about 100sccm. The plasma power may be about 50W to about 200W, with a bias voltage of about 30V to about 200V.

[0047] In some embodiments, the etching of the sidewalls of the nanostructure sacrificial layer 109 may include a dry etching process with a higher etching selectivity for SiGe of the nanostructure sacrificial layer 109 than for Si of the nanostructure layer 108. For example, a halogen-based chemical may exhibit a higher etching selectivity for Ge than for Si. Therefore, the halogen gas may etch SiGe faster than Si. In some embodiments, the halogen-based chemical may include a fluorine-based and / or chlorine-based gas. Alternatively, the etching of the nanostructure sacrificial layer 109 may include a wet etching process with a higher selectivity for SiGe than for Si. For example, the wet etching process may include using a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) and / or a mixture of ammonium hydroxide (NH4OH) with H2O2 and deionized water (DI).

[0048] In some embodiments, etching the dielectric material layer to form the inner gate spacer 118 may include an anisotropic dry etching process, and the etching rate along the Z axis may be higher than the etching rate along the X axis or the Y axis. Therefore, portions of the dielectric material layer located on the sidewalls of the outer gate spacer 614 and the nanostructure layer 108 and on the top surfaces of the polysilicon structure 512, the outer gate spacer 614, and the base structure 106 may be etched without etching portions of the dielectric material layer located in the inner gate spacer openings.

[0049] refer to Figure 3 In operation 320, S / D regions are formed in the superlattice structure. Figure 8 As shown, the S / D region 110 is formed in the superlattice structure 111. In some embodiments, the formation of the S / D region 110 may include epitaxially growing a semiconductor material (eg, Si or SiGe) having an n-type or p-type dopant in the opening 710, such as Figure 8 After forming the S / D region 110, an ESL layer 120 and an ILD layer 122 may be formed. Figure 8 shown.

[0050] refer to Figure 3 In operation 325, an interface spacer layer is formed between the external gate spacer and the superlattice structure. Figure 9-Figure 17 As described above, an interface spacer layer 116 is formed between the external gate spacer 114 and the topmost nanostructure layer 108 of the superlattice structure 111. The formation of the interface spacer layer 116 may include the following sequential operations: (i) removing the polysilicon structure 512 to form a gate opening 912 with a width W1, such as Fig. 9 As shown; (ii) Fig. 9 The external gate spacer 614 is subjected to a first oxidation process to form an oxide layer 1015, such as Fig.10(iii) Fig.10 The first oxide etching process is performed on the structure to reduce the thickness of the oxide layer 1015 from the thickness T3 to the thickness T4, and increase the width of the gate opening 912 from the width W1 to the width W2, as shown in FIG. Fig.11 (iv) Fig.11 The external gate spacer 614 is subjected to a second oxidation process to further oxidize the sidewall portion of the external gate spacer 614 to form an oxide layer 1215, such as Fig.12 as shown; (v) Fig.12 The structure of FIG. 1 is subjected to a second oxide etching process to remove oxide layers 516 and 1215. Fig.13 As shown; (vi) Fig.13 The structure is subjected to a third oxidation process to form an oxide layer 1415. Fig.14 as shown; and (vii) Fig.14 The third oxide etching process is performed to etch the oxide layer 1415 and form the interface spacer layer 116 and the external gate spacer 114, such as Fig.15 , Fig.16 or Fig.17 In some embodiments, according to the etching parameters of the third oxide etching process, a Fig.15 , Fig.16 or Fig.17 The interface spacer layer 116 has a structural profile.

[0051] In some embodiments, the first oxidation process may oxidize Fig. 9 The sidewall portion of the external gate spacer 614 is formed to form an oxide layer 1015 having a thickness T3 of about 4 nm to about 10 nm, as shown in FIG. Fig.10 In some embodiments, the external gate spacer 614 may include a SiOCN, SiOC, or SiON layer, and the first oxidation process may convert a sidewall portion of the SiOCN, SiOC, or SiON layer into SiO2 to form an oxide layer 1015. Due to the formation of the oxide layer 1015, the thickness of the external gate spacer 614 may be reduced from a thickness T1 to a thickness T2, as shown in FIG. Fig.10 As shown. In some embodiments, the first oxidation process may include a high temperature plasma oxidation process. The high temperature plasma oxidation process may include exposing the outer gate spacer 614 to oxygen radicals in a plasma at a high temperature of about 400° C. to about 900° C. and a chamber pressure of about 0.003 torr to about 3.0 torr. The plasma may be generated in a plasma chamber using a gas mixture of oxygen having a flow rate of about 6000 sccm to about 6500 sccm, nitrogen having a flow rate of about 3800 sccm to about 4000 sccm, and hydrogen having a flow rate of about 160 sccm to about 200 sccm.

[0052] In some embodiments, the first oxide etching process may include a wet etching process. The wet etching process may include exposing the oxide layer 1015 to a hydrofluoric (HF) acid solution in deionized (DI) water. The volume ratio between HF acid and DI water (HF:DI) may be about 1:100 to about 1:500.

[0053] In some embodiments, the second oxidation process may further oxidize Fig.11 The sidewall portion of the external gate spacer 614 is formed to form an oxide layer 1215 having a thickness T6 of about 4 nm to about 10 nm, as shown in FIG. Fig.12 In some embodiments, the second oxidation process may be similar to the first oxidation process, and may convert the sidewall portion of the external gate spacer 614 having the SiOCN, SiOC or SiON layer into SiO2 to form an oxide layer 1215. Due to the formation of the oxide layer 1215, the thickness of the external gate spacer 614 may be reduced from thickness T2 to thickness T5, as shown in FIG. Fig.12 shown.

[0054] In some embodiments, the second oxide etching process may include a dry etching process. The dry etching process may include exposing the oxide layers 516 and 1215 to a gas mixture of HF gas and ammonia (NH3) gas at a chamber pressure of about 0.1 torr to about 1.0 torr. The gas ratio of HF to NH3 may be about 1:4 to about 1:5. Removing the oxide layer 516 by the second oxide etching process forms an interface gap 1316 between the outer gate spacer 614 and the topmost nanostructure layer 108, as shown in FIG. Fig.13 The oxide layer 1215 is removed by the second oxide etching process so that the width of the gate opening 912 increases from the width W2 to the width W3, as shown in FIG. Fig.13 shown.

[0055] In some embodiments, the third oxidation process may oxidize the sidewall portion of the external gate spacer 614 exposed in the gate opening 912 to form a vertical portion of the oxide layer 1415 having a thickness T8, such as Fig.14 At the same time, the third oxidation process may oxidize the top surface of the nanostructure layer 108 exposed in the gate opening 912 to form a horizontal portion of the oxide layer 1415, as shown in FIG. Fig.14As shown. The horizontal portion of the oxide layer 1415 extends to fill the interface gap 1316 and is formed with a thickness T9 greater than the thickness T8. In some embodiments, the third oxidation process may be similar to the first oxidation process and may convert the sidewall portion of the external gate spacer 614 having the SiOCN, SiOC, or SiON layer into SiO2 to form a vertical portion of the oxide layer 1415. In some embodiments, the third oxidation process may also convert the top portion of the nanostructure layer 108 having the Si layer into SiO2 to form a horizontal portion of the oxide layer 1415. Due to the formation of the oxide layer 1415, the thickness of the external gate spacer 614 may be reduced from the thickness T5 to the thickness T7, as shown. Fig.14 shown.

[0056] In some embodiments, the third oxide etching process can be similar to the second oxide etching process, except that the duration of the third oxide etching process is shorter than the second oxide etching process. The duration of the third oxide etching process is shorter because the oxide layer 1415 is partially removed to leave some portions of the oxide layer 1415 in the interface gap 1316, which is different from the complete removal of the oxide layer 1215 during the second oxide etching process. The removal of the vertical portion of the oxide layer 1415 by the third oxide etching process increases the width of the gate opening 912 from the width W3 to the width W4, as shown in FIG. Fig.15 , Fig.16 and Fig.17 shown.

[0057] In some embodiments, the oxide layer 1415 may be formed by depositing a layer of insulating oxide material (e.g., SiO2, SiON, SiCN, and SiOCN) using a CVD process or an atomic layer deposition (ALD) process, instead of performing the third oxidation process. In such an embodiment, the thickness of the external gate spacer 614 is maintained at thickness T5, and is not reduced from thickness T5 to thickness T7. Since the thickness of the external gate spacer is maintained at T5, the width of the gate opening 912 is maintained at width W3, and is not increased from width W3 to width W4 after the third oxide etching process.

[0058] As described above, the first, second, and third oxidation and oxide etching processes can be used to form the interface spacer layer 116 and can be used to adjust the width of the gate opening 912 as needed. Therefore, the width of the gate opening 912 (which defines the gate length of the gate structure 112 formed subsequently) may not be limited by the width of the polysilicon structure 512.

[0059] In some embodiments, the first and second oxidation and oxide etching processes may not be performed, and the formation of the interface spacer layer 116 may include the following sequential operations: (i) removing the polysilicon structure 512 to form a gate opening 912 having a width W1, such as Fig. 9 (ii) using a dry etching process similar to the second oxide etching process to remove the oxide layer 516 to form an interface oxide gap 1316, (iii) Fig. 9 The external gate spacer 614 is subjected to a third oxidation process or a CVD or ALD process to form an oxide layer 1415, such as Fig.14 as shown, and (iv) Fig.14 The structure of FIG. 1 is subjected to a third oxide etching process to etch the oxide layer 1415 to form an interface spacer layer 116 and an external gate spacer 114, as shown in FIG. Fig.15 , Fig.16 or Fig.17 shown.

[0060] refer to Figure 3 In operation 330, a gate structure is formed around the nanostructure layer. Figure 18-Figure 20 As described above, a gate structure 112 is formed around the nanostructure layer 108. The formation of the gate structure 112 may include the following sequential operations: (i) Fig.15 , Fig.16 or Fig.17 (ii) performing an oxidation process on the exposed areas of the nanostructure layer 108 in the gate openings 912 and 1812 to form an IL layer 112A, such as Fig.18 (iii) forming a HK gate dielectric layer 112B on the IL layer 112A, as shown in FIG. Fig.19 (iv) forming a conductive layer 112C on the HK gate dielectric layer 112B, as shown in FIG. Fig.19 (v) etching the HK gate dielectric layer 112B and the conductive layer 112C in the outer gate portion 113A; and (vi) forming a gate cap layer 112D on the HK gate dielectric layer 112B and the conductive layer 112C, as shown in FIG. Fig. 20 In some embodiments, after forming the gate structure 112, a contact structure 124 may be formed on the S / D region 110, as shown in FIG. Fig. 20 shown.

[0061] The present disclosure provides example structures and methods for improving the bottom angle profile of the gate structure in the FET to prevent current leakage between the gate structure and the source / drain (S / D) region in the FET. In some embodiments, the FET (e.g., GAAFET 100) may have a nanostructure channel region (e.g., nanostructure channel region 108) disposed on a substrate, a gate structure (e.g., gate structure 112) disposed around the nanostructure channel region, an S / D region (e.g., S / D region 110) disposed adjacent to the nanostructure channel region, and an external gate spacer (e.g., external gate spacer 114) disposed along the sidewall of the gate structure to electrically isolate the gate structure from the adjacent source / drain region. In some embodiments, there may be an interface gap (e.g., interface gap 1316) between the external gate spacer and the topmost nanostructure channel region. These interface gaps can be filled with an interface spacer layer (e.g., interface spacer layer 116) having an insulating material. The interface spacer layer can prevent the bottom corner portion of the gate structure (e.g., bottom corner region 112cr) from being formed in the interface gap during the formation of the gate structure. Preventing the bottom corner portion of the gate structure from extending below the external gate spacer can increase the spacing between the gate structure and the adjacent S / D region, prevent current leakage between the gate structure and the adjacent S / D region or minimize the probability of current leakage, and improve device performance. Therefore, by using an interface spacer layer, the bottom angle profile of the gate structure can be controlled. According to the sidewall profile of the interface spacer layer (e.g., the right angle profile of sidewall 116s1, the inclined profile of sidewall 116s2, and the curved profile of sidewall 116s3), the gate structure can have a U-shaped cross-sectional profile, and its bottom corner has a right angle corner profile, a bevel corner profile, or a rounded corner profile.

[0062] In some embodiments, a semiconductor device includes a substrate, a semiconductor layer disposed on the substrate, an S / D region disposed adjacent to the semiconductor layer, a gate structure disposed on the semiconductor layer, an interface spacer layer having a triangular cross-sectional profile disposed along a sidewall of the gate structure, and a gate spacer. The gate spacer includes a first spacer portion and a second spacer portion, the first spacer portion including a first bottom surface having a substantially linear profile disposed on the semiconductor layer, and the second spacer portion including a second bottom surface having an inclined profile disposed on the interface spacer layer.

[0063] In some embodiments, a semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a gate spacer disposed along a sidewall of the gate structure, and an interface spacer layer. The interface spacer layer includes a first sidewall, a second sidewall, and a bottom surface, the first sidewall having an inclined profile facing a bottom surface of the spacer, the second sidewall facing a sidewall of the gate structure, and the bottom surface facing a top surface of the fin structure.

[0064] In some embodiments, a method includes forming an oxide layer on a semiconductor layer, forming a polysilicon structure on the oxide layer, forming a gate spacer on the oxide layer and the polysilicon structure, forming a gate opening by removing the polysilicon structure, forming an interface spacer layer between a bottom surface of the gate spacer and a top surface of the semiconductor layer, and forming a gate structure in the gate opening and in contact with the interface spacer layer and the gate spacer.

[0065] The above disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0066] Example 1 is a semiconductor device comprising: a substrate; a semiconductor layer disposed on the substrate; a source / drain region disposed adjacent to the semiconductor layer; a gate structure disposed on the semiconductor layer; an interface spacer layer disposed along a side wall of the gate structure and comprising a triangular cross-sectional profile; and a gate spacer comprising: a first spacer portion comprising a first bottom surface having a substantially linear profile disposed on the semiconductor layer; and a second spacer portion comprising a second bottom surface having an inclined profile disposed on the interface spacer layer.

[0067] Example 2. The semiconductor device of claim 1, wherein the interface spacer layer includes a sidewall having a substantially linear profile facing the gate structure.

[0068] Example 3. The semiconductor device of claim 1, wherein the interface spacer layer includes a sidewall having an inclined profile facing the gate structure.

[0069] Example 4. The semiconductor device of claim 1, wherein the interface spacer layer includes a sidewall having a curved profile facing the gate structure.

[0070] Example 5. The semiconductor device of claim 1, wherein the interface spacer layer is disposed between the gate spacer and the semiconductor layer.

[0071] Example 6. The semiconductor device of claim 1, wherein the interface spacer layer comprises an oxide of a material of the gate spacers.

[0072] Example 7. The semiconductor device of claim 1 , wherein the interface spacer layer comprises an oxide of a material of the semiconductor layer.

[0073] Example 8. The semiconductor device of claim 1 , wherein a bottom corner of the gate structure comprises a beveled corner profile and contacts the interface spacer layer.

[0074] Example 9. The semiconductor device of claim 1, wherein a bottom corner of the gate structure comprises a rounded corner profile and contacts the interface spacer layer.

[0075] Example 10. The semiconductor device of claim 1, wherein the gate structure comprises: a gate oxide layer in contact with the interface spacer layer; and a gate dielectric layer in contact with the interface spacer layer.

[0076] Example 11 is a semiconductor device, comprising: a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; a gate spacer disposed along the side wall of the gate structure; and an interface spacer layer, comprising: a first side wall having an inclined profile facing the gate spacer; a second side wall facing the side wall of the gate structure; and a bottom surface facing the top surface of the fin structure.

[0077] Example 12. The semiconductor device of claim 11, wherein the interface spacer layer is disposed between the gate spacer and the fin structure.

[0078] Example 13. The semiconductor device of claim 11, wherein the second sidewall comprises a substantially linear profile.

[0079] Example 14. The semiconductor device of claim 11, wherein the second sidewall comprises a sloped profile.

[0080] Example 15. The semiconductor device of claim 11, wherein the second sidewall comprises a curved profile.

[0081] Example 16. The semiconductor device of claim 11, wherein the gate structure comprises: a gate oxide layer in contact with the interface spacer layer; and a gate dielectric layer in contact with the interface spacer layer.

[0082] Example 17 is a method for forming a semiconductor device, comprising: forming an oxide layer on a semiconductor layer; forming a polysilicon structure on the oxide layer; forming a gate spacer on the oxide layer and the polysilicon structure; forming a gate opening by removing the polysilicon structure; forming an interface spacer layer between a bottom surface of the gate spacer and a top surface of the semiconductor layer; and forming a gate structure in the gate opening and in contact with the interface spacer layer and the gate spacer.

[0083] Example 18. The method of claim 17, wherein forming the interface spacer layer comprises oxidizing sidewalls of the gate spacers and a top surface of the semiconductor layer.

[0084] Example 19. The method of claim 17, wherein forming the interface spacer layer comprises exposing an interface gap between a bottom surface of the gate spacer and a top surface of the semiconductor layer.

[0085] Example 20. The method of claim 19, wherein exposing the interface gap comprises etching the oxide layer.

Claims

1. A semiconductor device, comprising: substrate; A semiconductor layer is disposed on the substrate; A source / drain region, disposed adjacent to the semiconductor layer; A gate structure, disposed on the semiconductor layer; an interface spacer layer disposed along a sidewall of the gate structure and comprising a triangular cross-sectional profile; as well as A gate spacer comprising: a first spacer portion including a first bottom surface having a substantially linear profile disposed on the semiconductor layer; as well as A second spacer portion includes a second bottom surface having an inclined profile disposed on the interface spacer layer.

2. The semiconductor device according to claim 1, wherein The interface spacer layer includes a sidewall having a substantially linear profile facing the gate structure.

3. The semiconductor device according to claim 1, wherein The interface spacer layer includes a sidewall having an inclined profile facing the gate structure.

4. The semiconductor device according to claim 1, wherein: The interface spacer layer includes a sidewall having a curved profile facing the gate structure.

5. The semiconductor device according to claim 1, wherein The interface spacer layer is disposed between the gate spacer and the semiconductor layer.

6. The semiconductor device according to claim 1, wherein The interface spacer layer includes an oxide of a material of the gate spacers.

7. The semiconductor device according to claim 1, wherein The interface spacer layer includes an oxide of the material of the semiconductor layer.

8. The semiconductor device according to claim 1, wherein A bottom corner of the gate structure includes a beveled corner profile and contacts the interface spacer layer.

9. A semiconductor device comprising: substrate; A fin structure is disposed on the substrate; A gate structure, disposed on the fin structure; a gate spacer disposed along a sidewall of the gate structure; as well as An interface spacer layer comprising: a first sidewall having an inclined profile facing the gate spacer; a second sidewall facing the sidewall of the gate structure; and A bottom surface faces the top surface of the fin structure.

10. A method of forming a semiconductor device, comprising: forming an oxide layer on the semiconductor layer; forming a polysilicon structure on the oxide layer; forming a gate spacer on the oxide layer and the polysilicon structure; forming a gate opening by removing the polysilicon structure; forming an interface spacer layer between a bottom surface of the gate spacer and a top surface of the semiconductor layer; as well as A gate structure is formed in the gate opening and in contact with the interface spacer layer and the gate spacer.

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