Metal oxide thin film transistor and preparation method thereof

Abstract

The invention relates to an oxide thin film transistor. The oxide thin film transistor comprises a substrate; the active layer is positioned above the substrate and comprises a channel region and a source-drain region; the hydrogen absorption layer is located above the active layer, and the part, located above the channel region, of the hydrogen absorption layer is removed; the hydrogen-rich sealing insulating layer is located above the hydrogen absorption layer, and the part, located above the channel region, of the hydrogen-rich sealing insulating layer is removed; the top gate dielectric layer is positioned above the hydrogen-rich sealing insulating layer and the active layer channel region; the top gate is positioned above the top gate dielectric layer; and the source electrode and the drain electrode are respectively in contact with the hydrogen absorption layer at the two sides of the channel region.

Description

Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a metal oxide thin film transistor and a method for preparing the same. Background Art

[0002] Small-size metal oxide semiconductor thin film transistors (TFTs) are widely used and play an important role in consumer electronics such as smart wearable electronic products due to their high efficiency and high flexibility. The performance requirements for them are becoming increasingly stringent.

[0003] The structure of traditional metal oxide semiconductor thin film transistors (TFTs) mainly includes back gate structure and self-aligned top gate structure. There is a large overlap capacitance between the source, drain and gate of the back gate structure TFT. For TFT devices with shrinking size, the overlap capacitance has a great impact on its operating speed. In contrast, the self-aligned gate-source / drain TFT structure is more suitable for small-sized TFT devices because there is no overlap capacitance. In the self-aligned gate-source / drain TFT structure, the high conductivity of the source and drain regions is usually achieved by introducing a large number of defects in the source and drain regions by bombarding the source and drain regions with argon (Ar) plasma. As the size of TFT devices is further reduced, the impact of the diffusion of source and drain defects on the channel cannot be ignored, resulting in a negative drift of the threshold voltage, thereby affecting the switching ability of the TFT device. In addition, the introduced source and drain defects have poor thermal stability, which limits the application of top gate self-aligned TFTs in three-dimensional integrated circuits with complex thermal processes. Summary of the invention

[0004] In view of the technical problems existing in the prior art, the present application proposes an oxide thin film transistor, comprising: a substrate; an active layer, located above the substrate, including a channel region and a source / drain region; a hydrogen absorption layer, located above the active layer, wherein a portion of the hydrogen absorption layer located above the channel region is removed; a hydrogen-rich sealing insulating layer, located above the hydrogen absorption layer, wherein a portion of the hydrogen-rich sealing insulating layer located above the channel region is removed; a top gate dielectric layer, located above the hydrogen-rich sealing insulating layer and the channel region; a top gate, located above the top gate dielectric layer; a source and a drain, respectively contacting the hydrogen absorption layer on both sides of the channel region.

[0005] In particular, the key point of the structure of the oxide thin film transistor proposed in the present application is that the hydrogen absorption layer can absorb hydrogen in the channel region and the hydrogen-rich sealing insulating layer to form a high-resistance channel region and improve the conductivity of the source and drain regions.

[0006] In particular, the key point of the structure of the oxide thin film transistor proposed in the present application is that a thicker hydrogen-rich sealing insulating layer is introduced under the top gate dielectric layer, so that the overlapping capacitance between the top gate and the source and drain regions is small enough to be ignored, forming a pseudo-self-aligned device structure.

[0007] Particularly, the oxide thin film transistor further comprises: a hydrogen blocking layer located above the substrate; and a buffer layer located above the hydrogen blocking layer; wherein the active layer is located above the buffer layer.

[0008] Particularly, the oxide thin film transistor further comprises: a back gate electrode located above the buffer layer; a back gate dielectric layer located above the buffer layer and the back gate electrode; wherein the active layer is located above the back gate dielectric layer.

[0009] Particularly, the source electrode and the drain electrode are also in contact with the source and drain regions below the hydrogen absorption layer, respectively.

[0010] Particularly, the width of the top gate is greater than the width of the channel region.

[0011] Particularly, the active layer material comprises an amorphous metal oxide, and the hydrogen absorption layer material comprises an indium-rich metal oxide.

[0012] Particularly, the hydrogen-rich sealing insulating layer material includes hydrogen-rich silicon nitride.

[0013] Particularly, the top gate dielectric layer is a breathable insulating material.

[0014] The present application also proposes a method for preparing an oxide thin film transistor, comprising: preparing a substrate; depositing an active layer on the substrate and patterning the active layer; depositing a hydrogen absorption layer on the active layer; depositing a hydrogen-rich sealing insulating layer on the hydrogen absorption layer; patterning the hydrogen absorption layer and the hydrogen-rich sealing insulating layer, removing the hydrogen absorption layer and the hydrogen-rich sealing insulating layer above the channel region to expose the channel region; depositing a top gate dielectric layer on the channel region of the active layer and the hydrogen-rich sealing insulating layer, and performing an annealing operation; patterning the top gate dielectric layer and the hydrogen-rich sealing insulating layer to form source-drain electrode contact holes; depositing a metal layer on the top gate dielectric layer and patterning it to form a top gate, and a source and a drain that at least penetrate into the source-drain electrode contact holes.

[0015] In particular, the method for preparing an oxide thin film transistor further includes: depositing a hydrogen blocking layer on the substrate; depositing a buffer layer on the hydrogen blocking layer; depositing the active layer on the buffer layer, and patterning the active layer.

[0016] The present application also proposes a method for preparing an oxide thin film transistor, comprising: preparing a substrate; depositing a buffer layer on the substrate; depositing a first metal layer on the buffer layer and patterning it to form a back gate; depositing a back gate dielectric layer on the back gate and the buffer layer; depositing an active layer on the back gate dielectric layer and patterning the active layer; depositing a hydrogen absorption layer on the active layer; depositing a hydrogen-rich sealing insulating layer on the hydrogen absorption layer; patterning the hydrogen absorption layer and the hydrogen-rich sealing insulating layer, removing the hydrogen absorption layer and the hydrogen-rich sealing insulating layer above the channel region to expose the channel region; depositing a top gate dielectric layer on the channel region of the active layer and the hydrogen-rich sealing insulating layer, and performing an annealing operation; patterning the top gate dielectric layer and the hydrogen-rich sealing insulating layer to form source-drain electrode contact holes; depositing a second metal layer on the top gate dielectric layer and patterning it to form a top gate, and a source and a drain at least deep into the source-drain electrode contact holes.

[0017] In particular, the method for preparing the oxide thin film transistor further includes: depositing a hydrogen blocking layer on the substrate; and depositing a buffer layer on the hydrogen blocking layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1a to Figure 1b is a cross-sectional view of a thin film transistor according to an embodiment of the present application; Figure 2 is a flow chart of a method for preparing a thin film transistor according to an embodiment of the present application; Figure 3a to Figure 3h yes Figure 1a to Figure 1b A diagram showing a state of fabrication of a thin film transistor of the embodiment shown; Figure 4a to Figure 4b is a cross-sectional view of a thin film transistor according to another embodiment of the present application; Figure 5 is a flow chart of a method for preparing a thin film transistor according to another embodiment of the present application; Figure 6a to Figure 6h yes Figure 4a to Figure 4b A diagram showing the fabrication state of the thin film transistor of the embodiment shown. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In the following detailed description, reference may be made to the various drawings of the specification sheets which are part of the present application and are used to illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0021] The technologies, methods and devices known to those skilled in the art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0022] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor, wherein the control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, the corresponding second electrode may be the source or drain of the field effect transistor, and the control electrode or the third electrode may be the gate; when the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, the corresponding second electrode may be the emitter or collector of the bipolar transistor, and the control electrode or the third electrode may be the base. The transistor may be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process.

[0023] Figure 1a to Figure 1b is a structural cross-sectional view of an oxide thin film transistor according to an embodiment of the present application.

[0024] According to one embodiment, the oxide thin film transistor may include a substrate 101. In one embodiment of the present application, the substrate 101 may include PEN or other flexible insulating materials such as PI, PET, or may include rigid materials such as hard substrate silicon, glass, etc.

[0025] According to one embodiment, the oxide thin film transistor may further include an active layer 102, which is located above the substrate 101. The active layer 102 material may include amorphous indium gallium zinc oxide (a-IGZO), amorphous indium zinc oxide (a-IZO), amorphous indium gallium oxide (a-IGO), etc., with a thickness of not less than 1 nm. The active layer 102 may include a channel region 1021, a source region 1022, and a drain region 1023.

[0026] According to one embodiment, the oxide thin film transistor may further include a hydrogen absorption layer 103 located above the active layer 102. The hydrogen absorption layer 103 includes two parts isolated from each other, and the hydrogen absorption layer above the channel region 1021 is removed. The hydrogen absorption layer 103 may be made of an indium-rich metal oxide with good conductivity, such as indium zinc oxide (IZO) or indium oxide (In2O3) with a high indium content.

[0027] According to one embodiment, the oxide thin film transistor may further include a hydrogen-rich sealing insulating layer 104 located above the hydrogen absorption layer 103. The material of the hydrogen-rich sealing insulating layer 104 may include, for example, hydrogen-rich silicon nitride (Si3N4:H). The hydrogen-rich sealing insulating layer 104 includes two parts isolated from each other, and the hydrogen-rich sealing insulating layer above the channel region 1021 is removed.

[0028] According to one embodiment, since hydrogen has a high chemical activity and can be combined with oxygen in the indium-rich metal oxide to form a HO bond or combined with In to form an In-H bond, the hydrogen absorption layer 103 can absorb hydrogen impurities. In addition, in addition to absorbing hydrogen impurities in the channel region 1021 and the hydrogen-rich sealing insulating layer 104 to increase the carrier concentration in the source and drain regions, the hydrogen absorption layer 103 can also directly contact the metal oxide in the source and drain regions of the active layer 102 to further improve the conductivity of the source and drain regions.

[0029] According to one embodiment, the hydrogen absorption layer 103 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 104 and the channel region 1021, ensuring a low hydrogen content in the channel region 1021 and forming a highly resistive channel region. The hydrogen absorption layer 103 absorbs hydrogen impurities, and the hydrogen content increases, while the hydrogen content in the source region 1022 and the drain region 1023 is relatively low. Therefore, a concentration gradient is generated between the hydrogen absorption layer 103 and the hydrogen content in the source region 1022 and the drain region 1023. Affected by the concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 103 will diffuse into the source region 1022 and the drain region 1023 to form a highly conductive source-drain region, thereby precisely controlling the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 1021, and increasing the hydrogen content in the source region 1022 and the drain region 1023. Such a structure can improve the conductivity of the source and drain regions, avoid the process in which defects are generated by plasma bombardment to form highly conductive source and drain regions in the existing solution, and avoid the influence of defects in the source and drain regions on the channel region.

[0030] According to one embodiment, the oxide thin film transistor may further include a top gate dielectric layer 105 located above the hydrogen-rich sealing insulating layer 104 and the channel region 1021. The material of the top gate dielectric layer 105 may include a gas-permeable material such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO x ) etc. The hydrogen in the channel region 1021 can also be discharged to the outside through the top gate dielectric layer 105 during the transistor manufacturing process, thereby ensuring a low hydrogen content in the channel region 1021 .

[0031] According to one embodiment, the oxide thin film transistor may further include a top gate 106, whose width is greater than the width of the channel region 1021. There is a certain amount of overlap between the top gate 106 and the source region 1022 and the drain region 1023. However, a hydrogen-rich sealing insulating layer 104 with a thickness of not less than 100 nm is introduced under the top gate dielectric layer 105, so that the overlap capacitance between the top gate 106 and the source region 1022 and the drain region 1023 is small enough to be ignored, forming a pseudo self-aligned device structure.

[0032] According to one embodiment, the oxide thin film transistor may further include a source electrode 107 and a drain electrode 108. The source electrode 107 and the drain electrode 108 may be made of metal molybdenum (Mo) with a thickness of not less than 20 nm.

[0033] According to one embodiment, Figure 1b As shown, the source 107 and the drain 108 may extend downward and directly contact the source and drain regions in the active layer 102 , respectively.

[0034] Figure 2 It is a flow chart of a method for preparing a thin film transistor according to an embodiment of the present application. Figure 3a to Figure 3h yes Figure 1a to Figure 1b A diagram showing the fabrication state of the thin film transistor of the embodiment shown.

[0035] Step 201: Figure 3a As shown, a substrate 301 is prepared.

[0036] Step 202: Figure 3b As shown, an active layer 302 is deposited on a substrate 301. The material of the active layer 302 may include a-IGZO, a-IZO, a-IGO, etc., with a thickness of not less than 1 nm. The active layer is then patterned by a photolithography process to form an active island.

[0037] Step 203, such as Figure 3c As shown, a hydrogen absorption layer 303 is deposited on the active layer 302. Since the indium-rich material has a strong ability to combine with hydrogen, the hydrogen absorption layer 303 material may include an indium-rich metal oxide with good conductivity, such as IZO or In2O3 with a high indium content, with a thickness of not less than 1 nm.

[0038] Step 204, such as Figure 3d As shown, a hydrogen-rich sealing insulating layer 304 is deposited on the hydrogen absorption layer 303. The material of the hydrogen-rich sealing insulating layer 304 may include, for example, Si3N4:H, etc., and the thickness is not less than 100 nm.

[0039] Step 205, such as Figure 3e As shown, the hydrogen absorption layer 303 and the hydrogen-rich sealing insulating layer 304 are patterned, and a portion of the hydrogen absorption layer and the hydrogen-rich sealing insulating layer is removed to expose the channel region 3021 .

[0040] Step 206, such as Figure 3f As shown, a top gate dielectric layer 305 is deposited on the channel region 3021 and the hydrogen-rich sealing insulating layer 304. The material of the top gate dielectric layer 305 can be SiO2, Al2O3, HfO x The thickness is not less than 1 nm.

[0041] Step 207, annealing is performed on the structure formed by the above process, and the annealing temperature can be 300°C to 400°C, and the annealing atmosphere is oxygen (O2). During the annealing process, oxygen can enter the channel region 3021 of the active layer through the top gate dielectric layer 305, repair defects such as oxygen vacancies, and make the channel region 3021 highly resistive; at the same time, hydrogen impurities in the channel region 3021 can also be discharged to the outside through the top gate dielectric layer 305.

[0042] According to one embodiment, the hydrogen absorption layer 303 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 304 and the intermediate channel region 3021, ensuring a low hydrogen content in the channel region 3021 and forming a highly resistive channel region. Affected by the concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 303 will diffuse to the source region 3022 and the drain region 3023, forming a highly conductive source-drain region, thereby precisely controlling the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 3021, and increasing the hydrogen content in the source region 3022 and the drain region 3023.

[0043] Step 208, as Figure 3g As shown, the top gate dielectric layer 305 and the hydrogen-rich sealing insulating layer 304 are patterned to form a source contact hole 3061 and a drain contact hole 3062 .

[0044] According to one embodiment, the source contact hole 3061 and the drain contact hole 3062 may extend downward and directly contact the source and drain regions in the active layer 302 , respectively.

[0045] Step 209, as Figure 3h As shown, a metal layer is deposited on the top gate dielectric layer 305 and in the source contact hole 3061 and the drain contact hole 3062, and patterned to form a top gate 308, as well as a source 3071 and a drain 3072 that at least penetrate into the source contact hole 3061 and the drain contact hole 3062. The material may be Mo with a thickness of not less than 20 nm.

[0046] According to an embodiment, step 209 may adopt another implementation method, specifically comprising: depositing metal electrodes in the source contact hole 3061 and the drain contact hole 3062 and performing a lift-off process to form a source 3071 and a drain 3072. Depositing a metal layer on the top gate dielectric layer 305 and patterning it to form a top gate 308.

[0047] According to one embodiment, the width of the top gate 308 is greater than the width of the channel region 3021, and there is a certain amount of overlap between the top gate 308 and the source region 3022 and the drain region 3023. However, a hydrogen-rich sealing insulating layer 304 with a thickness of not less than 100 nm is introduced under the top gate dielectric layer 305, so that the overlap capacitance between the top gate 308 and the source region 3022 and the drain region 3023 is small enough to be ignored, forming a pseudo self-aligned device structure.

[0048] Figure 4a to Figure 4b is a structural cross-sectional view of a dual-gate oxide thin film transistor according to an embodiment of the present application.

[0049] According to one embodiment, the dual-gate oxide thin film transistor may include a substrate 401 .

[0050] According to one embodiment, the dual-gate oxide thin film transistor may further include a hydrogen blocking layer 402, which is located above the substrate 401 and has a thickness of not less than 1 nm. According to one embodiment, the hydrogen blocking layer 402 may include a highly dense Al2O3, HfO x , or HfO x Hydrogen is transported by Al2O3, HfO x After absorption, with Al2O3, HfO x The hydrogen blocking layer 402 combines with oxygen vacancies or oxygen atoms in the TFT to reduce the amount of hydrogen diffused into the TFT. Therefore, the hydrogen blocking layer 402 can improve the hydrogen resistance of the TFT.

[0051] According to one embodiment, the dual-gate oxide thin film transistor may further include a buffer layer 403, which is located above the hydrogen blocking layer 402 and has a thickness greater than 1 nm. The material of the buffer layer 403 may include SiO2, SiN x 、Al2O3、HfO x etc., or a stack of the foregoing materials.

[0052] According to one embodiment, the dual-gate oxide thin film transistor may further include a back gate electrode 404 located above the buffer layer 403. The back gate electrode 404 may be made of Mo.

[0053] According to one embodiment, the dual-gate oxide thin film transistor may further include a back gate dielectric layer 405 located above the buffer layer 403 and the back gate electrode 404. The material of the back gate dielectric layer 405 may include SiO2, Al2O3, HfO x wait.

[0054] According to one embodiment, the dual-gate oxide thin film transistor may further include an active layer 406 located above the back gate dielectric layer 405. The active layer 406 material may include a-IGZO, amorphous a-IZO, a-IGO, etc., with a thickness of not less than 1 nm. The active layer 406 may include a channel region 4061, a source region 4062, and a drain region 4063.

[0055] According to one embodiment, the dual-gate oxide thin film transistor may further include a hydrogen absorption layer 407, which is located above the active layer 406. The hydrogen absorption layer 407 includes two parts isolated from each other, and the hydrogen absorption layer above the channel region 4061 is removed. The hydrogen absorption layer 407 may be made of an indium-rich metal oxide with good conductivity, such as IZO or In2O3 with a high indium content.

[0056] According to one embodiment, the dual-gate oxide thin film transistor may further include a hydrogen-rich sealing insulating layer 408, which is located above the hydrogen absorption layer 407. The material of the hydrogen-rich sealing insulating layer 408 may include, for example, Si3N4:H, etc. The hydrogen-rich sealing insulating layer 408 includes two parts isolated from each other, and the hydrogen-rich sealing insulating layer above the channel region 4061 is removed.

[0057] According to one embodiment, since hydrogen has a high chemical activity and can be combined with oxygen in the indium-rich metal oxide to form a HO bond or combined with In to form an In-H bond, the hydrogen absorption layer 407 can absorb hydrogen impurities. In addition, in addition to absorbing hydrogen impurities in the channel region 4061 and the hydrogen-rich sealing insulating layer 408 to increase the carrier concentration in the source and drain regions, the hydrogen absorption layer 407 can also directly contact the metal oxide in the source and drain regions of the active layer 406 to further improve the conductivity of the source and drain regions.

[0058] According to one embodiment, the hydrogen absorption layer 407 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 408 and the channel region 4061, ensuring a low hydrogen content in the channel region 4061 and forming a highly resistive channel region. The hydrogen absorption layer 407 absorbs hydrogen impurities, and the hydrogen content increases, while the hydrogen content in the source region 4062 and the drain region 4063 is relatively low. Therefore, a concentration gradient is generated between the hydrogen absorption layer 407 and the hydrogen content in the source region 4062 and the drain region 4063. Affected by the concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 407 will diffuse to the source region 4062 and the drain region 4063 to form a highly conductive source-drain region, thereby precisely controlling the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 4061, and increasing the hydrogen content in the source region 4062 and the drain region 4063. Such a structure can improve the conductivity of the source and drain regions, avoid the process in which defects are generated by plasma bombardment to form highly conductive source and drain regions in the existing solution, and avoid the influence of defects in the source and drain regions on the channel region.

[0059] According to one embodiment, the dual-gate oxide thin film transistor may further include a top gate dielectric layer 409 located above the hydrogen-rich sealing insulating layer 408 and the channel region 4061. The material of the top gate dielectric layer 409 may include a gas-permeable material such as SiO2, Al2O3, HfO x The hydrogen in the channel region 4061 can also be discharged to the outside through the top gate dielectric layer 409 during the transistor manufacturing process, thereby ensuring a low hydrogen content in the channel region 4061 .

[0060] According to one embodiment, the dual-gate oxide thin film transistor may further include a top gate 410, whose width is greater than the width of the channel region 4061. There is a certain amount of overlap between the top gate 410 and the source region 4062 and the drain region 4063. However, a hydrogen-rich sealing insulating layer 408 with a thickness of not less than 100 nm is introduced under the top gate dielectric layer 409, so that the overlap capacitance between the top gate 410 and the source region 4062 and the drain region 4063 is small enough to be ignored, forming a pseudo self-aligned device structure.

[0061] According to one embodiment, the dual-gate oxide thin film transistor may further include a source 411 and a drain 412 , the material of which may include Mo, and the thickness of which is not less than 20 nm.

[0062] According to one embodiment, Figure 4b As shown, the source 411 and the drain 412 may extend downward and directly contact the source and drain regions in the active layer 406 , respectively.

[0063] Figure 5 It is a flow chart of a method for preparing a dual-gate oxide thin film transistor according to an embodiment of the present application. Figure 6a to Figure 6h yes Figure 4a to Figure 4b A diagram showing the manufacturing state of the dual-gate oxide thin film transistor of the embodiment shown.

[0064] Step 501, preparing a substrate 601.

[0065] Step 502, depositing a hydrogen barrier layer 602 on the substrate 601, the hydrogen barrier layer 602 material may include highly dense Al2O3, HfO x , or HfO x The stacking layer with Al2O3 has a thickness of not less than 1 nm. The hydrogen barrier layer can improve the hydrogen resistance of TFT.

[0066] Step 503, depositing a buffer layer 603 on the hydrogen barrier layer 602, the material of which may be SiO2, SiN x 、Al2O3、HfO x etc., or a stack of the above materials, with a thickness greater than 1 nm.

[0067] Step 504, such as Figure 6a As shown, a back gate electrode 604 is deposited on the buffer layer 603. The material of the back gate electrode 604 may include Mo, and the thickness is not less than 20 nm. The back gate electrode 604 is patterned to form a back gate electrode pattern.

[0068] Step 505, such as Figure 6b As shown, a back gate dielectric layer 605 is deposited on the buffer layer 603 and the back gate electrode 604. The material of the back gate dielectric layer 605 may include SiO2, Al2O3, HfO xThe thickness is not less than 1 nm.

[0069] Step 506, such as Figure 6c As shown, an active layer 606 is deposited on the back gate dielectric layer 605. The material of the active layer 606 may include a-IGZO, a-IZO, a-IGO, etc., with a thickness of not less than 1 nm. The active layer 606 is then patterned to form an active island.

[0070] Step 507, depositing a hydrogen absorption layer 607 on the active layer 606. Since the indium-rich material has a strong ability to bind hydrogen, the hydrogen absorption layer 607 may include an indium-rich metal oxide with good conductivity, such as IZO or In2O3 with a high indium content.

[0071] Step 508, such as Figure 6d As shown, a hydrogen-rich sealing insulating layer 608 is deposited on the hydrogen absorption layer 607. The material of the hydrogen-rich sealing insulating layer 608 may include, for example, Si3N4:H, etc., and the thickness is not less than 100 nm.

[0072] Step 509, such as Figure 6e As shown, the hydrogen absorption layer 607 and the hydrogen-rich sealing insulating layer 608 are patterned, and a portion of the hydrogen absorption layer and the hydrogen-rich sealing insulating layer is removed to expose the channel region 6061 .

[0073] Step 510, such as Figure 6f As shown, a top gate dielectric layer 609 is deposited on the channel region 6061 and the hydrogen-rich sealing insulating layer 608. The material of the top gate dielectric layer 609 can be SiO2, Al2O3, HfO x Materials such as aluminum foil and aluminum foil, with a thickness of not less than 1 nm.

[0074] Step 511, annealing is performed on the structure formed by the above process, the annealing temperature is 300°C to 400°C, and the annealing atmosphere is O2. During the annealing process, oxygen can enter the channel region 6061 of the active layer through the top gate dielectric layer 609, repair defects such as oxygen vacancies, and make the channel region 6061 highly resistive; at the same time, hydrogen impurities in the channel region 6061 can also be discharged to the outside through the top gate dielectric layer 609.

[0075] According to one embodiment, the hydrogen absorption layer 607 can absorb hydrogen impurities from the hydrogen-rich sealing insulating layer 608 and the intermediate channel region 6061, ensuring a low hydrogen content in the channel region 6061 and forming a highly resistive channel region. Affected by the concentration gradient and temperature, the hydrogen impurities absorbed by the hydrogen absorption layer 607 will diffuse to the source region 6062 and the drain region 6063, forming a highly conductive source-drain region, thereby precisely controlling the distribution of hydrogen in the metal oxide, reducing the hydrogen content in the channel region 6061, and increasing the hydrogen content in the source region 6062 and the drain region 6063.

[0076] Step 512, such as Figure 6g As shown, the top gate dielectric layer 609 and the hydrogen-rich sealing insulating layer 608 are patterned to form a source contact hole 6101 and a drain contact hole 6102 .

[0077] According to one embodiment, the source contact hole 6101 and the drain contact hole 6102 may extend downward and directly contact the source and drain regions in the active layer 606 , respectively.

[0078] Step 513, as Figure 6h As shown, a metal layer is deposited on the top gate dielectric layer 609 and in the source contact hole 6101 and the drain contact hole 6102, and patterned to form a top gate 612, as well as a source 6111 and a drain 6112 that at least penetrate into the source contact hole 6101 and the drain contact hole 6102. The material may be Mo with a thickness of not less than 20 nm.

[0079] According to one embodiment, step 513 may adopt another implementation method, specifically comprising: depositing metal electrodes in the source contact hole 6101 and the drain contact hole 6102 and performing a lift-off process to form a source 6111 and a drain 6112. Depositing a metal layer on the top gate dielectric layer 609 and performing patterning to form a top gate 612.

[0080] According to one embodiment, the width of the top gate 612 is greater than the width of the channel region 6061, and there is a certain amount of overlap between the top gate 612 and the source region 6062 and the drain region 6063. However, a hydrogen-rich sealing insulating layer 608 with a thickness of not less than 100 nm is introduced under the top gate dielectric layer 609, so that the overlap capacitance between the top gate 612 and the source region 6062 and the drain region 6063 is small enough to be ignored, forming a pseudo self-aligned device structure.

[0081] The solution of the present application can avoid using plasma bombardment to form source and drain regions, reduce the formation of defects in the source and drain regions, and at the same time ensure the formation of low-resistance source and drain regions. In addition, since the thickness of the hydrogen-rich layer is controlled to be relatively thick, it can avoid the gate and source and drain overlap capacitance being too large to form a pseudo self-aligned transistor.

[0082] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. An oxide thin film transistor, comprising: substrate; An active layer, located above the substrate, including a channel region and a source / drain region; a hydrogen absorption layer located above the active layer, wherein a portion of the hydrogen absorption layer located above the channel region is removed; a hydrogen-rich sealing insulating layer, located above the hydrogen absorption layer, wherein a portion of the hydrogen-rich sealing insulating layer located above the channel region is removed; A top gate dielectric layer, located above the hydrogen-rich sealing insulating layer and the channel region; A top gate, located above the top gate dielectric layer; as well as, The source electrode and the drain electrode are respectively in contact with the hydrogen absorption layer at two sides of the channel region.

2. The oxide thin film transistor according to claim 1, further comprising a hydrogen blocking layer located above the substrate; and, A buffer layer, located above the hydrogen barrier layer; in, The active layer is located above the buffer layer.

3. The oxide thin film transistor according to claim 2, further comprising: A back gate electrode, located above the buffer layer; as well as A back-gate dielectric layer, located above the buffer layer and the back-gate electrode; Wherein, the active layer is located above the back gate dielectric layer. 4 . The oxide thin film transistor according to claim 1 , wherein the source electrode and the drain electrode are also in contact with the source and drain regions below the hydrogen absorption layer, respectively. 5 . The oxide thin film transistor according to claim 1 , wherein a width of the top gate is greater than a width of the channel region. 6 . The oxide thin film transistor according to claim 1 , wherein the active layer material comprises an amorphous metal oxide, and the hydrogen absorption layer material comprises an indium-rich metal oxide. 7 . The oxide thin film transistor according to claim 1 , wherein the hydrogen-rich sealing insulating layer material comprises hydrogen-rich silicon nitride. 8 . The oxide thin film transistor according to claim 1 , wherein the top gate dielectric layer is a gas permeable insulating material.

9. A method for preparing an oxide thin film transistor, comprising: preparing a substrate; Depositing an active layer on the substrate and patterning the active layer; depositing a hydrogen absorption layer above the active layer; depositing a hydrogen-rich sealing insulating layer above the hydrogen absorbing layer; Patterning the hydrogen absorption layer and the hydrogen-rich sealing insulating layer, removing the hydrogen absorption layer and the hydrogen-rich sealing insulating layer above the channel region, and exposing the channel region; Depositing a top gate dielectric layer in the channel region of the active layer and above the hydrogen-rich sealing insulating layer, and performing annealing treatment; Patterning the top gate dielectric layer and the hydrogen-rich sealing insulating layer to form source-drain electrode contact holes; as well as, A metal layer is deposited on the top gate dielectric layer and patterned to form a top gate, and a source electrode and a drain electrode at least extending into the source-drain electrode contact holes.

10. The method for preparing an oxide thin film transistor according to claim 9, further comprising: depositing a hydrogen barrier layer over the substrate; depositing a buffer layer above the hydrogen barrier layer; as well as, The active layer is deposited on the buffer layer, and the active layer is patterned.

11. A method for preparing an oxide thin film transistor, comprising: preparing a substrate; depositing a buffer layer over the substrate; Depositing a first metal layer on the buffer layer and patterning it to form a back gate; Depositing a back gate dielectric layer above the back gate and the buffer layer; Depositing an active layer on the back gate dielectric layer and patterning the active layer; depositing a hydrogen absorption layer above the active layer; depositing a hydrogen-rich sealing insulating layer above the hydrogen absorbing layer; Patterning the hydrogen absorption layer and the hydrogen-rich sealing insulating layer, removing the hydrogen absorption layer and the hydrogen-rich sealing insulating layer above the channel region, and exposing the channel region; Depositing a top gate dielectric layer in the channel region of the active layer and above the hydrogen-rich sealing insulating layer, and performing an annealing operation; Patterning the top gate dielectric layer and the hydrogen-rich sealing insulating layer to form source-drain electrode contact holes; as well as, A second metal layer is deposited on the top gate dielectric layer and patterned to form a top gate, and a source electrode and a drain electrode at least penetrating into the source-drain electrode contact holes.

12. The method for preparing an oxide thin film transistor according to claim 11, further comprising: depositing a hydrogen barrier layer over the substrate; and, A buffer layer is deposited over the hydrogen barrier layer.

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