Transistor, display panel and preparation method of transistor

Abstract

The embodiment of the invention provides a transistor, a display panel and a preparation method of the transistor, and aims to improve the use performance of the display panel. The transistor is used for an array substrate of a display panel, and comprises a buffer layer; the active layer is arranged on the buffer layer and comprises a semiconductor part, the semiconductor part comprises a channel region and at least two non-channel regions, and the at least two non-channel regions are arranged on the two sides of the channel region; the first insulating layer is arranged on one side, deviating from the buffer layer, of the active layer; the first conducting layer is arranged on the side, away from the active layer, of the first insulating layer, and the first conducting layer comprises a first grid electrode; wherein the orthographic projection of the channel region on the buffer layer and the orthographic projection of the first gate on the buffer layer are at least partially overlapped, and the resistance value of at least one non-channel region is 500-3000 omega.

Description

Technical Field

[0001] The present application relates to the technical field of display components, and in particular to a transistor, a display panel, and a method for manufacturing the transistor. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a transistor, a display panel, and a method for manufacturing the transistor, aiming to improve the performance of the display panel.

[0005] An embodiment of the first aspect of the present application provides a transistor for an array substrate of a display panel, the transistor comprising: a buffer layer; an active layer, arranged on the buffer layer and comprising a semiconductor portion, the semiconductor portion comprising a channel region and a non-channel region, at least two non-channel regions being arranged on both sides of the channel region; a first insulating layer, arranged on a side of the active layer away from the buffer layer; a first conductive layer, arranged on a side of the first insulating layer away from the active layer, the first conductive layer comprising a first gate; wherein an orthographic projection of the channel region on the buffer layer and an orthographic projection of the first gate on the buffer layer at least partially overlap, and a resistance value of at least one non-channel region is 500Ω to 3000Ω.

[0006] According to an implementation of the first aspect of the present application, a resistance value of at least one non-channel region is 900Ω to 2500Ω.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the length of the channel region on the buffer layer in the first direction is less than 4 microns, and at least two non-channel regions are arranged on both sides of the channel region in the first direction.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the length of the channel region on the buffer layer in the first direction is less than 3 micrometers.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, an extension width of an orthographic projection of the channel region on the buffer layer in the second direction is greater than or equal to an extension length of an orthographic projection of the channel region on the buffer layer in the first direction, and the second direction intersects with the first direction.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the two non-channel regions include a source region and a drain region disposed on both sides of the channel region, and the resistance value of the source region and / or the drain region is 500Ω to 3000Ω.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a source and a drain, the source and the source region are electrically connected, and the drain and the drain region are electrically connected.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a second insulating layer located on a side of the first conductive layer away from the active layer, and the source and the drain are located on a side of the second insulating layer away from the first conductive layer.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the carrier mobility in the channel region is greater than 20 cm 2 / Vs.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, the carrier mobility in the channel region is greater than 30 cm 2 / Vs.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, the carrier mobility in the channel region is less than 50 cm 2 / Vs.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, it also includes a second conductive layer, which is located between the active layer and the buffer layer. The second conductive layer includes a second gate, and the orthographic projection of the channel region on the buffer layer and the orthographic projection of the second gate on the buffer layer at least partially overlap.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the channel region on the buffer layer is located within the orthographic projection of the second gate on the buffer layer.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, the channel region is a single-layer structure, or the channel region includes a plurality of sub-layers stacked in a direction away from the buffer layer.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the buffer layer includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0020] According to any of the aforementioned embodiments of the first aspect of the present application, the material of the semiconductor portion includes at least one of indium, gallium, and zinc.

[0021] According to any of the above embodiments of the first aspect of the present application, the material of the semiconductor portion includes InO x , x is one of 1, 2, and 3.

[0022] According to any of the above embodiments of the first aspect of the present application, the material of the semiconductor portion includes InGaO x , x is one of 1, 2, and 3.

[0023] According to any of the above embodiments of the first aspect of the present application, the material of the semiconductor portion includes InZnO x , x is one of 1, 2, and 3.

[0024] According to any of the above embodiments of the first aspect of the present application, the material of the semiconductor portion includes InGaZnO x , x is one of 1, 2, and 3.

[0025] According to any of the aforementioned embodiments of the first aspect of the present application, the orthographic projection of the channel region on the substrate is located within the orthographic projection of the first gate on the substrate.

[0026] The embodiment of the second aspect of the present application further provides an array substrate, comprising a transistor of any of the above-mentioned embodiments of the first aspect.

[0027] According to an implementation of the second aspect of the present application, a test component is further included, the semiconductor portion includes a first end and a second end opposite to each other in its extension direction, the test component is connected between the first end and the second end, and the test component is used to obtain the resistance of the semiconductor portion.

[0028] According to any of the aforementioned embodiments of the second aspect of the present application, the driving circuit includes a switching transistor and a gate driving transistor, and the switching transistor and / or the gate driving transistor are transistors of any of the aforementioned embodiments of the first aspect.

[0029] An embodiment of a third aspect of the present application provides a display panel, comprising an array substrate of any one of the above-mentioned embodiments of the second aspect.

[0030] An embodiment of a fourth aspect of the present application provides a method for manufacturing a transistor, comprising:

[0031] A semiconductor material layer is disposed on one side of the buffer layer, and the semiconductor material layer is patterned to form an active layer, wherein the active layer includes a semiconductor portion, and the semiconductor portion includes a channel region and non-channel regions located on both sides of the channel region;

[0032] Disposing a first insulating layer on a side of the active layer away from the buffer layer;

[0033] A first conductive material layer is disposed on a side of the first insulating layer away from the active layer, and the first conductive material layer is patterned to form a first conductive layer, wherein the first conductive layer includes a first gate, and an orthographic projection of the channel region on the buffer layer and an orthographic projection of the first gate on the buffer layer at least partially overlap;

[0034] Wherein, the resistance value of at least one non-channel region is 500Ω-3000Ω.

[0035] According to an embodiment of the fourth aspect of the present application, ions are implanted into the semiconductor portion from a side of the first conductive layer facing away from the first insulating layer.

[0036] According to any of the aforementioned embodiments of the fourth aspect of the present application, the energy of ion implantation is 5KV to 75KV.

[0037] According to any of the aforementioned embodiments of the fourth aspect of the present application, the dose of ion implantation is 1*10 11 cm 3 ~1*10 15 cm 3 .

[0038] According to any of the aforementioned embodiments of the fourth aspect of the present application, after the step of implanting ions into the semiconductor portion from a side of the first conductive layer away from the first insulating layer, the step further includes:

[0039] The semiconductor portion is subjected to annealing treatment, the annealing temperature is 200° C. to 400° C., and / or the annealing time is 10 minutes to 2 hours.

[0040] According to any of the aforementioned embodiments of the fourth aspect of the present application, in the step of providing a first insulating layer on a side of the active layer away from the buffer layer:

[0041] The first insulating layer is formed by using a chemical vapor deposition process.

[0042] According to any of the aforementioned embodiments of the fourth aspect of the present application, the material of the first insulating layer includes silicon oxide, the chemical vapor deposition gas precursor includes silane gas and nitrous oxide, and the ratio of silane gas to nitrous oxide gas is 0.1 to 0.01.

[0043] According to any of the aforementioned embodiments of the fourth aspect of the present application, the working pressure of chemical vapor deposition is 100Pa to 300Pa.

[0044] According to any of the aforementioned embodiments of the fourth aspect of the present application, the operating power of the chemical vapor deposition is 0.5kW to 10kW.

[0045] According to any of the aforementioned embodiments of the fourth aspect of the present application, it also includes: a second insulating layer is disposed on a side of the first conductive layer away from the first insulating layer.

[0046] According to any of the aforementioned embodiments of the fourth aspect of the present application, a chemical vapor deposition process is selected to form the second insulating layer.

[0047] According to any of the aforementioned embodiments of the fourth aspect of the present application, the material of the second insulating layer includes silicon oxide, the gas precursor of chemical vapor deposition includes silane gas and nitrous oxide, and the ratio of silane gas to nitrous oxide gas is 0.1 to 0.01.

[0048] According to any of the aforementioned embodiments of the fourth aspect of the present application, the working pressure of chemical vapor deposition is 100Pa to 300Pa.

[0049] According to any of the aforementioned embodiments of the fourth aspect of the present application, the operating power of the chemical vapor deposition is 0.5kW to 10kW.

[0050] In the transistor provided in the embodiment of the present application, the transistor includes a buffer layer, an active layer, a first insulating layer and a first conductive layer. The buffer layer provides a supporting buffering function for the device of the transistor. A semiconductor part is provided in the active layer, and the semiconductor part includes a channel region and a non-channel region. The conduction of carriers between the non-channel regions is realized by the conduction of the channel region. The first insulating layer ensures the insulation performance between the first conductive layer and the active layer. The first conductive layer includes a first gate, and the positive projection of the channel region on the buffer layer and the positive projection of the first gate on the buffer layer at least partially overlap, so that the first gate can control whether the channel region is turned on or not. The resistance value of at least one non-channel region is 500Ω to 3000Ω. When the resistance value of the non-channel region is within the above range, when the channel region conducts the carriers of the non-channel region and moves to the channel region, the carrier concentration in the channel region can be effectively controlled, the device characteristics of the transistor are guaranteed, and the yield of the transistor is improved. When the transistor is used in a display panel, the performance of the display panel can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0052] Figure 1 is a schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0053] Figure 2 In one example Figure 1 Sectional view at AA in the middle;

[0054] Figure 3 In another example Figure 1 Sectional view at AA in the middle;

[0055] Figure 4 In another example Figure 1 Sectional view at AA in the middle;

[0056] Figure 5 In another example Figure 1 Sectional view at AA in the middle;

[0057] Figure 6 is a schematic diagram of a driving circuit structure of an array substrate provided in an embodiment of the present application;

[0058] Figure 7 is a structural schematic diagram of a pixel circuit of an array substrate provided in an embodiment of the present application;

[0059] Figure 8 This is a schematic diagram of the connection of a test component of an array substrate provided in an embodiment of the present application;

[0060] Fig. 9 It is a schematic flow chart of a method for preparing a transistor provided in an embodiment of the present application;

[0061] Figures 10 to 12 It is a structural schematic diagram of a transistor manufacturing process provided in an embodiment of the present application;

[0062] Fig.13 is a schematic flow chart of a method for manufacturing a transistor provided in another embodiment of the present application;

[0063] Fig.14 It is a structural schematic diagram of a transistor preparation process provided by another embodiment of the present application.

[0064] Description of reference numerals:

[0065] 10. transistor; 20. drive circuit; 21. switch transistor; 22. gate drive transistor; 23. pixel circuit; 30. test component;

[0066] 100. Buffer layer;

[0067] 200, active layer; 210, semiconductor portion; 211, channel region; 211a, sublayer; 212, non-channel region; 212a, source region; 212b, drain region; 213, first end; 214, second end;

[0068] 300, a first insulating layer;

[0069] 400, a first conductive layer; 410, a first gate;

[0070] 510, source; 520, drain;

[0071] 600, second insulating layer;

[0072] 700, a second conductive layer; 710, a second gate;

[0073] 800. A third insulating layer. DETAILED DESCRIPTION

[0074] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0075] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0076] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0077] The display panel includes a light-emitting unit and a driving circuit for driving the light-emitting unit to emit light. The driving circuit includes a plurality of transistors, which control the direction of the current through the transistors, thereby controlling whether the light-emitting unit emits light or not. The characteristics of the transistor have a great influence on the performance of the display panel. Transistors include metal oxide transistors and low-temperature polysilicon transistors. Metal oxide transistors usually use metal oxides such as indium gallium zinc oxide (IGZO) as semiconductor materials. Such materials have high electron mobility, good transparency and stability. Low-temperature polysilicon transistors use polycrystalline silicon (poly-Si) as semiconductor material. Polycrystalline silicon has higher carrier mobility, but needs to be crystallized at a lower temperature to avoid damaging the underlying flexible substrate.

[0078] Although low-temperature polysilicon transistors have the advantage of high mobility, the preparation process of low-temperature polysilicon transistors is relatively complicated and the manufacturing cost is high. In order to replace low-temperature polysilicon transistors, metal oxide transistors are constantly pursuing higher mobility. However, the applicant found that high-mobility oxide transistors are prone to negative bias conduction problems. The main reason is that the increase in metal oxide mobility is accompanied by a significant increase in the carrier concentration in the channel region. Therefore, the conductor in the non-channel area 212 is difficult to control in a fixed area, which is easy to affect the carrier concentration in the channel area, causing the effective channel length to shrink, and the threshold voltage negative bias conduction problem occurs.

[0079] In order to solve the above technical problems, this application is proposed. In order to better understand this application, Figures 1 to 14 The transistor, display panel and transistor manufacturing method of the embodiments of the present application are described in detail.

[0080] Please also read Figure 1 and Figure 2 , Figure 1 A top view of a transistor 10 provided in an embodiment of the present application. Figure 2 yes Figure 1 Cross-sectional view at AA in the middle.

[0081] like Figure 1 As shown, the transistor 10 provided in the present application is used for an array substrate of a display panel, and the transistor 10 includes: a buffer layer 100; an active layer 200, which is arranged on the buffer layer 100 and includes a semiconductor portion 210, the semiconductor portion 210 includes a channel region 211 and a non-channel region 212, and at least two non-channel regions 212 are arranged on both sides of the channel region 211; a first insulating layer 300, which is arranged on the side of the active layer 200 away from the buffer layer 100; a first conductive layer 400, which is arranged on the side of the first insulating layer 300 away from the active layer 200, and the first conductive layer 400 includes a first gate 410; wherein the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the first gate 410 on the buffer layer 100 at least partially overlap, and the resistance value of at least one non-channel region 212 is 500Ω~3000Ω.

[0082] In the transistor 10 provided in the embodiment of the present application, the transistor 10 includes a buffer layer 100, an active layer 200, a first insulating layer 300 and a first conductive layer 400. The buffer layer 100 provides a supporting buffering function for the device of the transistor 10. A semiconductor portion 210 is provided in the active layer 200, and the semiconductor portion 210 includes a channel region 211 and a non-channel region 212. The conduction of the channel region 211 realizes the conduction of carriers between the non-channel region 212. The first insulating layer 300 ensures the insulation performance between the first conductive layer 400 and the active layer 200. The first conductive layer 400 includes a first gate 410, and the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the first gate 410 on the buffer layer 100 at least partially overlap, so that the first gate 410 can control whether the channel region 211 is turned on or not. The resistance value of at least one non-channel region 212 is 500Ω~3000Ω. When the resistance value of the non-channel region 212 is within the above range, when the channel region 211 is turned on and the carriers in the non-channel region 212 move to the channel region 211, the carrier concentration in the channel region 211 can be effectively controlled, the device characteristics of the transistor 10 can be ensured, and the yield of the transistor 10 can be improved. Therefore, when the transistor 10 is used in a display panel, the performance of the display panel can be improved.

[0083] In addition, in an embodiment of the present application, when the transistor 10 is a metal oxide transistor 10, when the resistance value of at least one non-channel region 212 is 500Ω~3000Ω, the carrier concentration in the channel region 211 is within an appropriate range, thereby ensuring the effective channel length and improving the threshold voltage negative bias conduction problem.

[0084] Optionally, the resistance value of the at least one non-channel region 212 may be 500Ω, 800Ω, 960Ω, 1500Ω, 2100Ω, 3000Ω, etc.

[0085] Optionally, the active layer 200 includes two non-channel regions 212, and the two non-channel regions 212 are disposed on both sides of the channel region 211 in the first direction. Then, the first direction may be the length direction of the channel region 211. Optionally, one of the two non-channel regions 212 may be a source region 212a, and the other may be a drain region 212b.

[0086] Optionally, the orthographic projection of the channel region 211 on the buffer layer 100 overlaps with the orthographic projection of the first gate 410 on the buffer layer 100. For example, when the semiconductor portion 210 is conductively conductively formed using the first gate 410 as a mask, the portion covered by the first gate 410 is the channel region 211, and the portion not covered by the first gate 410 is conductively conductively formed as the non-channel region 212. At this time, the orthographic projections of the channel region 211 and the first gate 410 overlap.

[0087] In some optional embodiments, the resistance value of the at least one non-channel region 212 is 900Ω-2500Ω. For example, the resistance value of the at least one non-channel region 212 may be 900Ω, 850Ω, 980Ω, 1520Ω, 2150Ω, 2500Ω, etc.

[0088] In these optional embodiments, when the resistance value of the non-channel region 212 is further limited within the above range, it can improve the problem that the resistance value of the non-channel region 212 is too large and the carrier concentration in the channel region 211 is too low, which affects the mutual conduction between the non-channel regions 212; it can also improve the problem that the resistance value of the non-channel region 212 is too small and the carrier concentration in the channel region 211 is too high, which affects the effective channel length of the channel region 211 and causes the threshold voltage negative bias conduction problem.

[0089] In some optional embodiments, the length of the orthographic projection of the channel region 211 on the buffer layer 100 in the first direction is less than 4 micrometers, for example, the length of the orthographic projection of the channel region 211 on the buffer layer 100 in the first direction is 3.5 micrometers, 3.0 micrometers, 2.5 micrometers, 2.3 micrometers, 1.8 micrometers, etc. Please refer to the above, at least two non-channel regions 212 are disposed on both sides of the channel region 211 in the first direction.

[0090] In the embodiment of the present application, when the length of the orthographic projection of the channel region 211 on the buffer layer 100 in the first direction is within the above range, the length of the channel region 211 is relatively small. Since the resistance range of the non-channel region 212 is set within a suitable range in the embodiment of the present application, the carrier concentration in the channel region 211 is within a suitable range, and therefore, even if the channel length is relatively small, the effective channel length of the channel region 211 can be guaranteed, and the device performance can be guaranteed. In addition, a shorter channel length can improve mobility.

[0091] Optionally, the length of the orthographic projection of the channel region 211 on the buffer layer 100 in the first direction is less than 3 micrometers, for example, the length of the orthographic projection of the channel region 211 on the buffer layer 100 in the first direction is 2.8 micrometers, 2.6 micrometers, 2.5 micrometers, 2.3 micrometers, 1.8 micrometers, etc. The shorter the length of the channel region 211, the higher the mobility of the channel region 211.

[0092] Optionally, the orthographic projection of the semiconductor portion 210 on the buffer layer 100 is a first rectangle, and the first rectangle extends along the first direction. The orthographic projection of the channel region 211 on the buffer layer 100 is a second rectangle, and the orthographic projection of the non-channel region 212 on the buffer layer 100 is a third rectangle, and the second rectangle and two third rectangles located on both sides of the second rectangle in the first direction are combined to form the first rectangle. The distance between the two opposite sides of the second rectangle in the first direction can be the length of the above-mentioned channel region 211.

[0093] In some optional embodiments, the width of the channel region 211 projected on the buffer layer 100 in the second direction is greater than or equal to the length of the channel region 211 projected on the buffer layer 100 in the first direction. The second direction intersects the first direction, for example, the second direction is perpendicular to the first direction.

[0094] In these optional embodiments, the width of the channel region 211 is relatively large, so that the channel region 211 has a suitable distribution area, ensuring normal conduction of the source region 212 a and the drain region 212 b .

[0095] Optionally, the distance between two opposite sides of the second rectangle in the second direction is equal to the width of the channel region 211 .

[0096] In some optional embodiments, the two non-channel regions 212 include a source region 212a and a drain region 212b disposed on both sides of the channel region 211, and the resistance value of the source region 212a and / or the drain region 212b is 500Ω~3000Ω, so that the carrier concentration of the channel region 211 is within an appropriate range.

[0097] Optionally, the resistance values ​​of the source region 212 a and the drain region 212 b are both 500Ω to 3000Ω, so as to further improve the performance of the channel region 211 and enhance the uniformity of the transistor 10 device.

[0098] Optionally, the transistor 10 further includes a source 510 and a drain 520, wherein the source 510 is electrically connected to the source region 212a, and the drain region 212b is electrically connected to the drain 520. When the channel region 211 is turned on, the source 510 and the drain 520 can be mutually connected through the source region 212a, the channel region 211, and the drain region 212b, so that current flows between the source 510 and the drain 520.

[0099] Optionally, the transistor 10 further includes a second insulating layer 600, which is located on a side of the first conductive layer 400 away from the active layer 200, and the source 510 and the drain 520 are located on a side of the second insulating layer 600 away from the first conductive layer 400. The second insulating layer 600 is disposed between the source 510, the drain 520 and the first conductive layer 400 to improve the short circuit connection problem between the source 510, the drain 520 and the first gate 410.

[0100] In some optional embodiments, the carrier mobility of the channel region 211 is greater than 20 cm 2 / Vs. For example, the carrier mobility of the channel region 211 is 21cm 2 / Vs, 28cm 2 / Vs, 35cm 2 / Vs, 46cm 2 / Vs, 50cm 2 / Vs, etc.

[0101] In these optional embodiments, the carrier mobility of the channel region 211 is relatively high, which can improve the performance of the transistor 10 device, so that the transistor 10 has the advantages of fast response, reduced delay, lower power consumption, etc. In addition, in the embodiment of the present application, since the resistance value of the non-channel region 212 is within a suitable range, the carrier concentration in the channel region 211 is within a suitable range, even if the carrier mobility of the channel region 211 is relatively large, it is possible to ensure that the channel region 211 has a suitable effective length, thereby ensuring device performance.

[0102] Optionally, the carrier mobility of the channel region 211 is greater than 30 cm 2 / Vs. For example, the carrier mobility of the channel region 211 is 31cm 2 / Vs, 35cm 2 / Vs, 38cm 2 / Vs, 45cm 2 / Vs, 50cm 2 / Vs, etc. In these optional embodiments, the carrier mobility of the channel region 211 is higher, which can further improve the performance of the transistor 10 device, so that the transistor 10 has the advantages of fast response, reduced delay, lower power consumption, etc.

[0103] Preferably, the carrier mobility of the channel region 211 is less than 50 cm 2 For example, the carrier mobility of the channel region 211 is 31 cm2 / Vs, 35 cm2 / Vs, 38 cm2 / Vs, 45 cm2 / Vs, 49 cm 2 / Vs.

[0104] In these optional embodiments, the carrier mobility of the channel region 211 is within a suitable range to improve the effect of the effective length of the channel region 211 caused by excessive carrier mobility of the channel region 211 .

[0105] In some optional embodiments, such as Figure 1 and Figure 5 As shown, the transistor 10 further includes a second conductive layer 700 , which is located between the active layer 200 and the buffer layer 100 . The second conductive layer 700 includes a second gate 710 , and the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the second gate 710 on the buffer layer 100 at least partially overlap.

[0106] In these optional embodiments, a second gate 710 is provided in the second conductive layer 700 of the transistor 10, that is, gates are provided on both sides of the channel region 211 in the third direction. The transistor 10 is a dual-gate transistor 10, which can improve the control capability of the gate of the transistor 10 and achieve purposes such as fine adjustment.

[0107] Optionally, the orthographic projection of the channel region 211 on the buffer layer 100 is located within the orthographic projection of the second gate 710 on the buffer layer 100 , so as to improve the control capability of the second gate 710 over the channel region 211 .

[0108] In some optional embodiments, such as Figure 2 As shown, the channel region 211 is a single-layer structure, that is, the channel region 211 includes three film layers arranged in the third direction. Figure 3 and Figure 4 As shown, the channel region 211 includes a plurality of sub-layers 211a stacked in a direction away from the buffer layer 100. That is, the channel region 211 includes a plurality of sub-layers 211a stacked in a third direction, and the performance of the channel region 211 can be improved by controlling the materials of different sub-layers 211a.

[0109] Optional, such as Figure 3 As shown, the semiconductor portion 210 as a whole can be prepared in layers, and the non-channel region 212 can also include a plurality of sub-layers 211a. Figure 4 As shown, the non-channel region 212 is a single-layer structure, and the channel region 211 includes a plurality of sub-layers 211 a.

[0110] In some optional embodiments, the material of the buffer layer 100 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride, so that the buffer layer 100 has good insulation and buffer properties.

[0111] In some optional embodiments, the material of the semiconductor portion 210 includes at least one of indium gallium zinc oxide and low temperature polycrystalline oxide, that is, the transistor 10 may be a metal oxide transistor or a low temperature polycrystalline silicon transistor.

[0112] In some optional embodiments, the material of the semiconductor portion 210 includes at least one of indium, gallium, and zinc. That is, the semiconductor portion 210 can be a metal oxide transistor, so that the transistor 10 has the advantages of easy preparation. Indium, gallium, zinc and other metal materials have good mobility and low cost.

[0113] Optionally, the material of the semiconductor portion 210 may include indium. For example, the material of the semiconductor portion may include InO x , x is one of 1, 2, and 3. That is, the material of the semiconductor portion 210 may include monovalent indium, divalent indium, or ternary indium.

[0114] Optionally, the material of the semiconductor portion 210 may include indium and gallium. For example, the material of the semiconductor portion may include InGaO x , x is one of 1, 2, and 3. That is, the material of the semiconductor portion 210 may include monovalent indium, divalent indium, or ternary indium. Alternatively, the material of the semiconductor portion 210 may include monovalent gallium, divalent gallium, or ternary gallium.

[0115] Optionally, the material of the semiconductor portion 210 may include indium and zinc. For example, the material of the semiconductor portion may include InZnO. x , x is one of 1, 2, and 3. That is, the material of the semiconductor portion 210 may include monovalent indium, divalent indium, or ternary indium. Alternatively, the material of the semiconductor portion 210 may include monovalent zinc, divalent zinc, or ternary zinc.

[0116] Optionally, the material of the semiconductor portion 210 may include indium, gallium, and zinc. For example, the material of the semiconductor portion includes InGaZnO. x , x is one of 1, 2, and 3. That is, the material of the semiconductor portion 210 may include monovalent indium, divalent indium, or ternary indium. Alternatively, the material of the semiconductor portion 210 may include monovalent gallium, divalent gallium, or ternary gallium, or the material of the semiconductor portion 210 may include monovalent zinc, divalent zinc, or ternary zinc.

[0117] Optionally, in addition to indium, gallium and zinc, other trace elements may be doped into the semiconductor portion 210 .

[0118] In some optional embodiments, the orthographic projection of the channel region 211 on the substrate is located within the orthographic projection of the first gate 410 on the substrate, so that the first gate 410 can accurately control the channel region 211 .

[0119] like Figure 6 and Figure 7 As shown, the embodiment of the second aspect of the present application further provides an array substrate, the array substrate includes a substrate and a driving circuit 20 disposed on the substrate, and the driving circuit 20 includes the transistor 10 of any of the above-mentioned embodiments of the first aspect. Since the array substrate of the present application includes the above-mentioned transistor 10, the array substrate of this embodiment has the beneficial effects of the transistor 10 in any of the above-mentioned embodiments, which will not be repeated here.

[0120] Optionally, the array substrate is used for a display panel, and the array substrate is arranged on the non-display side of the display panel. Optionally, the array substrate may also include devices such as capacitors. The capacitor includes a first electrode plate and a second electrode plate that are arranged opposite to each other, and the first electrode plate may be arranged in the same layer as the first gate electrode 410, that is, the first electrode plate may be located in the first conductive layer 400. The second electrode plate may be arranged in the same layer as the source electrode 510 and the drain electrode 520. Alternatively, the array substrate further includes a third conductive layer, and the third conductive layer is located between the conductive layer where the source electrode 510 and the drain electrode 520 are located and the first conductive layer 400, and the second electrode plate is located in the third conductive layer.

[0121] like Figure 7As shown, the driving circuit 20 may include a pixel circuit 23 and a gate driving circuit 20, and the gate driving circuit 20 may include a gate driving transistor 22. The pixel circuit 23 may include a switching transistor 21 (S-TFT), a driving transistor 10 (D-TFT), and a capacitor (C), wherein the driving transistor 10 (D-TFT) is connected between a power signal line (VDD) and a light emitting element (EL), a gate of the switching transistor 21 (S-TFT) is connected to a scanning signal line (Scan), one of a source 510 and a drain 520 of the switching transistor 21 (S-TFT) is connected to a data signal line (Data), and the other of a source 510 and a drain 520 of the switching transistor 21 (S-TFT) is connected to the gate of the driving transistor 10 (D-TFT). When there are driving signals on both the scan signal line (Scan) and the data signal line (Data), the source 510 and the drain 520 of the switching transistor 21 (S-TFT) are turned on, the gate of the driving transistor 10 (D-TFT) controls the source 510 and the drain 520 of the driving transistor 10 (D-TFT) to be turned on, and the power signal line (VDD) and the light-emitting element (EL) are turned on to drive the light-emitting element (EL) to emit light.

[0122] In some optional embodiments, such as Figure 8 As shown, the array substrate further includes a test component 30 , the semiconductor portion 210 includes a first end 213 and a second end 214 opposite to each other in its extension direction, the test component 30 is connected between the first end 213 and the second end 214 , and is used to obtain the resistance of the semiconductor portion 210 .

[0123] In these optional embodiments, the array substrate further includes a testing component 30 connected between two ends of the semiconductor portion 210 , so that the testing component 30 can obtain the resistance of the semiconductor portion 210 , thereby facilitating determination of whether the resistance meets the device requirements.

[0124] Optionally, when the array substrate includes a plurality of transistors 10, the semiconductor portions 210 of the plurality of transistors 10 may be connected in series with each other, for example, the semiconductor portions 210 of the plurality of transistors 10 are connected in series into an integrated structure and have a first end 213 and a second end 214 that are arranged opposite to each other, and the test component 30 is connected between the first end 213 and the second end 214 after the series connection, so that the test component 30 can obtain the resistance of the plurality of semiconductor portions 210. Alternatively, the test component 30 may be connected to both ends of any semiconductor portion 210.

[0125] In some optional embodiments, the driving circuit 20 includes a switching transistor 21 and a gate driving transistor 22, and the switching transistor 21 and / or the gate driving transistor 22 is the transistor 10 of any of the above-mentioned first aspect embodiments.

[0126] In these optional embodiments, the switching transistor 21 and the gate driving transistor 22 have higher requirements on the devices. The switching transistor 21 and / or the gate driving transistor 22 are the transistor 10 of any of the above-mentioned first aspect embodiments, which can improve the yield and performance of the switching transistor 21 and / or the gate driving transistor 22, thereby improving the performance of the display panel.

[0127] Optionally, the driving circuit 20 also includes a driving transistor 10, a compensation transistor 10, a light-emitting control transistor 10, etc. The driving transistor 10, the compensation transistor 10, and the light-emitting control transistor 10 can also select the transistor 10 of any of the above-mentioned first aspect embodiments to improve the yield and performance of the array substrate.

[0128] The third aspect of the present application also provides a display panel, including the array substrate of any of the second aspect embodiments. Since the display panel of this embodiment includes the array substrate, the display panel of this embodiment has the beneficial effects of the array substrate, which will not be described in detail.

[0129] Optionally, the display panel further includes a planarization layer, a first electrode layer, a pixel definition layer, a second electrode layer and an encapsulation layer stacked in sequence on the array substrate. The first electrode layer includes a plurality of first electrodes distributed in an array, the pixel definition layer includes a pixel defining portion and a pixel opening, and a light-emitting unit is disposed in the pixel opening. Each first electrode is exposed by each pixel opening, and each first electrode cooperates with the second electrode layer to drive the light-emitting unit to emit light. The first electrode is electrically connected to the driving circuit 20, for example, the first electrode is electrically connected to the driving transistor 10.

[0130] The embodiment of the present application also provides a display device, including the display panel of any of the above embodiments. Since the display device provided by the embodiment of the present application includes the display panel of any of the above embodiments, the display device provided by the embodiment of the present application has the beneficial effects of the display panel of any of the above embodiments, which will not be described in detail here.

[0131] The display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0132] like Fig. 9 As shown, the fourth aspect of the present application also provides a method for preparing a transistor 10. The transistor 10 may be the transistor 10 provided by any of the first aspect embodiments described above. Please refer to Figures 1 to 5 , the preparation method of transistor 10 includes:

[0133] Step S01: Fig.10As shown, a semiconductor material layer is disposed on one side of the buffer layer 100 , and the semiconductor material layer is patterned to form an active layer 200 . The active layer 200 includes a semiconductor portion 210 . The semiconductor portion 210 includes a channel region 211 and non-channel regions 212 located on both sides of the channel region 211 .

[0134] Step S02: Fig.11 As shown, a first insulating layer 300 is disposed on a side of the active layer 200 facing away from the buffer layer 100 .

[0135] Step S03: Fig.12 As shown, a first conductive material layer is arranged on the side of the first insulating layer 300 away from the active layer 200, and the first conductive material layer is patterned to form a first conductive layer 400, the first conductive layer 400 includes a first gate 410, and the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the first gate 410 on the buffer layer 100 at least partially overlap.

[0136] The resistance value of at least one non-channel region 212 is 500Ω-3000Ω.

[0137] In the method for preparing the transistor 10 provided in the embodiment of the present application, firstly, an active layer 200 is prepared on the buffer layer 100 through step S01. The buffer layer 100 provides a supporting buffering function for the device of the transistor 10. A semiconductor portion 210 is provided in the active layer 200, and the semiconductor portion 210 includes a channel region 211 and a non-channel region 212. The conduction of carriers between the non-channel region 212 is realized by the conduction of the channel region 211. Then, a first insulating layer 300 is prepared on the active layer 200 through step S02, and a first conductive layer 400 is continuously prepared on the first insulating layer 300 through step S03. The first insulating layer 300 ensures the insulation performance between the first conductive layer 400 and the active layer 200. The first conductive layer 400 includes a first gate 410, and the orthographic projection of the channel region 211 on the buffer layer 100 and the orthographic projection of the first gate 410 on the buffer layer 100 at least partially overlap, so that the first gate 410 can control whether the channel region 211 is turned on or not. The resistance value of at least one non-channel region 212 is 500Ω~3000Ω. When the resistance value of the non-channel region 212 is within the above range, when the channel region 211 is turned on and the carriers in the non-channel region 212 move to the channel region 211, the carrier concentration in the channel region 211 can be effectively controlled, the device characteristics of the transistor 10 can be ensured, and the yield of the transistor 10 can be improved. Therefore, when the transistor 10 is used in a display panel, the performance of the display panel can be improved.

[0138] In some optional embodiments, such as Fig.13 As shown, the method for preparing the transistor 10 further includes:

[0139] Step S04 : performing ion implantation into the semiconductor portion 210 from a side of the first conductive layer 400 facing away from the first insulating layer 300 .

[0140] In the embodiment of the present application, ion implantation is performed on the semiconductor portion 210 through step S04. Due to the presence of the first gate 410 in the first conductive layer 400, the first gate 410 blocks the channel region 211, and ions can be implanted into the non-channel region 212 to achieve conductivity of the non-channel region 212.

[0141] Optionally, the energy of the ion implantation is 5KV to 75KV. When the energy of the ion implantation is within the above range, the non-channel region 212 has a suitable resistance range, so that the resistance value of the non-channel region 212 is controlled between 500Ω and 3000Ω.

[0142] Optionally, the ion implantation dose is 1*10 11 cm 3 ~1*10 15 cm 3 When the ion implantation dose is within the above range, it can improve the problem that the implantation dose is too small, resulting in excessive resistance of the non-channel region 212 , or that the implantation dose is too large, resulting in excessive resistance of the non-channel region 212 , thereby affecting device performance.

[0143] In some optional embodiments, step S04 may further include:

[0144] Step S05 : performing annealing treatment on the semiconductor portion 210 , wherein the annealing temperature is 200° C. to 400° C., and / or the annealing time is 10 minutes to 2 hours.

[0145] In the above embodiment, after ion implantation is performed on the semiconductor portion 210 , the semiconductor portion 210 is annealed. When the annealing temperature and / or the annealing time is within the above range, the resistance of the non-channel region 212 can be controlled to be between 500Ω and 3000Ω.

[0146] Optionally, in step S05 , the annealing temperature is 200° C. to 400° C., and the annealing time is 10 minutes to 2 hours, so as to further ensure that the resistance of the non-channel region 212 is between 500Ω and 3000Ω.

[0147] In some optional embodiments, in step S02 : a chemical vapor deposition process is selected to form the first insulating layer 300 .

[0148] Optionally, the material of the first insulating layer 300 includes silicon oxide, the chemical vapor deposition gas precursor includes silane gas and nitrous oxide, and the ratio of the silane gas to the nitrous oxide gas is 0.1-0.01.

[0149] Optionally, the working pressure of chemical vapor deposition is 100Pa to 300Pa.

[0150] Optionally, the operating power of the chemical vapor deposition is 0.5 kW to 10 kW.

[0151] In these optional embodiments, the first insulating layer 300 is prepared by chemical vapor deposition, which can improve the compactness of the first insulating layer 300 and improve the insulating performance of the first insulating layer 300. In the chemical vapor deposition process, by adjusting the precursor, working pressure and working power of the chemical vapor deposition, the performance of the non-channel area 212 can be affected, so that when the non-channel area 212 is subsequently conductorized, the resistance value of the non-channel area 212 can be maintained at 500Ω to 3000Ω.

[0152] In some optional embodiments, the method for preparing the transistor 10 further includes:

[0153] Step S06: Fig.14 As shown, the second insulating layer 600 is disposed on a side of the first conductive layer 400 facing away from the first insulating layer 300 .

[0154] Optionally, the second insulating layer 600 is formed by a chemical vapor deposition process.

[0155] Optionally, the material of the second insulating layer 600 includes silicon oxide, the gas precursor of chemical vapor deposition includes silane gas and nitrous oxide, and the ratio of the silane gas to the nitrous oxide gas is 0.1-0.01.

[0156] Optionally, the working pressure of chemical vapor deposition is 100Pa to 300Pa.

[0157] Optionally, the operating power of the chemical vapor deposition is 0.5 kW to 10 kW.

[0158] In these optional embodiments, firstly setting the second insulating layer 600 can improve the short circuit connection between the first conductive layer 400 and other conductive layers. The second insulating layer 600 is prepared by chemical vapor deposition, which can improve the compactness of the second insulating layer 600 and improve the insulation performance of the second insulating layer 600. In the chemical vapor deposition process, by adjusting the precursor, working pressure and working power of the chemical vapor deposition, the performance of the non-channel area 212 can be affected, so that when the non-channel area 212 is subsequently conductorized, the resistance value of the non-channel area 212 can be maintained at 500Ω to 3000Ω.

[0159] Optionally, after step S06 , the above-mentioned source electrode 510 and drain electrode 520 may be prepared on the second insulating layer 600 .

[0160] Optionally, before step S01, a second conductive layer 700 may be formed on the buffer layer 100, the second conductive layer 700 including the second gate 710. A third insulating layer 800 may be formed on the second conductive layer 700. In step S01, an active layer 200 may be formed on the third insulating layer 800.

[0161] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A transistor for an array substrate of a display panel, characterized in that: include: Buffer layer; An active layer, disposed on the buffer layer and comprising a semiconductor portion, wherein the semiconductor portion comprises a channel region and a non-channel region, and at least two non-channel regions are disposed on both sides of the channel region; A first insulating layer, disposed on a side of the active layer away from the buffer layer; A first conductive layer, disposed on a side of the first insulating layer away from the active layer, the first conductive layer comprising a first gate; The orthographic projection of the channel region on the buffer layer and the orthographic projection of the first gate on the buffer layer at least partially overlap, and the resistance value of at least one of the non-channel regions is 500Ω to 3000Ω.

2. The transistor according to claim 1, characterized in that The resistance value of at least one of the non-channel regions is 900Ω to 2500Ω.

3. The transistor according to claim 1, characterized in that The length of the orthographic projection of the channel region on the buffer layer in the first direction is less than 4 micrometers, and at least two non-channel regions are arranged on both sides of the channel region in the first direction; Preferably, the length of the channel region in the first direction of the positive projection of the buffer layer is less than 3 microns; Preferably, an extension width of the channel region in the second direction of the orthogonal projection of the buffer layer is greater than or equal to an extension length of the orthogonal projection of the channel region in the buffer layer in the first direction, and the second direction intersects with the first direction.

4. The transistor according to claim 1, characterized in that The two non-channel regions include a source region and a drain region respectively disposed on both sides of the channel region, and the resistance value of the source region and / or the drain region is 500Ω to 3000Ω; Preferably, it further comprises a source electrode and a drain electrode, the source electrode is electrically connected to the source region, and the drain electrode is electrically connected to the drain region; Preferably, the method further comprises a second insulating layer located on a side of the first conductive layer away from the active layer, and the source electrode and the drain electrode are located on a side of the second insulating layer away from the first conductive layer.

5. The transistor according to claim 1, characterized in that The carrier mobility of the channel region is greater than 20 cm 2 / Vs; Preferably, the carrier mobility in the channel region is greater than 30 cm 2 / Vs; Preferably, the carrier mobility in the channel region is less than 50 cm 2 / Vs.

6. The transistor according to claim 1, characterized in that Also includes a second conductive layer, the second conductive layer is located between the active layer and the buffer layer, the second conductive layer includes a second gate, and the orthographic projection of the channel region on the buffer layer and the orthographic projection of the second gate on the buffer layer at least partially overlap; Preferably, an orthographic projection of the channel region on the buffer layer is located within an orthographic projection of the second gate on the buffer layer.

7. The transistor according to claim 1, characterized in that The channel region is a single-layer structure, or the channel region includes a plurality of sub-layers stacked in a direction away from the buffer layer.

8. The transistor according to claim 1, characterized in that The material of the buffer layer includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.

9. The transistor according to claim 1, characterized in that The material of the semiconductor portion includes at least one of indium, gallium, and zinc; Preferably, the material of the semiconductor portion includes InO x , x is one of 1, 2, and 3; Preferably, the material of the semiconductor portion includes InGaO x , x is one of 1, 2, and 3; Preferably, the material of the semiconductor portion includes InZnO x , x is one of 1, 2, and 3; Preferably, the material of the semiconductor portion includes InGaZnO x , x is one of 1, 2, and 3.

10. The transistor according to claim 1, characterized in that The orthographic projection of the channel region on the substrate is located within the orthographic projection of the first gate on the substrate.

11. An array substrate, characterized in that: It comprises a substrate and a driving circuit arranged on the substrate, wherein the driving circuit comprises the transistor according to any one of claims 1 to 10.

12. The array substrate according to claim 11, characterized in that: A test component is also included. The semiconductor portion includes a first end and a second end opposite to each other in an extending direction thereof. The test component is connected between the first end and the second end. The test component is used to obtain the resistance of the semiconductor portion.

13. The array substrate according to claim 11, characterized in that: The driving circuit comprises a switching transistor and a gate driving transistor, and the switching transistor and / or the gate driving transistor is the transistor according to any one of claims 1-10.

14. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 11 to 13.

15. A method for preparing a transistor, characterized in that: include: A semiconductor material layer is disposed on one side of the buffer layer, and the semiconductor material layer is patterned to form an active layer, wherein the active layer includes a semiconductor portion, and the semiconductor portion includes a channel region and non-channel regions located on both sides of the channel region; Disposing a first insulating layer on a side of the active layer away from the buffer layer; A first conductive material layer is disposed on a side of the first insulating layer away from the active layer, and the first conductive material layer is patterned to form a first conductive layer, wherein the first conductive layer includes a first gate, and an orthographic projection of the channel region on the buffer layer and an orthographic projection of the first gate on the buffer layer at least partially overlap; Wherein, the resistance value of at least one of the non-channel regions is 500Ω to 3000Ω.

16. The method according to claim 15, characterized in that Also includes: Performing ion implantation into the semiconductor portion from a side of the first conductive layer facing away from the first insulating layer; Preferably, the energy of ion implantation is 5KV to 75KV; Preferably, the ion implantation dose is 1*10 11 cm 3 ~1*10 15 cm 3 .

17. The method according to claim 16, characterized in that After the step of implanting ions into the semiconductor portion from a side of the first conductive layer away from the first insulating layer, the step further includes: The semiconductor portion is subjected to annealing treatment, the annealing temperature is 200° C. to 400° C., and / or the annealing time is 10 minutes to 2 hours.

18. The method according to claim 15, characterized in that In the step of providing a first insulating layer on a side of the active layer away from the buffer layer: Forming the first insulating layer by a chemical vapor deposition process; Preferably, the material of the first insulating layer includes silicon oxide, the chemical vapor deposition gas precursor includes silane gas and nitrous oxide, and the ratio of silane gas to nitrous oxide gas is 0.1 to 0.01; Preferably, the working pressure of chemical vapor deposition is 100Pa to 300Pa; Preferably, the operating power of the chemical vapor deposition is 0.5 kW to 10 kW.

19. The method according to claim 15, characterized in that Also includes: Disposing a second insulating layer on a side of the first conductive layer away from the first insulating layer; Preferably, the second insulating layer is formed by a chemical vapor deposition process; Preferably, the material of the second insulating layer includes silicon oxide, the gas precursor of chemical vapor deposition includes silane gas and nitrous oxide, and the ratio of silane gas to nitrous oxide gas is 0.1 to 0.01; Preferably, the working pressure of chemical vapor deposition is 100Pa to 300Pa; Preferably, the operating power of the chemical vapor deposition is 0.5 kW to 10 kW.

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