Tin oxide thin film transistor and preparation method thereof

Abstract

The invention belongs to the technical field of thin film transistors, and particularly discloses a tin oxide thin film transistor and a preparation method thereof.The tin oxide thin film transistor comprises a substrate comprising a gate electrode, a gate dielectric layer is arranged on the substrate, and a tin oxide channel layer is arranged on the upper surface of the gate dielectric layer; a tellurium layer is arranged on one side of the upper surface of the tin oxide channel layer, a source electrode is arranged on the other side of the upper surface of the tin oxide channel layer, and a gap exists between the tellurium layer and the source electrode; and a drain electrode is arranged on the upper surface of the tellurium layer. The work function matching effect of Te is utilized, the forward offset of the threshold voltage can be regulated and controlled, and Te is a carrier capture layer, so that the off-state current value is reduced, and the power consumption of the device is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of thin film transistors, and in particular to a tin oxide thin film transistor and a preparation method thereof. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] As new display technologies are rapidly developing towards high resolution, low power consumption and flexibility, the performance of thin-film transistors (TFTs), as the core components of the driving backplane, directly determines the response speed, energy efficiency and device life of the display panel.

[0004] At present, mainstream indium-based oxide semiconductors (such as IGZO) have the advantage of high mobility, but their dependence on the raw material bottleneck of rare metal indium (the abundance in the earth's crust is only 0.05 ppm) leads to high costs and supply chain risks, which restricts the sustainable development of the display industry. In this context, tin-based oxide semiconductors have become an important direction for replacing indium-based materials due to their rich resources (the abundance of tin in the earth's crust is 2.2 ppm), excellent environmental compatibility and unique electrical properties.

[0005] Tin oxide (SnO2) has a wide bandgap (3.6–4.3 eV) and high visible light transmittance (>85%), which is suitable for transparent displays and flexible devices, such as foldable screens and electronic paper, and promotes the development of consumer electronics towards lightweight and energy-saving. At the same time, the low-energy consumption preparation process of SnO2 thin-film transistors (TFTs) (such as solution method and low-temperature sputtering) can reduce carbon emissions in the production process, which is in line with the trend of green manufacturing.

[0006] Although tin-based oxide semiconductors have shown great potential in replacing traditional indium-based materials, their industrialization process still faces the following technical problems: n-type SnO2 thin film transistors (TFTs) have high density interface defects (oxygen vacancy concentration > 1×10 19 cm -3 , grain boundary defect density>5×10 11 cm -2 ) can easily cause the threshold voltage to drift negatively (Vth<0 V), causing a surge in device power consumption.

[0007] The current improvement methods are: (1) O2 plasma pretreatment of the SnO2 channel layer was used to optimize the dielectric layer / channel interface, effectively reducing oxygen vacancy defects and achieving a positive shift in the threshold voltage. However, the field effect mobility of the device decreased after pretreatment, and an ultra-thin SnO2 channel was used in the experiment to achieve complete depletion. If the channel thickness increases, the pretreatment effect will be weakened.

[0008] (2) Indium (In) and gallium (Ga) are co-doped into SnO2 by the sol-gel method, and the difference in ionic radius between the two is used to balance the lattice strain, inhibit the generation of oxygen vacancies, and adjust the band structure so that the threshold voltage is shifted positively. However, the device mobility decreases after doping. At the same time, the sol-gel method requires multiple steps of synthesis and annealing, and the high process complexity increases energy consumption and time costs. Summary of the invention

[0009] In order to solve the above problems, the present invention proposes a tin oxide thin film transistor and a preparation method, which adopts a tellurium layer and a SnO2 layer to form a heterojunction, and utilizes the work function matching effect of tellurium (Te) to regulate the positive shift of the threshold voltage. At the same time, tellurium serves as a carrier capture layer, which reduces the off-state current value and greatly reduces the power consumption of the device.

[0010] In some embodiments, the following technical solutions are adopted: A tin oxide thin film transistor comprises: a substrate including a gate electrode, a gate dielectric layer is provided on the substrate, a tin oxide channel layer is provided on the upper surface of the gate dielectric layer, a tellurium layer is provided on one side of the upper surface of the tin oxide channel layer, a source electrode is provided on the other side of the upper surface of the tin oxide channel layer, and there is a gap between the tellurium layer and the source electrode; a drain electrode is provided on the upper surface of the tellurium layer.

[0011] Under this scheme, the tellurium layer and the tin oxide channel layer form a single heterojunction, which can utilize the work function matching effect of Te and tin oxide to regulate the positive shift of the threshold voltage; at the same time, when the SnO2TFT is in the off state, there will be a small amount of on-state current, that is, a small amount of electrons are captured by the Te layer, which significantly reduces the off-state current and reduces the power consumption of the device.

[0012] As a further implementation, the tellurium layer uses a tellurium film with a thickness of 5-20nm. The thickness of the tellurium layer is related to the ability to regulate the threshold voltage. The greater the thickness, the stronger the regulation ability. However, too thick a thickness will cause a significant decrease in the on-state current of the TFT. Therefore, a tellurium film with a thickness of 5-20nm is used. The tellurium film within this thickness range can both ensure the ability to regulate the threshold voltage and not cause a significant decrease in the on-state current of the TFT.

[0013] In other embodiments, the following technical solutions are adopted: A tin oxide thin film transistor comprises: a substrate including a gate electrode, a gate dielectric layer is provided on the substrate, a tin oxide channel layer is provided on the upper surface of the gate dielectric layer, tellurium layers are provided on both sides of the upper surface of the tin oxide channel layer, and there is a gap between the tellurium layers on both sides; a drain electrode is provided on the upper surface of one side of the tellurium layer, and a source electrode is provided on the upper surface of the other side of the tellurium layer.

[0014] As a further embodiment, the tellurium layer is a tellurium thin film with a thickness of 10 nm.

[0015] In this scheme, the tellurium layer and the tin oxide channel layer form a double heterojunction, which can also utilize the work function matching effect of Te and tin oxide to regulate the positive shift of the threshold voltage; however, compared with a single heterojunction, the on-state current and switching ratio of the device will be reduced in this structure.

[0016] In other embodiments, the following technical solutions are adopted: A method for preparing the tin oxide thin film transistor as described above comprises: preparing a bottom gate dielectric layer on a substrate; Depositing a tin oxide film on a substrate including a bottom gate dielectric layer to form an amorphous tin oxide channel layer; Performing air annealing to form a crystalline tin oxide channel layer; A tellurium thin film is prepared on one side of the upper surface of the crystalline tin oxide channel layer by thermal evaporation to form a tellurium layer; Nickel is thermally evaporated on the other side of the upper surface of the crystalline tin oxide channel layer and the upper surface of the tellurium layer as a source electrode and a drain electrode, respectively.

[0017] As a further embodiment, the tellurium layer has a thickness of 5-20 nm.

[0018] In other embodiments, the following technical solutions are adopted: A method for preparing the tin oxide thin film transistor as described above comprises: preparing a bottom gate dielectric layer on a substrate; Depositing a tin oxide film on a substrate including a bottom gate dielectric layer to form an amorphous tin oxide channel layer; Performing air annealing to form a crystalline tin oxide channel layer; Using thermal evaporation to prepare tellurium thin films on both sides of the upper surface of the crystalline tin oxide channel layer to form tellurium layers; and there is a gap between the tellurium layers on the two sides; Nickel is thermally evaporated on the upper surface of the tellurium layer on both sides of the crystalline tin oxide channel layer as a source electrode and a drain electrode.

[0019] As a further embodiment, the tellurium layer has a thickness of 10 nm.

[0020] Compared with the prior art, the present invention has the following beneficial effects: (1) Threshold voltage of SnO2 (V TH ) is usually a negative value. The present invention adopts a Te layer and a SnO2 layer to form a heterojunction, and utilizes the work function matching effect of Te to adjust the positive shift of the threshold voltage.

[0021] (2) To address the problem of large off-state current of SnO2, the present invention utilizes the Te layer as a carrier capture layer, thereby reducing the off-state current value and greatly reducing the power consumption of the device.

[0022] (3) Compared with the double heterojunction, the single heterojunction has a weaker effect on suppressing the on-state current of the SnO2 TFT, so the switching ratio is larger and the electrical performance is better.

[0023] Other features and advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the structure of a tin oxide thin film transistor without a tellurium layer; Figure 2 A schematic diagram of the structure of a single heterojunction tin oxide thin film transistor with a tellurium layer in an embodiment of the present invention; Figure 3 The figure is a comparison of the current transfer curves of single heterojunction tin oxide thin film transistors with different tellurium layer thicknesses and tin oxide thin film transistors without a tellurium layer; Figure 4 This is a schematic diagram of the structure of a double heterojunction tin oxide thin film transistor with a tellurium layer in Embodiment 5 of the present invention; Figure 5 Comparison of current transfer curves of tin oxide thin film transistors without tellurium layer, single heterojunction and double heterojunction. DETAILED DESCRIPTION

[0025] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used in the present invention have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0026] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0027] Embodiment 1 In one or more embodiments, a tin oxide thin film transistor is disclosed, in combination with Figure 2 , specifically including: a substrate including a gate electrode, wherein the gate electrode is a bottom gate electrode, and the bottom gate electrode is located at the bottom of the substrate; the bottom gate electrode is heavily doped P-type silicon.

[0028] A gate dielectric layer is arranged on the substrate, and the material of the gate dielectric layer is silicon oxide; the thickness of the gate dielectric layer is 100 nm.

[0029] A tin oxide channel layer is arranged on the upper surface of the gate dielectric layer. The tin oxide channel layer is an n-type tin oxide film. The thickness of the tin oxide film is 30 nm. A tellurium (Te) layer is provided on one side of the upper surface of the tin oxide channel layer. In this embodiment, the thickness of the tellurium film is 5 nm.

[0030] A source electrode is provided on the other side of the upper surface of the tin oxide channel layer, and there is a gap between the tellurium layer and the source electrode; the specific gap may be the channel width: 200 microns; a drain electrode is provided on the upper surface of the tellurium layer.

[0031] In this embodiment, the source electrode and the drain electrode are both made of nickel (Ni) metal, and the thickness of the nickel metal is 100 nm.

[0032] The method for preparing the tin oxide thin film transistor in this embodiment specifically includes the following steps: (a) Substrate cleaning: Use a cleaning solution to clean the surface of the substrate; Specifically, the cleaning steps of the substrate are as follows: put the substrate into anhydrous ethanol and perform ultrasonic cleaning for 5 minutes to remove organic pollutants and grease on the surface of the substrate; then take the substrate out of the anhydrous ethanol, put it into deionized water, and perform ultrasonic cleaning for 5 minutes to remove residual anhydrous ethanol and inorganic pollutants. Finally, blow dry the surface of the substrate with high-purity nitrogen (N2) to ensure that there is no liquid residue on the surface.

[0033] Use atomic layer deposition (ALD), chemical vapor deposition (CVD) or sputtering to deposit a gate dielectric layer (SiO2) on the substrate, control the thickness of the gate dielectric layer to 100nm, and ensure that the gate dielectric layer is uniform and defect-free.

[0034] (b) Preparation of tin oxide thin film: On the substrate obtained in step (a), an amorphous tin oxide channel layer is deposited on the substrate by pulse magnetron sputtering of amorphous tin oxide, and the thickness of the amorphous tin oxide channel layer is controlled to be 30 nm.

[0035] In this embodiment, the magnetron sputtering process parameters for preparing the tin oxide film are as follows: argon gas is introduced at 30 sscm, oxygen is introduced at 6 sscm, the working gas pressure is set to 1.0 Pa, pulse power supply magnetron sputtering, the sputtering power is 30 W, the sputtering time is 300 s, and the thickness is 30 nm.

[0036] (c) Annealing treatment: The sample obtained in (b) is air annealed to generate crystalline tin oxide. The specific implementation method is: use a tube furnace or a box furnace, ensure that the temperature in the furnace is uniform, set the annealing temperature and time: the annealing temperature in this embodiment is 230°C, and the annealing time is 120 minutes; put the sample obtained in (b) into the furnace, and ensure air circulation (the furnace is air atmosphere). Heat to the target temperature at an appropriate heating rate (such as 8°C / min), maintain a constant temperature at the target temperature, so that the amorphous tin oxide is fully crystallized (for example: anneal at a constant temperature of 230°C for 120 minutes); after the annealing is completed, cool to room temperature at an appropriate cooling rate (such as natural cooling or controlled cooling).

[0037] (d) Preparation of tellurium layer: A tellurium thin film is prepared on one side of the tin oxide channel layer by thermal evaporation to form a tellurium layer; a metal mask is used to align the metal mask with the upper surface of the tin oxide, and the sample and the mask are placed in a thermal evaporation device and vacuumed to ≤10 -6 Torr; heat high-purity tellurium particles (purity 99.9%) to evaporate and deposit in the mask opening area to form a tellurium layer. The thermal evaporation parameters for preparing tellurium thin films are: deposition rate 0.9nm / s, deposition thickness 5nm, and substrate temperature 20℃.

[0038] (e) Preparation of source and drain electrodes: Use a metal mask to align the metal mask with the other side of the upper surface of the tin oxide channel layer and the upper surface of the tellurium layer, respectively. Place the sample and the mask in a thermal evaporation device and evacuate the vacuum to ≤10 - 6 Torr; heat the nickel source to evaporate and deposit nickel in the opening area of ​​the mask with a deposition thickness of 100 nm to form a source electrode and a drain electrode.

[0039] The final result is a tin oxide thin film transistor with a tellurium layer.

[0040] Embodiment 2 This embodiment discloses a tin oxide thin film transistor, which specifically includes: a substrate including a gate electrode, wherein the gate electrode is a bottom gate electrode, and the bottom gate electrode is located at the bottom of the substrate; the bottom gate electrode is heavily doped P-type silicon.

[0041] A gate dielectric layer is arranged on the substrate, and the material of the gate dielectric layer is silicon oxide; the thickness of the gate dielectric layer is 100 nm.

[0042] A tin oxide channel layer is disposed on the upper surface of the gate dielectric layer. The tin oxide channel layer is an n-type tin oxide film. In this embodiment, the thickness of the tin oxide film is 30 nm. A tellurium (Te) layer is provided on one side of the upper surface of the tin oxide channel layer. In this embodiment, the thickness of the tellurium film is 10 nm.

[0043] A source electrode is provided on the other side of the upper surface of the tin oxide channel layer, and there is a gap between the tellurium layer and the source electrode; the specific gap may be the channel width: 200 microns; a drain electrode is provided on the upper surface of the tellurium layer.

[0044] The source electrode and the drain electrode of this embodiment are both made of nickel (Ni) metal. In this embodiment, the thickness of the nickel metal is selected to be 100 nm.

[0045] The specific preparation method of the tin oxide thin film transistor in this embodiment is the same as that in the first embodiment, except that the deposition thickness of the tellurium thin film is 10 nm.

[0046] Embodiment 3 This embodiment discloses a tin oxide thin film transistor, which specifically includes: a substrate including a gate electrode, wherein the gate electrode is a bottom gate electrode, and the bottom gate electrode is located at the bottom of the substrate; the bottom gate electrode is heavily doped P-type silicon.

[0047] A gate dielectric layer is arranged on the substrate. The material of the gate dielectric layer is silicon oxide and the thickness of the gate dielectric layer is 100 nm.

[0048] A tin oxide channel layer is disposed on the upper surface of the gate dielectric layer. The tin oxide channel layer is an n-type tin oxide film. In this embodiment, the thickness of the tin oxide film is 30 nm. A tellurium (Te) layer is provided on one side of the upper surface of the tin oxide channel layer. The thickness of the tellurium layer is related to the ability to control the threshold voltage. The greater the thickness, the stronger the control ability. However, too thick a thickness will cause a significant decrease in the on-state current of the TFT. In this embodiment, the thickness of the tellurium film is 15nm.

[0049] A source electrode is provided on the other side of the upper surface of the tin oxide channel layer, and there is a gap between the tellurium layer and the source electrode; the specific gap may be the channel width: 200 microns; a drain electrode is provided on the upper surface of the tellurium layer.

[0050] The source electrode and the drain electrode of this embodiment are both made of nickel (Ni) metal. In this embodiment, the thickness of the nickel metal is selected to be 100 nm.

[0051] The specific preparation method of the tin oxide thin film transistor in this embodiment is the same as that in the first embodiment, except that the deposition thickness of the tellurium thin film is 15 nm.

[0052] Embodiment 4 This embodiment discloses a tin oxide thin film transistor, which specifically includes: a substrate including a gate electrode, wherein the gate electrode is a bottom gate electrode, and the bottom gate electrode is located at the bottom of the substrate; the bottom gate electrode is heavily doped P-type silicon.

[0053] A gate dielectric layer is arranged on the substrate. The material of the gate dielectric layer is silicon oxide and the thickness of the gate dielectric layer is 100 nm.

[0054] A tin oxide channel layer is disposed on the upper surface of the gate dielectric layer. The tin oxide channel layer is an n-type tin oxide film. In this embodiment, the thickness of the tin oxide film is 30 nm. A tellurium (Te) layer is provided on one side of the upper surface of the tin oxide channel layer. The thickness of the tellurium layer is related to the ability to control the threshold voltage. The greater the thickness, the stronger the control ability. However, too thick a thickness will cause a significant decrease in the on-state current of the TFT. In this embodiment, the thickness of the tellurium film is 20nm.

[0055] A source electrode is provided on the other side of the upper surface of the tin oxide channel layer, and there is a gap between the tellurium layer and the source electrode; the specific gap may be the channel width: 200 microns; a drain electrode is provided on the upper surface of the tellurium layer.

[0056] The source electrode and the drain electrode of this embodiment are both made of nickel (Ni) metal. In this embodiment, the thickness of the nickel metal is selected to be 100 nm.

[0057] The specific preparation method of the tin oxide thin film transistor in this embodiment is the same as that in the first embodiment, except that the deposition thickness of the tellurium thin film is 20 nm.

[0058] In the above-mentioned embodiments 1 to 4, a tellurium layer is provided on one side of the upper surface of the tin oxide channel layer, and the Te layer forms a single heterojunction with the SnO2 layer. When SnO2 (work function of about 4.4-4.6 eV) contacts Te (work function of about 4.8-5.0 eV), electrons flow from SnO2 to Te, resulting in the formation of a hole accumulation layer on the SnO2 side and an electron accumulation layer on the Te side at the interface. The hole accumulation on the SnO2 surface is equivalent to p-type doping enhancement, and a higher gate voltage is required to form an inversion layer (n-type conductive channel), resulting in a positive shift of Vth.

[0059] In addition, Te is a p-type semiconductor, and the main carriers inside the semiconductor are holes. SnO2 is an n-type semiconductor, and the main carriers inside it are electrons. Therefore, when the SnO2TFT is in the off state, there will be a small amount of on-current, that is, a small amount of electrons flow into the Te layer. The electrons flowing into the Te layer recombine and annihilate with the holes in the Te layer, which significantly reduces the off-state current.

[0060] Embodiment 5 In one or more embodiments, a tin oxide thin film transistor is disclosed, in combination with Figure 4 , specifically including: a substrate including a gate electrode, wherein the gate electrode is a bottom gate electrode, and the bottom gate electrode is located at the bottom of the substrate; the bottom gate electrode is heavily doped P-type silicon.

[0061] A gate dielectric layer is arranged on the substrate. The material of the gate dielectric layer is silicon oxide and the thickness of the gate dielectric layer is 100 nm.

[0062] A tin oxide channel layer is disposed on the upper surface of the gate dielectric layer. The tin oxide channel layer is an n-type tin oxide film. In this embodiment, the thickness of the tin oxide film is 30 nm. Tellurium (Te) layers are provided on both sides of the upper surface of the tin oxide channel layer, and the thickness range of the tellurium layer is the same as that in the first embodiment; in this embodiment, the thickness of the tellurium layer is selected to be 10 nm.

[0063] There is a gap between the two tellurium layers, and the specific gap can be the channel width: 200 microns; nickel is thermally evaporated on the upper surfaces of the tellurium layers on both sides of the crystalline tin oxide channel layer as a source electrode and a drain electrode.

[0064] The source electrode and the drain electrode of this embodiment are both made of nickel (Ni) metal. In this embodiment, the thickness of the nickel metal is selected to be 100 nm.

[0065] The method for preparing the tin oxide thin film transistor in this embodiment specifically includes the following steps: (a) Substrate cleaning; (b) Preparation of tin oxide thin film; (c) annealing treatment; The specific implementation methods of the above (a), (b), and (c) are consistent with those in the first embodiment and will not be described in detail.

[0066] (d) Preparation of a tellurium layer: A tellurium thin film is prepared by thermal evaporation on both sides of the upper surface of the crystalline tin oxide channel layer to form a tellurium layer; and there is a gap between the tellurium layers on both sides.

[0067] Specifically, a metal mask is used, and the metal mask is aligned with the two sides of the upper surface of the tin oxide, and the sample and the mask are placed in a thermal evaporation device, and the vacuum is evacuated to ≤10 -6 Torr; high-purity tellurium particles (purity 99.9%) are heated to evaporate the tellurium and deposit it in the opening area of ​​the mask to form a tellurium layer; the thermal evaporation parameters for preparing the tellurium film are: deposition rate of 0.9nm / s, deposition thickness of 10nm, and substrate temperature of 20°C.

[0068] (e) Preparation of source electrode and drain electrode: Nickel is thermally evaporated on the upper surface of the tellurium layer on both sides of the crystalline tin oxide channel layer as the source electrode and drain electrode, respectively.

[0069] Use a metal mask to align the metal mask with the upper surface of the tellurium layer on both sides of the crystallized tin oxide channel layer; place the sample and the mask in a thermal evaporation device and evacuate the vacuum to ≤10 -6 Torr; heat the nickel source to evaporate and deposit nickel in the opening area of ​​the mask with a deposition thickness of 100 nm to form a source electrode and a drain electrode.

[0070] The final result is a tin oxide thin film transistor with a tellurium layer.

[0071] In this embodiment, Te layers are provided on both sides of the upper surface of the tin oxide channel layer. The Te layer and the SnO2 layer form a double heterojunction. The double heterojunction can also achieve a positive shift of the threshold voltage based on the matching effect of the SnO2 and Te work functions.

[0072] However, when a double heterojunction is formed, a hole accumulation layer on the SnO2 side and an electron accumulation layer on the Te side are formed at the interface between Te and SnO2 under the source. The direction of the accumulated space charge electric field is consistent with the direction of source-drain pressure. Therefore, the width of the space charge region increases, and it is difficult for electrons in the channel region to flow into the metal electrode, resulting in a significant reduction in the on-state current.

[0073] Comparative Example: Figure 1 A tin oxide thin film transistor structure without a tellurium layer is given as a control structure. Figure 1 A tin oxide thin film transistor without a tellurium layer is provided with a substrate, a bottom gate dielectric layer and a tin oxide channel layer from bottom to top, and a source electrode and a drain electrode are provided on the tin oxide channel layer.

[0074] The substrate is a silicon substrate, and the bottom gate is silicon. The thickness of the gate dielectric layer is 100nm, and the gate dielectric layer is silicon oxide (SiO2). The tin oxide channel layer uses a tin oxide film as the channel layer, and the thickness of the tin oxide film is 30nm. The source and drain electrodes are both Ni metal, and the thickness of Ni is 100nm.

[0075] Experimental verification: 1. The single heterojunction tin oxide thin film transistors with different tellurium layer thicknesses in Examples 1 to 4 are used as example structures, and the tin oxide thin film transistor without heterojunction in the comparative example is used as a control structure. The transfer characteristics of the example structure and the control structure are tested respectively. The measured transfer characteristic curves are shown in FIG. Figure 3 As shown; Figure 3 The horizontal axis is the gate voltage V GS , the vertical axis is the source-drain current I DS The turning point of the transfer characteristic curve is the threshold voltage. Table 1 shows the electrical performance parameters of tin oxide thin film transistors with single heterojunction and no heterojunction with different tellurium layer thicknesses.

[0076] Table 1

[0077] Combination Figure 3 As can be seen from Table 1, the threshold voltage (V TH ) moves positively; and, as the thickness of the tellurium layer in the single heterojunction increases, the SnO2TFT threshold voltage (V TH ) The larger the positive offset value, the lower the off-state current value will be. -12The A level no longer decreases, but the on-state current value decreases, and its switching ratio (I on / I off ) shows a trend of increasing first and then decreasing, and the subthreshold swing (SS) and mobility (μ FE ) show a decreasing trend; at a thickness of 10nm, the SnO2TFT threshold voltage (V TH ) is 0.1V, the device can be turned on at a lower gate voltage, significantly reducing the operating voltage of the drive circuit and resulting in lower power consumption.

[0078] 2. Transfer characteristic tests were performed on the tin oxide thin film transistor without a tellurium layer in the comparative example (no heterojunction), the tin oxide thin film transistor with a single heterojunction and a tellurium layer thickness of 10 nm in Example 2, and the tin oxide thin film transistor with a double heterojunction and a tellurium layer thickness of 10 nm in Example 5. The measured transfer characteristic curves are shown in FIG. Figure 5 As shown, Figure 5 The horizontal axis is the gate voltage V GS , the vertical axis is the source-drain current I DS The turning point of the transfer characteristic curve is the threshold voltage. Table 2 shows the electrical performance parameters of the tin oxide thin film transistor without heterojunction, the single heterojunction tin oxide thin film transistor with a tellurium layer thickness of 10nm, and the double heterojunction tin oxide thin film transistor with a tellurium layer thickness of 10nm.

[0079] Table 2

[0080] Combination Figure 5 As can be seen from Table 2, the threshold voltage (V TH ) are obviously moving forward. However, the on-state current value of the double heterojunction tin oxide thin film transistor is obviously reduced, and the switching ratio is reduced (I on / I off ), mobility (μ FE ) also decreased significantly.

[0081] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A tin oxide thin film transistor, characterized in that: include: A substrate comprising a gate electrode, wherein a gate dielectric layer is disposed on the substrate, a tin oxide channel layer is disposed on the upper surface of the gate dielectric layer, a tellurium layer is disposed on one side of the upper surface of the tin oxide channel layer, a source electrode is disposed on the other side of the upper surface of the tin oxide channel layer, and a gap exists between the tellurium layer and the source electrode; and a drain electrode is disposed on the upper surface of the tellurium layer.

2. A tin oxide thin film transistor as claimed in claim 1, characterized in that: The tellurium layer is a tellurium thin film with a thickness of 5-20 nm.

3. A tin oxide thin film transistor, characterized in that: include: A substrate comprising a gate electrode, wherein a gate dielectric layer is provided on the substrate, a tin oxide channel layer is provided on the upper surface of the gate dielectric layer, tellurium layers are provided on both sides of the upper surface of the tin oxide channel layer, and there is a gap between the tellurium layers on both sides; a drain electrode is provided on the upper surface of one side of the tellurium layer, and a source electrode is provided on the upper surface of the other side of the tellurium layer.

4. A tin oxide thin film transistor as claimed in claim 3, characterized in that: The tellurium layer is a tellurium thin film with a thickness of 10 nm.

5. A tin oxide thin film transistor as claimed in claim 1 or 3, characterized in that: The gate electrode is a bottom gate electrode, which is located at the bottom of the substrate; the bottom gate electrode is heavily doped P-type silicon.

6. A tin oxide thin film transistor as claimed in claim 1 or 3, characterized in that: The source electrode and the drain electrode are both made of nickel metal.

7. A method for preparing a tin oxide thin film transistor as claimed in claim 1, characterized in that: include: preparing a bottom gate dielectric layer on a substrate; Depositing a tin oxide film on a substrate including a bottom gate dielectric layer to form an amorphous tin oxide channel layer; performing air annealing to form a crystalline tin oxide channel layer; A tellurium thin film is prepared on one side of the upper surface of the crystalline tin oxide channel layer by thermal evaporation to form a tellurium layer; Nickel is thermally evaporated on the other side of the upper surface of the crystalline tin oxide channel layer and the upper surface of the tellurium layer as a source electrode and a drain electrode, respectively.

8. The method for preparing a tin oxide thin film transistor according to claim 7, characterized in that: The tellurium layer has a thickness of 5-20 nm.

9. A method for preparing a tin oxide thin film transistor as claimed in claim 3, characterized in that: include: preparing a bottom gate dielectric layer on a substrate; Depositing a tin oxide film on a substrate including a bottom gate dielectric layer to form an amorphous tin oxide channel layer; performing air annealing to form a crystalline tin oxide channel layer; Using thermal evaporation to prepare tellurium thin films on both sides of the upper surface of the crystalline tin oxide channel layer to form tellurium layers; and there is a gap between the tellurium layers on the two sides; Nickel is thermally evaporated on the upper surface of the tellurium layer on both sides of the crystalline tin oxide channel layer as a source electrode and a drain electrode.

10. The method for preparing a tin oxide thin film transistor according to claim 9, characterized in that: The tellurium layer has a thickness of 10 nm.

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