Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate, an epitaxial layer, a first conductive layer, and a second conductive layer. The epitaxial layer is arranged on one side of the substrate and comprises a doping layer and a drift layer, the doping layer is located on the side, away from the substrate, of the drift layer, and the conduction type of the drift layer is different from that of at least part of the doping layer. The first conductive layer is located on the side, back to the substrate, of the epitaxial layer. The second conductive layer is located on one side of the substrate back to the epitaxial layer. Wherein any unit region of the substrate and the epitaxial layer is internally provided with a metal composite center, and the concentration of the metal composite center in the drift layer is greater than the concentration of the metal composite center in at least part of the unit region in the doped layer. The performance of the semiconductor device can be effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] In the design and manufacture of semiconductor devices, optimizing carrier lifetime and recombination mechanism is one of the key factors to improve device performance. Heavy metals (such as platinum, gold, silver, etc.) are widely used as recombination centers in various semiconductor devices. By introducing these heavy metal atoms, the recombination rate of carriers can be effectively controlled, thereby improving the working characteristics of semiconductor devices.

[0003] During the deposition of heavy metals and the subsequent preparation process, non-uniform concentration recombination centers are usually formed inside the semiconductor device, especially near the PN junction, which causes the reverse leakage current of the semiconductor device to increase and reduce the performance of the semiconductor device. Summary of the invention

[0004] The semiconductor device and the method for manufacturing the same provided by the embodiments of the present application can effectively improve the performance of the semiconductor device.

[0005] In a first aspect, a semiconductor device is proposed according to an embodiment of the present application, and the semiconductor device includes a substrate, an epitaxial layer, a first conductive layer, and a second conductive layer. The epitaxial layer is arranged on one side of the substrate, and the epitaxial layer includes a doped layer and a drift layer. The doped layer is located on the side of the drift layer away from the substrate, and the conductivity type of the drift layer is different from the conductivity type of at least part of the doped layer. The first conductive layer is located on the side of the epitaxial layer facing away from the substrate. The second conductive layer is located on the side of the substrate facing away from the epitaxial layer. Among them, a metal recombination center is provided in any unit area of ​​the substrate and the epitaxial layer, and the concentration of the metal recombination center in the drift layer is greater than the concentration of the metal recombination center in at least part of the unit area of ​​the doped layer.

[0006] According to a first aspect of an embodiment of the present application, the doping layer includes a main doping region and a terminal doping region, the terminal doping region is located on the peripheral side of the main doping region, and the semiconductor device also includes a first dielectric layer, the first dielectric layer is located on the side of the epitaxial layer facing away from the substrate, and along a direction perpendicular to the substrate, the first dielectric layer and the terminal doping region at least partially overlap.

[0007] According to a first aspect of an embodiment of the present application, the first dielectric layer is provided with a through hole, and the through hole exposes a portion of the surface of the epitaxial layer.

[0008] According to a first aspect of an embodiment of the present application, the metal complex center includes one or more combinations of gold atoms, platinum atoms, and palladium atoms.

[0009] In a second aspect, an embodiment of the present application also provides a method for preparing a semiconductor device. The method includes preparing an epitaxial layer on one side of a substrate, the epitaxial layer including a doped layer and a drift layer, the doped layer is located on the side of the drift layer away from the substrate, and the conductivity type of the drift layer is different from the conductivity type of at least part of the doped layer. A first metal material layer is deposited on the surface of at least one of the substrate and the epitaxial layer. A first heat treatment process is performed to allow atoms in the first metal material layer to diffuse into the structure to any unit area of ​​the substrate and the epitaxial layer and form a metal composite center. A first ion material is injected from the side of the epitaxial layer facing away from the substrate and a second heat treatment process is performed, the first ion material is at least injected into the doped layer, so that the metal composite center in the doped layer diffuses to the surface of the epitaxial layer. The concentration of the metal composite center in the drift layer is greater than the concentration of the metal composite center in at least part of the unit area in the doped layer.

[0010] According to a second aspect of the embodiment of the present application, the doped layer includes a main doped region and a terminal doped region, and the terminal doped region is located on the peripheral side of the main doped region. Before the step of depositing a first metal material layer on the surface of at least one of the substrate and the epitaxial layer, the step also includes: preparing a first dielectric prefabricated layer at least on the side of the terminal doped region facing away from the substrate.

[0011] According to the second aspect of the embodiment of the present application, before the step of injecting the first ion material from the side of the epitaxial layer facing away from the substrate and performing the second heat treatment process, the step includes: patterning the first dielectric prefabricated layer to form a first dielectric layer and a through hole, wherein the through hole exposes part of the epitaxial layer surface.

[0012] According to the second aspect of the embodiment of the present application, the implantation dose range of the first ion material is 1e 12 cm -2 ~1e 15 cm -2 .

[0013] According to a second aspect of the embodiment of the present application, the temperature of the first heat treatment process is greater than the temperature of the second heat treatment process.

[0014] According to a second aspect of the embodiment of the present application, the temperature of the second heat treatment process is 500°C to 700°C.

[0015] According to the semiconductor device and preparation method thereof provided by the present application, the concentration of metal recombination centers in the drift layer is made greater than the concentration of metal recombination centers in at least a portion of a unit area in the doping layer to reduce the concentration of metal recombination centers in the doping layer, thereby reducing the concentration of metal recombination centers at the PN junction in the doping layer, reducing reverse leakage current, improving the reliability of the semiconductor device, and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0017] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application;

[0018] Figure 2 A schematic cross-sectional structure diagram of another semiconductor device provided in some embodiments of the present application;

[0019] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0020] Figures 4 to 10 A schematic diagram of a process structure of a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0021] Fig.11 A schematic diagram of the concentration distribution of metal recombination centers in a semiconductor device provided in some embodiments of the present application;

[0022] Fig.12 A schematic diagram of metal recombination center concentration distribution in another semiconductor device provided for some embodiments of the present application.

[0023] Marking Description:

[0024] 10. Substrate;

[0025] 20, epitaxial layer; 21, doping layer; 211, main doping region; 212, terminal doping region; 22, drift layer;

[0026] 30, metal composite center; 40, first conductive layer; 50, second conductive layer; 60, first dielectric layer; H, through hole; 70, second dielectric layer;

[0027] 1. First metal material layer; 2. First ion material; 3. First dielectric prefabricated layer; Z, thickness direction.

[0028] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0029] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0030] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0031] Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device provided for some embodiments of the present application.

[0032] like Figure 1 As shown, an embodiment of the present application provides a semiconductor device, which includes a substrate 10, an epitaxial layer 20, a first conductive layer 40, and a second conductive layer 50. The epitaxial layer 20 is disposed on one side of the substrate 10, and the epitaxial layer 20 includes a doped layer 21 and a drift layer 22. The doped layer 21 is located on the side of the drift layer 22 away from the substrate 10, and the conductivity type of the drift layer 22 is different from the conductivity type of at least part of the doped layer 21. The first conductive layer 40 is located on the side of the epitaxial layer 20 facing away from the substrate 10. The second conductive layer 50 is located on the side of the substrate 10 facing away from the epitaxial layer 20. Among them, a metal composite center 30 is provided in any unit area of ​​the substrate 10 and the epitaxial layer 20, and the concentration of the metal composite center 30 in the drift layer 22 is greater than the concentration of the metal composite center 30 in at least part of the unit area of ​​the doped layer 21.

[0033] In the embodiments of the present application, the semiconductor device may include power devices such as a fast recovery diode (FRD), a Schottky diode, an insulated gate bipolar transistor (IGBT), and a metal oxide field effect transistor (MOSFET).

[0034] The substrate 10 mainly plays a supporting role, and other layer structures are stacked in sequence on the substrate 10. The stacking arrangement mentioned here means that other layer structures are stacked in sequence along a thickness direction Z perpendicular to the substrate 10. Among them, the substrate 10 may include a single or multiple film layer structures, and the specific film layer structure of the substrate 10 is not limited in the embodiment of the present application. In addition, the thickness direction Z of other layer structures located on the substrate 10 is usually consistent with the thickness direction Z of the substrate 10 itself. Therefore, for the convenience of expression, the thickness direction Z of the substrate 10 or the thickness direction Z of other film layers and the direction perpendicular to the substrate 10 mentioned in the embodiment of the present application are all illustrated in the same direction.

[0035] The conductive type may include a P-type conductive type and an N-type conductive type. Layer structures of different conductive types may be formed by different semiconductor materials. For example, a layer structure of a P-type conductive type is formed by a P-type semiconductor material, and a layer structure of an N-type conductive type is formed by an N-type semiconductor material.

[0036] Exemplarily, the conductivity type of the substrate 10 is N-type conductivity type, the conductivity type of the drift layer 22 is N-type conductivity type, and the conductivity type of the doped layer 21 is P-type conductivity type. Optionally, the doped layer 21 can be formed by preparing a P-type semiconductor material, or the doped layer 21 can be formed by preparing an N-type semiconductor material and then implanting P-type ions. For example, the conductivity type of the epitaxial layer 20 as a whole is N-type conductivity type, and the doped layer 21 is formed by implanting P-type ions at one end of the epitaxial layer 20 away from the substrate 10.

[0037] The epitaxial layer 20 is disposed on one side of the substrate 10 , and the epitaxial layer 20 may be formed by epitaxial growth of the substrate 10 .

[0038] The drift layer 22 may be a channel for current transmission. When an external voltage is applied to the semiconductor device, the charges in the drift layer 22 may move due to the electric field force, and this movement enables current transmission.

[0039] The doping layer 21 is generally used to form structures such as a PN junction, an ohmic contact, and a barrier layer to achieve specific electrical properties.

[0040] For example, the doping layer 21 may include an N-type doping layer 21 and a P-type doping layer 21 , and a PN junction may be formed at the interface between the N-type doping layer 21 and the P-type doping layer 21 . The PN junction has unidirectional conductivity.

[0041] In some examples, the first conductive layer 40 may include a first electrode, and the second conductive layer 50 may include a second electrode. Optionally, the first electrode and the second electrode have opposite polarities, that is, when the first electrode is positive, the second electrode is negative; when the first electrode is negative, the second electrode is positive. Of course, in some semiconductor devices, one of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0042] Exemplarily, the stacked structure of the semiconductor device along the thickness direction Z is sequentially the second conductive layer 50 - the substrate 10 - the epitaxial layer 20 and the first conductive layer 40 .

[0043] In some examples, the metal recombination center 30 may be a heavy metal recombination center 30, which means that certain heavy metal impurities in the semiconductor device can serve as recombination centers. The recombination center can promote the recombination of carriers and plays a decisive role in the length of the non-equilibrium carrier lifetime. The metal recombination center 30 introduces one or more deep energy levels in the bandgap, which can capture both electrons and holes, thereby promoting the recombination process. The presence of the metal recombination center 30 can reduce the forward conduction voltage drop of the device and increase the conduction loss; at the same time, it can also reduce the switching time and reverse recovery charge, and reduce the loss associated with the turn-off.

[0044] The unit area may refer to an area of ​​a preset unit size in a layer structure, for example, the unit area may refer to an area of ​​1 cubic millimeter. Any unit area refers to an area of ​​any preset unit size in a layer structure, for example, any area of ​​1 cubic millimeter in a layer structure.

[0045] As an example, any unit area of ​​the substrate 10 is provided with a metal composite center 30 , that is, any area of ​​a preset unit size of the substrate 10 is provided with a metal composite center 30 .

[0046] As an example, any unit area of ​​the epitaxial layer 20 is provided with a metal recombination center 30 , that is, any area of ​​a preset unit size of the epitaxial layer 20 is provided with a metal recombination center 30 .

[0047] In some examples, the concentration of the metal recombination centers 30 in the drift layer 22 is greater than the concentration of the metal recombination centers 30 in any unit area in the doping layer 21. In other examples, the concentration of the metal recombination centers 30 in the drift layer 22 is greater than the concentration of the metal recombination centers 30 in a portion of the unit area in the doping layer 21, and the concentration of the metal recombination centers 30 in the drift layer 22 is equal to the concentration of the metal recombination centers 30 in another portion of the unit area in the doping layer 21. For example, the concentration of the metal recombination centers 30 in the region from the surface of the doping layer 21 on the side facing away from the substrate 10 to the preset position in the doping layer 21 is less than the concentration of the metal recombination centers 30 in the drift layer 22, and the concentration of the metal recombination centers 30 in the region from the preset position in the doping layer 21 to the interface between the doping layer 21 and the drift layer 22 is less than the concentration of the metal recombination centers 30 in the drift layer 22. Optionally, the preset position may be half the thickness of the doping layer 21. The preset position may also be the side of the PN junction facing the drift layer 22.

[0048] In some examples, the concentration of metallic recombination centers 30 within substrate 10 is greater than, equal to, or less than the concentration of metallic recombination centers 30 within drift layer 22 .

[0049] In some examples, the concentration of metallic recombination centers 30 within substrate 10 is greater than, equal to, or less than the concentration of metallic recombination centers 30 within doping layer 21 .

[0050] In some examples, the metal recombination centers 30 in the doping layer 21 may be arranged in equal concentration, that is, the concentration of the metal recombination centers 30 in any two unit areas in the doping layer 21 is the same.

[0051] In other examples, the concentration of the metal recombination centers 30 in the doping layer 21 may be different. For example, from the surface of the doping layer 21 facing away from the substrate 10 to the surface of the doping layer 21 facing the substrate 10, the concentration of the metal recombination centers 30 may gradually decrease, gradually increase, first decrease and then increase, first increase and then decrease, or the local concentration may be greater than the concentration in other regions.

[0052] In the semiconductor device provided by the present application, the concentration of the metal recombination center 30 in the drift layer 22 is made greater than the concentration of the metal recombination center 30 in at least a portion of a unit area in the doping layer 21, so as to reduce the concentration of the metal recombination center 30 in the doping layer 21, thereby reducing the concentration of the metal recombination center 30 at the PN junction in the doping layer 21, reducing the reverse leakage current, improving the reliability of the semiconductor device, and improving the performance of the semiconductor device.

[0053] In some optional embodiments, Figure 1 As shown, the doping layer 21 includes a main doping region 211 and a terminal doping region 212, and the terminal doping region 212 is located on the peripheral side of the main doping region 211. The semiconductor device also includes a first dielectric layer 60, and the first dielectric layer 60 is located on the side of the epitaxial layer 20 facing away from the substrate 10, and along the direction perpendicular to the substrate 10, the first dielectric layer 60 and the terminal doping region 212 at least partially overlap.

[0054] The main doping region 211 includes a cell region and a main junction region, the cell region includes a PN junction, and the cell region has unidirectional conductivity. When forward conduction occurs, the cell region allows current to pass through; when reverse conduction occurs, current is prevented from passing through. The embodiment of the present application does not limit the doping concentration, width, and structural design of the cell region. The main junction region is a region arranged around the cell region. The main junction region is used to enhance the voltage resistance of the semiconductor device and improve the current distribution. In the main junction region, a special doping process and structural design are usually adopted, such as arranging multiple first doping regions at intervals, etc., to form a structure that diverges to the surroundings. This structure helps to reduce the charge injection efficiency of the main junction region, thereby reducing the resistivity of the main junction region and improving the current gathering effect. At the same time, it can also reduce the area occupied by the main junction region and reduce the cost of the semiconductor device. Of course, the main doping region 211 can also include other doping regions for optimizing the performance of the semiconductor device.

[0055] The terminal doping region 212 includes structures such as a voltage divider field ring and a guard ring. The voltage divider field ring is located at the edge of the semiconductor device and forms a series of electric field distributions by changing the doping concentration and width, thereby effectively dispersing and withstanding high voltage. The design of the voltage divider field ring can significantly reduce the electric field concentration effect and improve the withstand voltage performance of the semiconductor device. The guard ring is usually located outside the voltage divider field ring to further protect the semiconductor device from high voltage breakdown.

[0056] The first dielectric layer 60 can provide electrical isolation. The terminal doping region 212 is used to improve the voltage resistance and stability of the semiconductor device. The first dielectric layer 60 can reduce the accidental electrical connection between the terminal doping region 212 and other regions, thereby improving the reliability of the semiconductor device. Optionally, the first dielectric layer 60 is located on the peripheral side of the first conductive layer 40.

[0057] In some examples, the first dielectric layer 60 overlaps the terminal doping region 212 along a direction perpendicular to the substrate 10, that is, in the thickness direction Z. In other examples, the first dielectric layer 60 overlaps a portion of the terminal doping region 212 along a direction perpendicular to the substrate 10, that is, in the thickness direction Z.

[0058] Figure 2 A schematic diagram of the cross-sectional structure of another semiconductor device provided for some embodiments of the present application.

[0059] In some optional embodiments, Figure 2 As shown, the first dielectric layer 60 is provided with a through hole H, and the through hole exposes a portion of the surface of the epitaxial layer 20 .

[0060] In some examples, the first dielectric layer 60 is provided with through holes H to separate the first dielectric layer 60 into a plurality of spacers.

[0061] In some examples, the number of through holes H may include one or more.

[0062] In some examples, the shape of the through hole H may include a circular hole, a square hole, a waist-shaped hole, or other shapes.

[0063] In some optional embodiments, the metal complex center 30 includes one or more combinations of gold atoms, platinum atoms, and palladium atoms.

[0064] In some examples, the metal complex center 30 includes one of gold atoms, platinum atoms, and palladium atoms. In other examples, the metal complex center 30 includes a combination of gold atoms, platinum atoms, and palladium atoms.

[0065] The above configuration of the embodiment of the present application is helpful to reduce the preparation cost of the metal composite center 30, increase the selection range of the metal composite center 30, and increase the use range of semiconductor devices.

[0066] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided in some embodiments of the present application. Figures 4 to 10 A schematic diagram of the process structure of a method for manufacturing a semiconductor device provided in some embodiments of the present application.

[0067] Second, as Figure 3 , Figures 4 to 10 As shown, the embodiment of the present application also provides a method for preparing a semiconductor device. The method comprises the following steps:

[0068] S100, preparing an epitaxial layer 20 on one side of the substrate 10, the epitaxial layer comprising a doped layer 21 and a drift layer 22, the doped layer 21 is located on a side of the drift layer 22 away from the substrate 10, and the conductivity type of the drift layer 22 is different from the conductivity type of at least part of the doped layer 21.

[0069] In step S100, Figure 4 and Figure 5 As shown, the epitaxial layer 20 can be prepared by epitaxial growth. In some examples, the epitaxial layer 20 as a whole is formed by epitaxial growth of a material of the same conductivity type as the substrate 10 to form an epitaxial prefabricated layer, and doping ions are injected from the side of the epitaxial prefabricated layer facing away from the substrate 10, and the doping ions are injected into a preset position to form a doping layer 21. The doping layer may include a plurality of doping parts, and the conductivity types of the doping ions doped in the plurality of doping parts may be the same or different. The dosages of the doping ions doped in the plurality of doping parts may be the same or different.

[0070] Optionally, the doping layer 21 includes a main doping region 211 and a terminal doping region 212 . The main doping region 211 and the terminal doping region 212 may be formed by different processes or by one process.

[0071] S200 , depositing a first metal material layer 1 on a surface of at least one of the substrate 10 and the epitaxial layer 20 .

[0072] In step S200, Figure 6 As shown, after the doping layer 21 is prepared, a first metal material layer 1 can be deposited on the surface of the substrate 10 and / or the surface of the epitaxial layer 20 facing away from the substrate 10. The first metal material layer 1 can be prepared by processes such as physical vapor deposition, chemical vapor deposition or electroplating.

[0073] Optionally, the first metal material layer 1 can be deposited only on the surface of the substrate 10 facing away from the epitaxial layer 20, or only on the surface of the epitaxial layer 20 facing away from the substrate 10, or the first metal material layer 1 can be deposited on both the surface of the substrate 10 facing away from the epitaxial layer 20 and the surface of the epitaxial layer 20 facing away from the substrate 10.

[0074] S300 , performing a first heat treatment process to diffuse atoms in the first metal material layer 1 into the structure to any unit area of ​​the substrate 10 and the epitaxial layer 20 and form a metal composite center 30 .

[0075] In step S300, Figure 7 As shown, the semiconductor material deposited with the first metal material layer 1 is heated. During the heating process, the heavy metal atoms begin to diffuse in the semiconductor material under the action of thermal energy. The diffusion process follows Fick's law, that is, the diffusion rate is proportional to the concentration gradient. During the heating process, the heavy metal atoms diffuse through the lattice gaps or substitutional positions of the semiconductor material. During the diffusion process, the heavy metal atoms interact with the atoms in the semiconductor material to form metal composite centers 30. After the diffusion is completed, the semiconductor material is cooled to promote the stable distribution of the heavy metal atoms in the semiconductor material and reduce the possibility of thermal stress caused by rapid cooling.

[0076] Optionally, the first thermal treatment process includes a first annealing diffusion process.

[0077] S400, a first ion material 2 is implanted from the side of the epitaxial layer 20 facing away from the substrate 10 and a second heat treatment process is performed, wherein the first ion material 2 is implanted at least into the doping layer 21, so that the metal recombination centers 30 in the doping layer 21 diffuse to the surface of the epitaxial layer 20. The concentration of the metal recombination centers 30 in the drift layer 22 is greater than the concentration of the metal recombination centers 30 in at least a portion of the unit area in the doping layer 21.

[0078] In step S400, Figures 8 to 10 As shown, the first ion material 2 with preset energy and preset dose is injected into the epitaxial layer 20 from the surface of the epitaxial layer 20 facing away from the substrate 10. The first ion material 2 can be injected into at least the doping layer 21, and then a second heat treatment process is performed to diffuse the first ion material 2.

[0079] Optionally, the first ion material 2 includes aluminum ions, which are highly reactive with oxygen atoms and have a relatively fast diffusion coefficient, and an oxide layer is generally naturally formed on the surface of the epitaxial layer 20 (for example, when the material of the epitaxial layer 20 is silicon, a silicon dioxide layer is formed on the surface of the epitaxial layer 20 facing away from the substrate 10), or an oxide layer is formed by deposition growth before step S400, or an oxidizing atmosphere is introduced in the second heat treatment process, which will form a segregation effect between the epitaxial layer 20 and the oxide layer (for example, silicon and silicon dioxide, explained below with the epitaxial layer 20 being silicon and the first ion material 2 being aluminum) or at the interface between silicon and oxygen, and aluminum diffuses outward to the surface of the epitaxial layer 20 facing away from the substrate 10 and is evaporated.

[0080] In the above process, the injection damage and diffusion migration of the first ion material 2 form lattice defects and vacancies in silicon. These lattice defects and vacancies have the ability to capture heavy metal ions, so that heavy metal atoms such as platinum and gold gradually move to the surface of the silicon wafer, thereby synchronously forming an external diffusion reaction, thereby reducing the concentration of heavy metal atoms such as platinum and gold in the injection area and its valley width.

[0081] Furthermore, the concentration value of the formed heavy metal ion low concentration area and the valley width range of the low concentration area can be adjusted and changed by the aluminum ion injection energy, aluminum ion injection concentration and the subsequent annealing diffusion gettering process temperature / time / atmosphere, etc. For example, a higher injection energy can form a deeper valley bottom position after gettering, an oxygen-containing atmosphere can form a lower heavy metal ion concentration after gettering, and a higher injection concentration, a higher annealing diffusion gettering temperature and a longer time can form a lower heavy metal ion concentration and gettering valley bottom width range after gettering.

[0082] Optionally, the preset energy of the first ion material 2 implantation is 100 keV to 500 keV. Exemplarily, the preset energy of the first ion material 2 implantation is 100 keV, 110 keV, 120 keV, 150 keV, 200 keV, 250 keV, 300 keV, 350 keV, 400 keV or 500 keV.

[0083] Optionally, after the metal composite center 30 is prepared, the first conductive layer 40 and the second conductive layer 50 may be prepared.

[0084] Optionally, after the first conductive layer 40 is prepared, a second dielectric layer 70 may be prepared on the side of the terminal doping region 212 facing away from the substrate 10 . Optionally, the first dielectric layer 60 is located between the second dielectric layer 70 and the epitaxial layer 20 .

[0085] The above steps in the embodiment of the present application are conducive to improving the accuracy of controlling the concentration of the metal composite center 30, reducing the difficulty of preparing the metal composite center 30, and reducing the concentration of the metal composite center 30 in the doping layer 21, thereby reducing the concentration of the metal composite center 30 at the PN junction in the doping layer 21, reducing the reverse leakage current, improving the reliability of the semiconductor device, and improving the performance of the semiconductor device.

[0086] In some optional embodiments, Figure 5 As shown, the doping layer 21 includes a main doping region 211 and a terminal doping region 212, and the terminal doping region is located at the peripheral side of the main doping region 211. Before the step of depositing the first metal material layer 1 on the surface of at least one of the substrate 10 and the epitaxial layer 20, the step further includes:

[0087] S500 , preparing a first dielectric prefabricated layer 3 at least on a side of the terminal doping region 212 facing away from the substrate 10 .

[0088] In step S500, a first dielectric prefabricated layer 3 is prepared on the side of the terminal doping region 212 facing away from the substrate 10. The first dielectric prefabricated layer 3 may be composed of one or more dielectric structures. The first dielectric prefabricated layer 3 may also include specific materials, such as materials that improve the hardness, wear resistance and other properties of the dielectric layer.

[0089] The first dielectric prefabricated layer 3 may be prepared before the preparation step S200 or after the preparation step S200.

[0090] In the embodiment of the present application, the first dielectric prefabricated layer 3 can be used to protect the terminal doping region 212, and can also be used to prepare the terminal doping region 212 and the main doping region 211, so as to improve the preparation yield of the semiconductor device.

[0091] In some optional embodiments, Figure 8 As shown, the steps of implanting the first ion material 2 from the side of the epitaxial layer 20 facing away from the substrate 10 and performing the second heat treatment process include:

[0092] S600 , patterning the first dielectric prefabricated layer 3 to form a first dielectric layer 60 and a through hole H, wherein the through hole exposes a portion of the surface of the epitaxial layer 20 .

[0093] In step S600, a patterning process such as photolithography may be used to form the first dielectric prefabricated layer 3 into the first dielectric layer 60 and the through hole H. The through hole exposes a portion of the surface of the epitaxial layer 20 to reduce the shielding of the first dielectric layer 60 on the first ion material 2, increase the implantation depth of the first ion material 2, and reduce the difficulty of the implantation process and the manufacturing cost.

[0094] Optionally, the through hole H may expose a portion of the terminal doping region 212 .

[0095] In some optional embodiments, the implantation dose of the first ion material 2 is in the range of 1e 12 cm -2 ~1e 15 cm -2 .

[0096] In some examples, the implantation dose of the first ion material 2 is in the range of 1e 12 cm -2 , 1e 13 cm -2 , 1e 14 cm -2 or 1e 15 cm -2 .

[0097] In the embodiment of the present application, the implantation dose of the first ion material 2 is set to be greater than or equal to 1e 12 cm -2 , so as to increase the depth of the first ion material 2 implantation, thereby reducing the concentration of the metal complex center 30 at the PN junction in the doping layer 21 and reducing the reverse leakage current; the implantation dose of the first ion material 2 is set to be less than or equal to 1e 15 cm -2 , so as to reduce the possibility of local abnormality in the performance of the drift layer 22 caused by local abnormality in the concentration of the metal composite center 30 in the drift layer 22, and improve the reliability of the semiconductor device.

[0098] In some optional embodiments, the temperature of the first heat treatment process is greater than the temperature of the second heat treatment process to reduce the possibility that the heating diffusion process of the second heat treatment process affects the metal atoms of the metal recombination center 30 in the drift layer 22, thereby improving the reliability of the semiconductor device.

[0099] In some optional embodiments, the temperature of the second heat treatment process is 500°C to 700°C.

[0100] Optionally, the second heat treatment process includes a second annealing process.

[0101] Illustratively, the temperature of the second heat treatment process is 500°C, 510°C, 520°C, 530°C, 550°C, 600°C, 650°C, or 700°C.

[0102] In some examples, the temperature of the first thermal treatment process is 750°C to 1200°C.

[0103] The embodiment of the present application sets the second heat treatment process temperature to greater than or equal to 500°C, which helps to repair lattice damage and restore the order of the lattice; setting the second heat treatment process temperature to less than or equal to 700°C is beneficial to increasing the activation rate of impurities, while reducing excessive diffusion of impurities and improving the performance of semiconductor devices.

[0104] Fig.11 A schematic diagram of the concentration distribution of metal recombination centers in a semiconductor device provided for some embodiments of the present application. Fig.12 A schematic diagram of the concentration distribution of metal recombination centers in another semiconductor device provided in some embodiments of the present application. It should be noted that: Fig.11 is a schematic diagram of concentration distribution after step S300 is completed. Fig.12 Schematic diagram of concentration distribution after step S400 is completed. The X coordinate is the concentration value of the metal composite center 30, and the Y coordinate is the height value, wherein the 0 point is the corresponding position of the surface of the side of the substrate 10 facing away from the epitaxial layer 20, and the coordinate point (0, A) is the corresponding position of the surface of the side of the epitaxial layer 20 facing away from the substrate 10. The coordinate (0, B) is the corresponding position at the interface between the drift layer 22 and the doping layer 21.

[0105] Reference Figure 7 , Figures 10 to 12 It can be known that the concentration of the metal recombination centers 30 in the doping layer 21 in the semiconductor material after completing step S300 is greater than or equal to the concentration of the metal recombination centers 30 in the drift layer 22, and the concentration of the metal recombination centers 30 on the side of the doping layer 21 close to the drift layer 22 in the semiconductor material after completing step S400 is less than the concentration of the metal recombination centers 30 in the drift layer 22, and the metal recombination centers 30 in the drift layer 22 are set to be of equal concentration to improve the reliability of the drift layer 22.

[0106] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: Substrate: An epitaxial layer is arranged on one side of the substrate, the epitaxial layer comprises a doped layer and a drift layer, the doped layer is located on a side of the drift layer away from the substrate, and the conductivity type of the drift layer is different from the conductivity type of at least part of the doped layer; A first conductive layer, located on a side of the epitaxial layer facing away from the substrate; A second conductive layer is located on a side of the substrate facing away from the epitaxial layer; Wherein, metal recombination centers are provided in any unit area of ​​the substrate and the epitaxial layer, and the concentration of the metal recombination centers in the drift layer is greater than the concentration of the metal recombination centers in at least part of the unit areas in the doping layer.

2. The semiconductor device according to claim 1, wherein: The doping layer includes a main doping region and a terminal doping region, wherein the terminal doping region is located on the peripheral side of the main doping region. The semiconductor device also includes a first dielectric layer, wherein the first dielectric layer is located on a side of the epitaxial layer facing away from the substrate, and along a direction perpendicular to the substrate, the first dielectric layer at least partially overlaps with the terminal doping region.

3. The semiconductor device according to claim 2, characterized in that The first dielectric layer is provided with a through hole, and the through hole exposes a portion of the surface of the epitaxial layer.

4. The semiconductor device according to claim 1, wherein: The metal complex center includes one or more combinations of gold atoms, platinum atoms and palladium atoms.

5. A method for preparing a semiconductor device, characterized in that: include: Preparing an epitaxial layer on one side of the substrate, the epitaxial layer comprising a doped layer and a drift layer, the doped layer being located on a side of the drift layer away from the substrate, and the conductivity type of the drift layer being different from the conductivity type of at least a portion of the doped layer; Depositing a first metal material layer on a surface of at least one of the substrate and the epitaxial layer; Performing a first heat treatment process to diffuse atoms in the first metal material layer into the structure to any unit area of ​​the substrate and the epitaxial layer and form a metal composite center; A first ion material is injected from the side of the epitaxial layer facing away from the substrate and a second heat treatment process is performed, wherein the first ion material is at least injected into the doping layer so that the metal recombination centers in the doping layer diffuse to the surface of the epitaxial layer, and the concentration of the metal recombination centers in the drift layer is greater than the concentration of the metal recombination centers in at least a portion of a unit area in the doping layer.

6. The preparation method according to claim 5, characterized in that: The doping layer comprises a main doping region and a terminal doping region, wherein the terminal doping region is located at a peripheral side of the main doping region; Before the step of depositing a first metal material layer on the surface of at least one of the substrate and the epitaxial layer, the method further comprises: A first dielectric prefabricated layer is prepared at least on a side of the terminal doping region facing away from the substrate.

7. The preparation method according to claim 6, characterized in that: The step of implanting the first ion material from the side of the epitaxial layer facing away from the substrate and performing a second heat treatment process includes: The first dielectric prefabricated layer is patterned to form a first dielectric layer and a through hole, wherein the through hole exposes a portion of the surface of the epitaxial layer.

8. The preparation method according to claim 5, characterized in that: The implantation dose range of the first ion material is 1e 12 cm -2 ~1e 15 cm -2 .

9. The preparation method according to claim 5, characterized in that: The temperature of the first heat treatment process is greater than the temperature of the second heat treatment process.

10. The preparation method according to claim 9, characterized in that: The temperature of the second heat treatment process is 500°C to 700°C.

11. The preparation method according to claim 5, characterized in that: The first ionic material includes aluminum ions.

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