Super junction device and forming method thereof

Abstract

The invention provides a super junction device and a forming method thereof, and the super junction device comprises a substrate which comprises a first surface; a deep trench located in the substrate from the first surface; the insulating layer is positioned on the surface of the side wall of the deep groove; the deep trench is located in the substrate, the doped column is located in the deep trench, first doped ions are arranged in the doped column, the concentration of the first doped ions in the doped column in the direction perpendicular to the surface of the substrate and the width of the deep trench are in a self-adaptive matching relation, and the concentration of the first doped ions in the doped column in the direction perpendicular to the surface of the substrate and the width of the deep trench are in a self-adaptive matching relation. The doped column comprises a first polycrystalline silicon layer and a second polycrystalline silicon layer, wherein the first polycrystalline silicon layer is positioned on the surface of the insulating layer and the bottom surface of the deep trench, and the first doped ions are arranged in the first polycrystalline silicon layer; the second polycrystalline silicon layer is located on the surface of the first polycrystalline silicon layer, and part of the first doped ions in the first polycrystalline silicon layer are diffused to the second polycrystalline silicon layer; the breakdown voltage of the super junction device is effectively improved, possibility is provided for further reduction of the size of a subsequent device, and the super junction device has a wide application range.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a super junction device and a method for forming the same. Background Art

[0002] The principle of voltage resistance of power devices is to dope the drift region of the device with low doping, so that the device can produce a large depletion region at high voltage to achieve the voltage resistance effect. Because vertical devices have thicker drift regions, they are the better choice in high-voltage applications.

[0003] Super junction devices combine the advantages of VDMOS's low loss during switching and IGBT's low loss in the on state, and have been widely used due to their excellent performance.

[0004] However, the performance of existing superjunction devices still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a super junction device and a method for forming the same, which effectively improves the breakdown voltage of the super junction device and provides the possibility for further reduction of the size of subsequent devices, and has a wider range of applications.

[0006] To solve the above problems, the present invention provides a super junction device, comprising: a substrate, the substrate comprising a first surface; a deep trench located in the substrate from the first surface; an insulating layer located on the sidewall surface of the deep trench; a doped column located in the deep trench, the doped column having a first doped ion, and the concentration of the first doped ion in the doped column in a direction perpendicular to the surface of the substrate is adaptively matched to the width of the deep trench, wherein the doped column comprises: a first polysilicon layer located on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer having the first doped ion; a second polysilicon layer located on the surface of the first polysilicon layer, and part of the first doped ion in the first polysilicon layer diffuses to the second polysilicon layer.

[0007] Optionally, the concentration of the first doping ions in the doping column is uniformly distributed in a direction parallel to the surface of the substrate.

[0008] Optionally, a concentration of the first doping ions in the doping column in a direction perpendicular to the substrate surface is inversely correlated with a width of the deep trench.

[0009] Optionally, the substrate further includes a second surface opposite to the first surface, and the width of the deep trench gradually decreases from the first surface to the second surface.

[0010] Optionally, it also includes: a body region located on both sides of the doped column; a gate trench located in part of the doped column; a trench gate structure located in the gate trench; a source region located in the body region on both sides of the trench gate structure; and a drain region located in the substrate on the second surface.

[0011] A method for forming a super junction device comprises the following steps: providing a substrate, the substrate comprising a first surface; etching the substrate from the first surface to form a deep trench in the substrate; forming an insulating layer on the sidewall surface of the deep trench; forming a first polysilicon layer on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer having first doping ions; forming a second polysilicon layer on the surface of the first polysilicon layer, the second polysilicon layer filling the deep trench; after forming the second polysilicon layer, performing an annealing treatment to diffuse part of the first doping ions into the second polysilicon layer to form a doping column in the deep trench, the concentration of the first doping ions in the doping column being adaptively matched to the width of the deep trench in a direction perpendicular to the substrate surface.

[0012] Optionally, the concentration of the first doping ions in the doping column is uniformly distributed in a direction parallel to the surface of the substrate.

[0013] Optionally, a concentration of the first doping ions in the doping column in a direction perpendicular to the substrate surface is inversely correlated with a width of the deep trench.

[0014] Optionally, the substrate further includes a second surface opposite to the first surface, and the width of the deep trench gradually decreases from the first surface to the second surface.

[0015] Optionally, the material of the insulating layer includes one or a combination of silicon oxide, silicon nitride, and silicon carbide.

[0016] Optionally, the substrate has second doping ions in it, and the type of the first doping ions is opposite to the type of the second doping ions.

[0017] Optionally, a concentration of the second doping ions in the doping column in a direction perpendicular to the substrate surface is inversely correlated with a width of the deep trench.

[0018] Optionally, the method for forming the insulating layer on the side wall surface of the deep trench includes: forming an initial insulating layer on the side wall and bottom surface of the deep trench; etching and removing the initial insulating layer on the bottom surface of the deep trench to expose the substrate surface at the bottom of the deep trench, thereby forming the insulating layer.

[0019] Optionally, after forming the doped column, the method further includes: forming a body region in the substrate on both sides of the doped column from the first surface, wherein the depth of the body region is smaller than the depth of the doped column.

[0020] Optionally, after forming the doped column, it also includes: etching the doped column with a partial thickness from the first surface, forming a gate trench in the doped column, forming a trench gate structure in the gate trench, the trench gate structure including forming a gate dielectric layer on the side wall surface and the bottom surface of the gate trench; forming a gate layer on the surface of the gate dielectric layer, the gate layer fills the gate trench, and the depth of the gate trench is greater than the depth of the body region.

[0021] Optionally, the method further includes: forming a source region in the body region on both sides of the trench gate structure; and forming a drain region in the substrate from the second surface, wherein the second surface exposes a top surface of the drain region.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the super junction device of the present invention, a deep trench is located in the substrate from the first surface of the substrate, a doped column is located in the deep trench, a first doped ion is contained in the doped column, a concentration of the first doped ion in the doped column in a direction perpendicular to the substrate surface is in an adaptive matching relationship with a width of the deep trench, the doped column comprises a first polysilicon layer located on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer has the first doped ion, a second polysilicon layer located on the surface of the first polysilicon layer, the second polysilicon layer fills the deep trench, part of the first doped ion in the first polysilicon layer diffuses into the second polysilicon layer to form a doped column with the first doped ion; the concentration of the first doped ion in the doped column is in an adaptive matching relationship with the width of the deep trench, that is, the width of the deep trench is large, and the concentration of the first doped ion in the corresponding doped column is small; the width of the deep trench is small, and the concentration of the first doped ion in the corresponding doped column is large, which reduces the difficulty of matching the doped column in the super junction device, increases the process window, and also provides feasibility for the continued optimization of the breakdown voltage (BV) and the continuous reduction of the size of the super junction device in the future, and has a wider range of application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 6 is a structural schematic diagram of a formation process of a super junction device according to an embodiment of the present invention;

[0025] Figure 7 is a schematic diagram of doping distribution in one embodiment of the present invention;

[0026] Figure 8 FIG. 4 is a schematic diagram showing the relationship between gate voltage and drain current in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The electrical performance of superjunction devices in the prior art still needs to be improved.

[0028] Traditional superjunction devices require deep trenches to be dug on an N-type substrate and filled with in-situ doped P-type columns using epitaxy. The N-type substrate and P-type doped columns are matched and depleted in the vertical direction of the silicon wafer to achieve a very high breakdown voltage (BV) with a very small lateral size.

[0029] The inventors found that due to the poor filling ability of the single-crystal silicon epitaxial layer, conventional superjunction devices are difficult to perfectly fill in deep and narrow trenches, which correspondingly limits the continued increase in the trench depth and the potential possibility of further improving the breakdown voltage (BV); In addition, the trench needs to be made into an inverted trapezoid to meet the filling feasibility of the single-crystal silicon epitaxial layer, but the inverted trapezoidal morphology makes the P-type doped column at the top of the trench wide and the P-type doped column at the bottom narrow. The total amount of P-type impurities contained in doped columns of different widths, that is, at different depths in the trench is different: the top trench is wide, with more P-type impurities, while the adjacent N-type area is narrow and has fewer N-type impurities; the bottom is the opposite, with fewer P-type impurities and more adjacent N-type impurities. It is impossible to achieve perfect matching and depletion of N-type and P-type ions from the top to the bottom of the trench at the same time, which ultimately leads to a device breakdown voltage (BV) lower than expected; if the trench is made straight and the sidewalls have no angles, it is easy for N-type and P-type ions to match, but single-crystal silicon epitaxy will not be able to achieve seamless filling; after the P-type doped column is formed, there is still a large amount of thermal budget that cannot be omitted, which leads to lateral diffusion of ions in the doped column, compressing the width of the current path in the N-type region, and ultimately reducing the current density.

[0030] The inventor has found through research that after forming a deep trench in the substrate, an insulating layer is formed on the sidewall of the deep trench, a first polysilicon layer is formed on the bottom surface of the deep trench and the surface of the insulating layer, the first polysilicon layer has first doping ions, a second polysilicon layer is formed on the surface of the first polysilicon layer, the second polysilicon layer fills the deep trench, part of the first doping ions in the first polysilicon layer diffuses into the second polysilicon layer, forming a doped column with the first doping ions; firstly, an insulating layer is formed as a diffusion stop layer, and an opening of the insulating layer is left at the bottom of the deep trench. The insulating layer can suppress the diffusion of the first doping ions in the first polysilicon layer filled subsequently, while not affecting the charge balance between the subsequent doping column and the substrate. Therefore, the filling cost and difficulty of the doped pillar can be reduced, and the on-resistance of the device can be further reduced; at the same time, a first polysilicon layer is deposited on the sidewall and bottom of the deep trench, wherein the first polysilicon layer has a first doped ion with a high doping concentration, and then the non-doped intrinsic second polysilicon layer is filled inside the deep trench, and annealing is performed to make the first doped ion diffuse uniformly in the deep trench laterally (parallel to the surface direction of the substrate), and form a concentration gradient in the vertical direction (perpendicular to the surface direction of the substrate), forming an adaptive doping concentration relative to different deep trench widths. This formation method will greatly reduce the difficulty of matching the doped pillar of the super junction device, increase the process window, and also provide feasibility for the continued optimization of the breakdown voltage (BV) of the super junction device and the continuous reduction of the pitch size in the future.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] First, please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a first surface 100a.

[0033] In this embodiment, the substrate 100 has second doping ions therein, and the second doping ions are N-type ions.

[0034] In this embodiment, the material of the substrate 100 includes one or a combination of some semiconductor materials such as silicon, silicon germanium, germanium, etc.

[0035] Please continue to refer to Figure 1 , the substrate 100 is etched from the first surface 100 a to form a deep trench 102 in the substrate 100 .

[0036] In this embodiment, the method for forming the deep trench 102 includes: forming a hard mask layer (not shown in the figure) on the surface of the substrate 100, etching the substrate 100 using the hard mask layer as a mask to form the deep trench 102; and then removing the hard mask layer.

[0037] In this embodiment, the substrate 100 further includes a second surface 100 b opposite to the first surface 100 a , and the width d of the deep trench 102 gradually decreases from the first surface 100 a to the second surface 100 b .

[0038] Please continue to refer to Figure 1 , an initial insulating layer 101 is formed on the sidewalls and bottom surfaces of the deep trench 102 .

[0039] In this embodiment, the initial insulating layer 101 is formed by an oxidation process.

[0040] In some embodiments, the initial insulating layer may be formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like.

[0041] Please refer to Figure 2 , the initial insulating layer 101 on the bottom surface of the deep trench 102 is etched away until the surface of the substrate 100 at the bottom of the deep trench 102 is exposed, so as to form the insulating layer 103 .

[0042] In this embodiment, the initial insulating layer 101 at the bottom of the deep trench 102 is exposed through an etching process to form a channel for carriers to prevent excessive voltage at the bottom of the deep trench 102 from causing breakdown.

[0043] In this embodiment, the material of the insulating layer 103 is silicon oxide.

[0044] In some embodiments, the material of the insulating layer 103 includes one or a combination of silicon oxide, silicon nitride, and silicon carbide.

[0045] Please refer to Figure 3 A first polysilicon layer 104 is formed on the surface of the insulating layer 103 and the bottom surface of the deep trench 102 , and the first polysilicon layer 104 has first doping ions.

[0046] In this embodiment, the first doping ions are P-type ions.

[0047] In this embodiment, the first doping ion is boron.

[0048] In this embodiment, a high concentration of the first doping ions is formed in the first polysilicon layer 104 , wherein the specific doping concentration is adjusted according to application requirements.

[0049] In this embodiment, an undoped first polysilicon layer is formed first, and then the first doping ions are in-situ doped to form the first polysilicon layer 104 having the first doping ions.

[0050] Please refer to Figure 4 , a second polysilicon layer 105 is formed on the surface of the first polysilicon layer 104 , and the second polysilicon layer 105 completely fills the deep trench 102 .

[0051] In this embodiment, the second polysilicon layer 105 is not doped with any type of ions.

[0052] Please refer to Figure 5 , an annealing treatment is performed, and part of the first doping ions are diffused into the second polysilicon layer 105 to form a doping column 106 in the deep trench 102.

[0053] In this embodiment, the concentration of the first doping ions in the doping column 106 and the width d of the deep trench 102 are in an adaptive matching relationship in a direction perpendicular to the surface of the substrate 100 .

[0054] Specifically, the concentration of the second doping ions in the doping column 106 in the direction Y perpendicular to the surface of the substrate 100 is inversely correlated with the width d of the deep trench 102, that is, the larger the width d of the deep trench 102, the smaller the concentration of the first doping ions in the corresponding doping column 106; the smaller the width d of the deep trench 102, the larger the concentration of the first doping ions in the corresponding doping column 106.

[0055] In this embodiment, an insulating layer 103 is first formed as a diffusion stop layer, and an opening of the insulating layer 103 is left at the bottom of the deep trench 102. The insulating layer 103 can inhibit the diffusion of the first doping ions in the first polysilicon layer 104 filled subsequently, while not affecting the charge balance between the subsequent doping column and the substrate 100. Therefore, the filling cost and difficulty of the doping column 106 can be reduced, and the on-resistance of the device can be further reduced; at the same time, a first polysilicon layer 104 is wrapped and deposited on the sidewall and bottom of the deep trench 102, wherein the first polysilicon layer 104 has a high doping concentration of the first doping ions, and then the non-doped intrinsic second polysilicon layer 105 is filled inside the deep trench 102, and annealing is performed to make the first doping ions diffuse uniformly in the deep trench in the horizontal direction (parallel to the surface direction X of the substrate), and form a concentration gradient in the vertical direction (vertical to the surface direction Y of the substrate), forming an adaptive doping concentration relative to different widths of the deep trench 102. This formation method will greatly reduce the difficulty of matching the doping pillars of the super junction device, increase the process window, and also provide feasibility for the continued optimization of the breakdown voltage (BV) of the super junction device and the continuous reduction of the pitch size in the future.

[0056] In this embodiment, the concentration of the first doping ions in the doping column 106 is uniformly distributed in a direction X parallel to the surface of the substrate 100 .

[0057] Please refer to Figure 6 A body region 107 is formed in the substrate 100 on both sides of the doped column 106 from the first surface 100 a , and a depth of the body region 107 is less than a depth of the doped column 106 .

[0058] Please continue to refer to Figure 6 , the first surface 100a is etched to a partial thickness of the doped column 106, a gate trench (not marked in the figure) is formed in the doped column 106, and a trench gate structure 108 is formed in the gate trench (not marked in the figure), and the trench gate structure 108 includes a gate dielectric layer 108a formed on the sidewall surface and the bottom surface of the gate trench (not marked in the figure); a gate layer 108b is formed on the surface of the gate dielectric layer 108a, and the gate layer 108b fills the gate trench (not marked in the figure), and the depth of the gate trench (not marked in the figure) is greater than the depth of the body region 107.

[0059] Please continue to refer to Figure 6, forming a source region 109 in the body region 107 on both sides of the trench gate structure 108 ; forming a drain region 110 in the substrate 100 from the second surface 100 b , and the second surface 100 b exposes the top surface of the drain region 110 .

[0060] Correspondingly, the present invention also provides a super junction device, comprising: a substrate 100, the substrate 100 comprising a first surface 100a; a deep trench 102 located in the substrate 100 from the first surface 100a; an insulating layer 103 located on the sidewall surface of the deep trench 102; a doping column 106 located in the deep trench 102, the doping column 106 having a first doping ion, the concentration of the first doping ion in the doping column 106 in a direction perpendicular to the surface of the substrate 100 is in an adaptive matching relationship with the width d of the deep trench 102, wherein the doping column 106 comprises: a first polysilicon layer 104 located on the surface of the insulating layer 103 and the bottom surface of the deep trench 102, the first polysilicon layer 104 having a first doping ion; a second polysilicon layer 105 located on the surface of the first polysilicon layer 104, a portion of the first doping ions in the first polysilicon layer 104 diffused into the second polysilicon layer 105.

[0061] In this embodiment, the concentration of the first doping ions in the doping column 106 is uniformly distributed in a direction parallel to the surface of the substrate 100 .

[0062] In this embodiment, the concentration of the first doping ions in the doping column 106 is inversely correlated with the width d of the deep trench 102 in a direction perpendicular to the surface of the substrate 100 .

[0063] In this embodiment, the substrate 100 further includes a second surface 100 b opposite to the first surface 100 a , and the width d of the deep trench 102 gradually decreases from the first surface 100 a to the second surface 100 b .

[0064] In this embodiment, it also includes: a body region 107 located on both sides of the doped column 106; a gate trench (not marked in the figure) located in part of the doped column 106; a trench gate structure 108 located in the gate trench (not marked in the figure); a source region 109 located in the body region 107 on both sides of the trench gate structure 108; and a drain region 110 located in the substrate 100 on the second surface 100b.

[0065] In the present embodiment, the concentration of the first doping ion in the doping column 106 is adaptively matched to the width d of the deep trench 102, that is, the larger the width d of the deep trench 102, the smaller the concentration of the first doping ion in the corresponding doping column 106; the smaller the width d of the deep trench 102, the larger the concentration of the first doping ion in the corresponding doping column 106, thereby reducing the difficulty of matching the doping column 106 in the super junction device, increasing the process window, and providing feasibility for the continued optimization of the breakdown voltage (BV) and the continuous reduction of the size of the super junction device in the future, and having a wider range of applications.

[0066] Please refer to Figure 7 The insulating layer prevents the diffusion of the first doping ions, so that the N-type drift region of the trench gate structure of the super junction device of this embodiment is wider.

[0067] Please refer to Figure 8 , the super junction device of this embodiment can greatly reduce the Rsp of the device.

[0068] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A super junction device, characterized in that: include: a substrate, the substrate comprising a first surface; a deep trench in the substrate from the first surface; an insulating layer located on the sidewall surface of the deep trench; A doped column located in the deep trench, wherein the doped column has a first doped ion, and the concentration of the first doped ion in the doped column in a direction perpendicular to the substrate surface is adaptively matched to the width of the deep trench, wherein the doped column includes: a first polysilicon layer located on the surface of the insulating layer and the bottom surface of the deep trench, wherein the first polysilicon layer has the first doped ion; and a second polysilicon layer located on the surface of the first polysilicon layer, wherein part of the first doped ion in the first polysilicon layer diffuses to the second polysilicon layer.

2. The super junction device according to claim 1, characterized in that: The concentration of the first doping ions in the doping column is uniformly distributed in a direction parallel to the surface of the substrate.

3. The super junction device according to claim 1, characterized in that: The concentration of the first doping ions in the doping column in a direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

4. The super junction device according to claim 1, characterized in that: The substrate further includes a second surface opposite to the first surface, and the width of the deep trench gradually decreases from the first surface to the second surface.

5. The super junction device according to claim 4, characterized in that: Also includes: A body region located on both sides of the doped column; a gate trench located in part of the doped column; a trench gate structure located in the gate trench; A source region located in the body region at both sides of the trench gate structure; and a drain region located in the substrate on the second surface.

6. A method for forming a super junction device, characterized in that: Includes steps: Providing a substrate, the substrate comprising a first surface; Etching the substrate from the first surface to form a deep trench in the substrate; forming an insulating layer on the sidewall surface of the deep trench; forming a first polysilicon layer on the surface of the insulating layer and the bottom surface of the deep trench, wherein the first polysilicon layer has first doping ions; forming a second polysilicon layer on the surface of the first polysilicon layer, wherein the second polysilicon layer completely fills the deep trench; After forming the second polysilicon layer, annealing treatment is performed, and part of the first doping ions diffuse into the second polysilicon layer to form doped columns in the deep trenches. The concentration of the first doping ions in the doped columns in a direction perpendicular to the substrate surface is adaptively matched to the width of the deep trenches.

7. The method for forming a super junction device according to claim 6, wherein: The concentration of the first doping ions in the doping column is uniformly distributed in a direction parallel to the surface of the substrate.

8. The method for forming a super junction device according to claim 6, wherein: The concentration of the first doping ions in the doping column in a direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

9. The method for forming a super junction device according to claim 6, wherein: The substrate further includes a second surface opposite to the first surface, and the width of the deep trench gradually decreases from the first surface to the second surface.

10. The method for forming a super junction device according to claim 6, characterized in that: The material of the insulating layer includes one or a combination of silicon oxide, silicon nitride and silicon carbide.

11. The method for forming a super junction device according to claim 6, characterized in that: The substrate has second doping ions therein, and the type of the first doping ions is opposite to the type of the second doping ions.

12. The method for forming a super junction device according to claim 11, characterized in that: The concentration of the second doping ions in the doping column in a direction perpendicular to the substrate surface is inversely correlated with the width of the deep trench.

13. The method for forming a super junction device according to claim 6, characterized in that: The method for forming the insulating layer on the sidewall surface of the deep trench comprises: forming an initial insulating layer on the sidewall and bottom surface of the deep trench; etching and removing the initial insulating layer on the bottom surface of the deep trench to expose the substrate surface at the bottom of the deep trench to form the insulating layer.

14. The method for forming a super junction device according to claim 9, characterized in that: After forming the doped column, the method further includes: forming body regions in the substrate at both sides of the doped column from the first surface, wherein the depth of the body regions is smaller than the depth of the doped column.

15. The method for forming a super junction device according to claim 14, characterized in that: After forming the doped column, it also includes: etching a portion of the thickness of the doped column from the first surface, forming a gate trench in the doped column, forming a trench gate structure in the gate trench, the trench gate structure including forming a gate dielectric layer on the side wall surface and the bottom surface of the gate trench; forming a gate layer on the surface of the gate dielectric layer, the gate layer fills the gate trench, and the depth of the gate trench is greater than the depth of the body region.

16. The method for forming a super junction device according to claim 15, characterized in that: Also includes: A source region is formed in the body region at both sides of the trench gate structure; a drain region is formed in the substrate from the second surface, and the second surface exposes the top surface of the drain region.

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