Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first conductive type drift region, a source region and a source adaptive region. Wherein the source region is located in the first conductivity type drift region. The source region includes a second conductive type well region and a first conductive type source region. The first conductive type source region is located in the second conductive type well region. The source electrode self-adaptive region is located in the first conductive type source region, and the source electrode self-adaptive region is further adjacent to the second conductive type well region to form a source electrode self-adaptive resistor, so that the short-circuit current flowing through the first conductive type source region is limited. The source self-adaptive resistor in the semiconductor device can play a good role in limiting short-circuit current when the device is in a short-circuit working condition, the stability of the device is improved, and the short-circuit current tolerance time and the reliability of the device are improved. The manufacturing method is simple in step and low in cost.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor devices and manufacturing technology, and relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In terms of material properties, the critical breakdown electric field of SiC is much higher than that of Si. For example, the critical breakdown electric field of 4H-SiC is 10 times that of silicon Si. This means that under the same drift region width conditions, SiC devices can withstand higher breakdown voltages and greater current densities than Si power devices. In addition, the bandgap width and thermal conductivity of SiC are 3 times that of Si, respectively. These properties make SiC very suitable for use in high-frequency, high-voltage and high-temperature environments. However, the current SiC vertical double-diffused metal oxide semiconductor field effect transistor (Vertical Double-diffused Metal Oxide Semiconductor, VDMOS) chips are prone to failure under extreme short-circuit conditions due to their small area and high current density.

[0003] In the related technology, a ballast resistor can be added to the source region of the device to limit the short-circuit current when the device is in a short-circuit condition through the resistor thermal effect. For example, a metal-embedded source resistor with a strong positive temperature coefficient is set in the source region. When a large short-circuit current passes through the source resistor, the source resistor senses the high temperature and its resistance value increases significantly, thereby reducing the short-circuit peak current and further improving the short-circuit withstand time.

[0004] Although the design of the source resistor can limit the short-circuit current to a certain extent, its limiting effect on the short-circuit current is temperature sensitive. Under short-circuit conditions, the increase in the resistance of the source resistor may be delayed, that is, the source resistor cannot sense the change in the current in the device in real time and adjust its resistance in time, resulting in the instantaneous current still exceeding the safe range. Therefore, the above-mentioned method of increasing the resistance of the source by relying on the metal thermal effect is not sensitive enough to the regulation of the short-circuit current, and cannot accurately regulate the source resistance, and the improvement of the short-circuit current capacity of the device is insufficient.

[0005] Therefore, how to provide a semiconductor device and a method for manufacturing the same to effectively improve the short-circuit current capability of the semiconductor device and increase the service life and reliability of the semiconductor device has become an important technical problem that needs to be urgently solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, so as to solve the problem that the short-circuit current capability and reliability of the semiconductor device in the prior art need to be improved.

[0008] To achieve the above objectives and other related objectives, in a first aspect, a semiconductor device is provided, comprising:

[0009] a first conductivity type drift region;

[0010] A source region, located in the first conductive type drift region, the source region comprising a second conductive type well region and a first conductive type source region, the first conductive type source region being located in the second conductive type well region;

[0011] A source adaptive region is located in the first conductive type source region, and the source adaptive region is also adjacent to the second conductive type well region; wherein,

[0012] The source adaptive region and the second conductive type well region form a source adaptive resistor to limit a short-circuit current flowing through the first conductive type source region.

[0013] Optionally, the source adaptive region includes a first conductivity type doping region and a second conductivity type doping region, the second conductivity type doping region is located in the first conductivity type source region, and the first conductivity type doping region is located between the second conductivity type doping region and the second conductivity type well region.

[0014] Optionally, a doping concentration of the first conductive type doping region is less than a doping concentration of the first conductive type source region.

[0015] Optionally, the doping concentration range of the first conductive type doping region is 8e15 cm -3 ~3e16 cm -3 The doping concentration range of the second conductive type doping region is 8e16 cm -3 ~3e17 cm -3 The doping concentration range of the second conductivity type well region is 8e17 cm -3 ~3e18 cm -3 .

[0016] Optionally, a ratio between a thickness of the first conductive type doping region and a thickness of the second conductive type doping region is in a range of 1.5 to 2.5.

[0017] Optionally, a ratio between a width of the first conductive type source region and a width of the source adaptive region is in a range of 2.6 to 3.2.

[0018] Optionally, the source adaptive region separates the first conductive type source region into a first sub-source region and a second sub-source region on a current flow path, and the source adaptive resistor is used to limit a short-circuit current flowing between the first sub-source region and the second sub-source region.

[0019] Optionally, the semiconductor device further includes a source metal, wherein the source metal is located above the first conductivity type drift region, and the source metal is connected to a portion of the first conductivity type source region and the second conductivity type doped region.

[0020] Optionally, the semiconductor device further includes a gate, and the gate includes at least one of a planar gate and a trench gate.

[0021] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0022] forming a first conductivity type drift region;

[0023] forming a source region in the first conductive type drift region, the source region comprising a second conductive type well region and a first conductive type source region, the first conductive type source region being located in the second conductive type well region;

[0024] A source adaptive region is formed in the first conductive type source region, and the source adaptive region is also adjacent to the second conductive type well region; wherein the source adaptive region and the second conductive type well region constitute a source adaptive resistor to limit the short-circuit current flowing through the first conductive type source region.

[0025] As described above, the semiconductor device of the present application forms a source adaptive region in the first conductive type source region, so that the source adaptive region and the second conductive type well region constitute a source adaptive resistor to limit the short-circuit current flowing through the first conductive type source region. The source adaptive resistor can play a good limiting role on the short-circuit current when the device is in a short-circuit condition, which not only improves the stability of the semiconductor device under short-circuit conditions and prolongs the short-circuit current tolerance time of the device, but also effectively improves the reliability and durability of the circuit while maintaining the high efficiency of the device, which helps to expand the application scenarios of semiconductor devices. The method for manufacturing a semiconductor device of the present application forms a source adaptive region in the first conductive type source region, so that the source adaptive region and the second conductive type well region constitute a source adaptive resistor, so that the short-circuit current capacity of the semiconductor device is effectively improved. The manufacturing method has simple steps, low cost, and is easy to achieve large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A schematic diagram showing a structure of a semiconductor device provided by an embodiment of the present application is shown;

[0027] Figure 2 Display as Figure 1 A magnified schematic diagram of the middle area A;

[0028] Figure 3 Another schematic diagram showing the structure of a semiconductor device provided by an embodiment of the present application;

[0029] Figure 4 A flowchart showing the steps of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0030] Figure 5 A schematic diagram showing a structure after an initial source region is formed in a second conductivity type well region in a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0031] Figure 6 A schematic diagram showing a structure after a second conductive type doping region is formed in an initial source region in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0032] Figure 7 Shown is a structural schematic diagram after an adaptive resistance region is formed in the method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0033] Description of reference numerals:

[0034] 10-first conductivity type drift region, 11-JFET region, 20-source region, 21-second conductivity type well region, 220-initial source region, 22-first conductivity type source region, 221-first sub-source region, 222-second sub-source region, 23-second conductivity type contact region, 30-source adaptive region, 31-first conductivity type doping region, 32-second conductivity type doping region, 40-gate, 41-gate dielectric, 42-gate electrode, 50-interlayer dielectric layer, 60-source metal, 70-substrate, A-region, S1~S3-steps. DETAILED DESCRIPTION

[0035] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0036] In view of the technical problem of insufficient regulation sensitivity of the metal embedded source resistor mentioned in the background technology, an attempt is made to use an electrically sensitive source resistor to replace the thermally sensitive source resistor, which can improve the timeliness of adjustment to a certain extent. For example, an N- region is embedded in the N+ source region as a resistance region. However, since the N- region has a comparable resistance under short-circuit conditions, the doping concentration of the N- region needs to be very low, even close to an intrinsic semiconductor, and it is impossible to flexibly adjust the resistance required for short circuits of different devices by changing the doping of the device. That is, since the N- region adjusts the source resistance based on its doping concentration (or resistivity), and the resistance change that can be provided by its N- region as a resistance region is limited, resulting in poor adjustability of the source resistance. Therefore, this solution also cannot effectively improve the short-circuit current capability of semiconductor devices.

[0037] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0038] The present application embodiment provides a semiconductor device. Figure 1 , Figure 1 Schematic diagram of the structure of the semiconductor device is shown. More specifically, Figure 1 The schematic diagram of the cross-sectional structure of the cell structure in the semiconductor device in the height direction is shown in FIG. 1 , and the cell structure is symmetrical in the width direction. The semiconductor device includes a first conductive type drift region 10 , a source region 20 and a source adaptive region 30 .

[0039] Specifically, Figure 1 As shown, the source region 20 is located in the first conductive type drift region 10. The source region 20 includes a second conductive type well region 21 and a first conductive type source region 22. The first conductive type source region 22 is located in the second conductive type well region 21. The source adaptive region 30 is located in the first conductive type source region 22. The source adaptive region 30 is also adjacent to the second conductive type well region 21. The source adaptive region 30 and the second conductive type well region 21 constitute a source adaptive resistor to limit the short-circuit current flowing through the first conductive type source region 22.

[0040] In the embodiment of the present application, the source adaptive region 30 is arranged in the first conductive type source region 22, and the source adaptive region 30 is adjacent to the second conductive type well region 21 to form a source adaptive resistor. When the source adaptive resistor senses the change of the current flowing through the first conductive type source region 22, it adaptively adjusts its own resistance value, thereby adjusting the size of the current path of the current in the first conductive type source region 22 (which can be regarded as the area of ​​the area in the first conductive type source region 22 that allows the current to pass). So that under the short-circuit condition, when the short-circuit large current flows through the first conductive type source region 22, the source adaptive resistor can instantly increase the resistance value to reduce the current path and limit the short-circuit peak current. Thereby extending the short-circuit current tolerance time of the device and improving the stability and reliability of the device. Since the source adaptive resistor is electrically sensitive (for example, the resistance value of the resistor is adjusted based on the change of the current size), compared with the thermally sensitive resistor, the reaction speed and sensitivity are significantly improved, which is suitable for practical applications. The short-circuit current includes the current flowing between the source and drain of the semiconductor device under a short-circuit condition. The source adaptive resistor in this article is used to limit the size of the short-circuit current flowing through the first conductive type source region 22.

[0041] It should be noted that there are two widely existing short-circuit conditions in the power device industry. The first short-circuit condition is that the device is short-circuited before turning on (i.e., hard switch failure), and the second short-circuit condition is that the device is short-circuited after turning on (i.e., load short-circuit). In these two short-circuit conditions, the short-circuit voltage of the hard switch failure is large, and the current density is large, so that the electrothermal stress generated during the short-circuit process is large, and the test for the device is more severe. Therefore, if the short-circuit tolerance of the device is improved under the short-circuit working conditions of the hard switch failure, the short-circuit tolerance of the device under general short-circuit conditions will also be improved. The short-circuit condition targeted by the adaptive source resistance in the power device provided in the embodiment of the present application is a hard switch failure. During the hard switch failure, the gate voltage is turned on, the power device is short-circuited, and the bus voltage is all actually on the power device, causing the current to rise rapidly. Since the JFET region in the source region is saturated before the channel current, the short-circuit peak current is suppressed, and the short-circuit current tolerance time is extended.

[0042] In an optional embodiment, the source adaptive region 30 includes a first conductive type doping region 31 and a second conductive type doping region 32, the second conductive type doping region 32 is located in the first conductive type source region 22, and the first conductive type doping region 31 is located between the second conductive type doping region 32 and the second conductive type well region 21. That is, the second conductive type doping region 32, the first conductive type doping region 31 and the second conductive type well region 21 are sequentially adjacent to form a JFET structure.

[0043] In the embodiment of the present application, by integrating the source adaptive resistor in the source region 20, the source adaptive resistor is a JFET structure formed by the second conductive type doping region 32, the first conductive type doping region 31 and the second conductive type well region 21 adjacent in sequence. When the short-circuit current passes through the first conductive type doping region 31, due to the increase in the voltage drop of the JFET structure, that is, the voltage between the first conductive type doping region 31 and the second conductive type doping region 32 increases, and the voltage between the first conductive type doping region 31 and the second conductive type well region 21 increases, so that the depletion region between the first conductive type doping region 31 and the second conductive type doping region 32 and the second conductive type well region 21 are all expanded, which is reflected in the narrowing of the current path in the first conductive type doping region 31, limiting the short-circuit peak current (i.e., self-clamping effect). In addition, the resistance of the source adaptive resistor in the normal on-state of the device is relatively small, and will not cause significant loss to the on-current capability of the device. Under the condition of large short-circuit current, its resistance increases rapidly, which has the effect of accurately and timely limiting the short-circuit current. Since the narrowing effect of the source adaptive resistor is directly related to the electrical environment in which it is located (i.e. the electrical sensitivity mentioned above), when the semiconductor device is in a short-circuit state, the source adaptive resistor can quickly and sensitively respond to the change of current and adaptively feedback it as a resistance change. As the short-circuit current increases, the current path in the JFET structure (i.e. the main structure of the first conductive type doping region 31 where the depletion region is not formed, and the area where the current is allowed to pass) will be affected by the voltage at both ends and quickly become narrow, thereby effectively limiting the short-circuit current.

[0044] In an optional embodiment, the doping concentration of the first conductive type doping region 31 is less than the doping concentration of the first conductive type source region 22. The doping concentration of the first conductive type doping region 31 is selected based on the on-resistance and short-circuit limiting capability required by the semiconductor device. For example, when the semiconductor device has strict requirements on the short-circuit limiting capability, the doping concentration of the first conductive type doping region 31 can be designed to be relatively low, so as to provide a larger resistance value under short-circuit conditions.

[0045] Furthermore, the doping concentration range of the first conductive type doping region 31 is 8e15 cm -3 ~3e16 cm -3 (including endpoint values), for example, the doping concentration of the first conductive type doping region 31 may be 9e15 cm -3 , 1e16 cm -3 or 2e16cm -3 The doping concentration of the second conductive type doping region 32 is in the range of 8e16 cm -3 ~3e17 cm -3(including endpoint values), for example, the doping concentration of the second conductive type doping region 32 may be 9e16 cm -3 , 1e17 cm -3 or 2e17cm -3 The doping concentration range of the second conductive type well region 21 is 8e17 cm -3 ~3e18 cm -3 (including endpoint values), for example, the doping concentration of the second conductive type well region 21 may be 9e17 cm -3 , 1e18 cm -3 or 2e18 cm -3 .

[0046] For an alternative embodiment, see Figure 2 , Figure 2 Shows Figure 1 In the enlarged structural diagram of the middle area A, the ratio between the thickness t1 of the first conductive type doping region 31 and the thickness t2 of the second conductive type doping region 32 is in the range of 1.5 to 2.5 (including the endpoint values). The ratio between the thickness t1 of the first conductive type doping region 31 and the thickness t2 of the second conductive type doping region 32 can be 1.8, 2.0 or 2.2. In this article, "width" refers to the dimension in the cell width direction (that is, the arrangement direction of multiple cells), and "thickness" refers to the dimension perpendicular to the cell width direction. To avoid ambiguity, the thickness of the various doping regions mentioned in this article can be regarded as the doping depth of the corresponding structure to a certain extent. Since the current will pass through the first conductive type doping region 31 in the source adaptive resistor under normal working conditions and short-circuit conditions, in order to prevent the source adaptive resistor from affecting the conduction capability of the device under normal conditions, the thickness t2 of the first conductive type doping region 31 is set as high as possible in a limited area. At the same time, in order to enable the source adaptive resistor to play a good role in limiting the short-circuit current, the thickness t1 of the second conductive type doping region 32 needs to be set in coordination to ensure that the width of the depletion region between the second conductive type doping region 32 and the first conductive type doping region 31 can be adjusted.

[0047] Further, the thickness t1 of the first conductive type doping region 31 ranges from 0.1 μm to 0.3 μm (including the endpoint value). For example, the thickness t1 of the first conductive type doping region 31 may be 0.15 μm, 0.2 μm or 0.25 μm. The thickness t2 of the second conductive type doping region 32 ranges from 0.05 μm to 0.15 μm (including the endpoint value). For example, the thickness t2 of the first conductive type doping region 31 may be 0.1 μm. The thickness t1 of the first conductive type doping region 31 and the thickness t2 of the second conductive type doping region 32 are reasonably adjusted on the premise that the on-resistance of the device is basically not affected in the normal conduction state, and the short-circuit current can be effectively limited in the short-circuit state. Correspondingly, the thickness of the first conductive type source region 22 ranges from 0.15 μm to 0.45 μm (including the endpoint value). For example, the thickness of the first conductive type source region 22 may be 0.25 μm, 0.3 μm or 0.35 μm. Similarly, the thickness of the second conductive type well region 21 needs to be reasonably designed to meet the controllability of the source adaptive resistance control current path. For example, the thickness of the second conductive type well region 21 ranges from 0.8 μm to 1.5 μm, so as to ensure that the thickness t3 of the portion of the second conductive type well region 21 located below the first conductive type source region 22 can generate a sufficiently wide depletion region between the first conductive type doped region 31. For example, the thickness of the second conductive type well region 21 can be 1 μm.

[0048] In an optional embodiment, if Figure 2 As shown, the ratio between the width w1 of the first conductive type source region 22 and the width w2 of the source adaptive region 30 is in the range of 2.8 to 3.2 (including the end values). For example, the ratio between the width w1 of the first conductive type source region 22 and the width w2 of the source adaptive region 30 can be 2.8, 2.9 or 3.0.

[0049] Further, the width w1 of the first conductive type source region 22 is in the range of 1.5 μm to 4.5 μm (including the endpoint value), and the width w2 of the source adaptive region 30 is in the range of 0.8 μm to 1.2 μm (including the endpoint value). Accordingly, the width of the first conductive type doping region and the width of the second conductive type doping region are both in the range of 0.8 μm to 1.2 μm (including the endpoint value). For example, the width of the first conductive type source region 22 is 2.9 μm, and the width of the source adaptive region 30 is 1.0 μm.

[0050] For an alternative embodiment, see Figure 1 and Figure 3 ,in, Figure 3Another schematic diagram of the structure of the semiconductor device is shown. The semiconductor device further includes a gate 40, and the gate 40 includes at least one of a planar gate and a trench gate. That is, the semiconductor device can be a planar gate type device (such as Figure 1 as shown) or trench gate devices (as Figure 3 As shown), for example, the semiconductor device may be an insulated gate bipolar transistor (IGBT for short).

[0051] In an optional embodiment, if Figure 1 and Figure 3 As shown, the gate 40 includes a gate dielectric 41 and a gate electrode 42, and the gate dielectric 41 is located between the first conductive type drift region 10 and the gate electrode 42. For example, the gate dielectric 41 covers the second sub-source region 222, and the gate electrode 42 covers at least a portion of the second sub-source region 222. The material of the gate dielectric 41 can be silicon dioxide, and the material of the gate electrode 42 can be polysilicon, and in order to reduce the resistance of the gate electrode 42, the gate electrode 42 can be heavily doped polysilicon. For example, the width of the gate dielectric 41 layer is 3μm, and the thickness of the gate dielectric 41 layer is 45nm.

[0052] In an optional embodiment, if Figure 1 and Figure 3 As shown, the semiconductor device further includes a source metal 60, the source metal 60 is located above the first conductive type drift region 10, and the source metal 60 is connected to a portion of the first conductive type source region 22 and the second conductive type doped region 32. In the case where the source adaptive region 30 separates the first conductive type source region 22 into a first sub-source region 221 and a second sub-source region 222, the source metal 60 is connected to one of the first sub-source region 221 and the second sub-source region 222, and is electrically isolated from the other of the first sub-source region 221 and the second sub-source region 222.

[0053] In an optional embodiment, if Figure 1 and Figure 3As shown, the source adaptive region 30 separates the first conductive type source region 22 into a first sub-source region 221 and a second sub-source region 222 on the current flow path, and the source adaptive resistor is used to limit the short-circuit current flowing between the first sub-source region 221 and the second sub-source region 222. The first sub-source region 221 is electrically connected to the source metal 60, the second sub-source region 222 is electrically isolated from the source metal 60, and the gate 40 covers at least a portion of the second sub-source region 222. When the gate 40 voltage is greater than the threshold voltage, a channel is formed based on the region of the second conductive type well region 21 located between the second sub-source region 222 and the first conductive type drift region 10 to achieve conduction of the semiconductor device. The first conductive type source region 22 is separated into a first sub-source region 221 and a second sub-source region 222 by the source adaptive region 30, so that the current flowing from the source metal 60 to the drain metal (or the current flowing from the drain metal to the source metal 60) in the semiconductor device can only flow through the source adaptive region 30, which can further improve the short-circuit current capability of the device.

[0054] In an optional embodiment, if Figure 1 and Figure 3 As shown, the source region 20 further includes a second conductive type contact region 23, which is located in the second conductive type well region 21 and is adjacent to the first conductive type source region 22. In the case where the first conductive type source region 22 is divided into a first sub-source region 221 and a second sub-source region 222, the second conductive type contact region 23 is adjacent to the first sub-source region 221, and the source metal 60 is also electrically connected to the second conductive type contact region 23. The width of the second conductive type contact region 23 may be equal to or different from the width of the source adaptive region 30, for example, the width of the second conductive type contact region 23 may be 1 μm.

[0055] In an optional embodiment, if Figure 1 and Figure 3 As shown, the thickness range of the first conductive type drift region 10 is 2 to 15 μm (including the endpoint values). For example, the thickness of the first conductive type drift region 10 can be 5 μm, 8 μm or 10 μm. The thickness of the first conductive type drift region 10 is designed based on the application scenario of the semiconductor device. For example, the thickness of the first conductive type drift region 10 is directly related to the withstand voltage level of the semiconductor device. When the semiconductor device is used in applications with higher withstand voltage performance, the thickness of the first conductive type drift region 10 is generally greater than 5 μm. The doping concentration range of the first conductive type drift region 10 is 8e15 cm -3 ~1e16 cm -3(including endpoint values), for example, the doping concentration of the first conductive type drift region 10 may be 9e15 cm -3 .

[0056] In an optional embodiment, if Figure 1 and Figure 3 As shown, the semiconductor device further includes a JFET region 11, the JFET region 11 is located in the first conductive type drift region 10, and the JFET region 11 is located between two adjacent second conductive type well regions 21 in the width direction of the cell. For example, the doping concentration of the JFET region 11 can be 1e17cm -3 Optionally, the surface of the JFET region 11 further forms a surface region, and the doping concentration of the surface region can be 5e16cm -3 .

[0057] In an optional embodiment, if Figure 1 and Figure 3 As shown, the semiconductor device further includes a substrate 70, the substrate 70 is of a first conductivity type, the first conductivity type drift region 10 is located on the substrate 70, and the doping concentration of the substrate 70 is greater than the doping concentration of the first conductivity type drift region 10. The material of the substrate 70 includes at least one of SiC and Si. The thickness of the substrate 70 can be 10 μm.

[0058] In an optional embodiment, the semiconductor device further includes a drain metal (not shown), and the drain metal is located on a side of the substrate 70 away from the first conductivity type drift region 10 .

[0059] In an optional embodiment, the first conductivity type is N-type, and correspondingly, the second conductivity type is P-type. Alternatively, the first conductivity type is P-type, and correspondingly, the second conductivity type is N-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type for example, that is, the semiconductor device in this embodiment includes an N-type drift region, a P-type well region, an N-type source region, an N-type doped region, a P-type doped region, and a P-type contact region, wherein the P-type well region, the N-type doped region, and the P-type doped region constitute the source adaptive resistor.

[0060] It should be noted that the structural parameters such as the width and thickness of the above-mentioned doping regions need to be adjusted based on the size of the cell. For example, in a specific embodiment, the width of a single cell of the semiconductor device is 5.8 μm, the width of the second conductive type well region 21 is 4.4 μm, the width of the first conductive type source region 22 is 2.9 μm, the width of the second conductive type contact region 23 is 1 μm, the width of the region for forming a channel in the second conductive type well region 21 is 0.4 μm, and the width of the JFET region 11 is 1.4 μm.

[0061] The semiconductor device provided in the embodiment of the present application forms a source adaptive region in the first conductive type source region, so that the source adaptive region and the second conductive type well region constitute a source adaptive resistor to limit the short-circuit current flowing through the first conductive type source region. The source adaptive resistor can play a good limiting role on the short-circuit current when the device is in a short-circuit condition. It not only improves the stability of the semiconductor device in the case of a short circuit and prolongs the short-circuit current withstand time (SWCT) of the device, but also can effectively improve the reliability and durability of the circuit while maintaining the high performance of the device (for example, conduction capability), which helps to expand the application scenarios of semiconductor devices (especially silicon carbide devices).

[0062] The present application also provides a method for manufacturing a semiconductor device, which can be used to manufacture the aforementioned semiconductor device or other suitable semiconductor devices. Figure 4 , Figure 4 The process flow chart of the manufacturing method is shown. The manufacturing method comprises the following steps:

[0063] S1: forming a first conductivity type drift region;

[0064] S2: forming a source region in the first conductive type drift region, wherein the source region includes a second conductive type well region and a first conductive type source region, and the first conductive type source region is located in the second conductive type well region;

[0065] S3: forming a source adaptive region in the first conductive type source region, wherein the source adaptive region is also adjacent to the second conductive type well region; wherein the source adaptive region and the second conductive type well region constitute a source adaptive resistor to limit the short-circuit current flowing through the first conductive type source region.

[0066] First, see Figure 5 , perform step S1 to form a first conductive type drift region 10 . For example, provide a substrate 70 , and form the first conductive type drift region 10 on the substrate 70 .

[0067] In an optional embodiment, if Figure 5 As shown, before step S2 and step S3, the method further includes forming the JFET region 11 in the first conductive type drift region 10, wherein the JFET region 11 is located between two adjacent second conductive type well regions 21 in the width direction of the cell.

[0068] Next, see Figures 5 to 7 , performing step S2 and step S3, forming a source region 20 in the first conductive type drift region 10, the source region 20 comprising a second conductive type well region 21 and a first conductive type source region 22, the first conductive type source region 22 being located in the second conductive type well region 21. Forming a source adaptive region 30 in the first conductive type source region 22, the source adaptive region 30 also being adjacent to the second conductive type well region 21; wherein the source adaptive region 30 and the second conductive type well region 21 constitute a source adaptive resistor to limit the current path of the current in the first conductive type source region 22.

[0069] In one embodiment, step S2 and step S3 include the following steps:

[0070] like Figure 5 As shown, a second conductive type well region 21 is formed in the first conductive type drift region 10 .

[0071] An initial source region 220 is formed in the second conductive type well region 21. The initial source region 220 is spaced apart from the second conductive type well region 21 by a preset distance on both sides of the width direction of the cell. Wherein, in the case where the semiconductor device further includes a second conductive type contact region 23, the second conductive type contact region 23 is also formed in a region on one side of the initial source region 220 where the second conductive type well region 21 is located.

[0072] like Figure 6 and Figure 7 As shown, the source adaptive region 30 is formed in the initial source region 220. The source adaptive region 30 is also adjacent to the second conductive type well region 21, and the region of the initial source region 220 that remains after the source adaptive region 30 is formed constitutes the first conductive type source region 22. The first conductive type source region 22 and the second conductive type well region 21 constitute the source region 20.

[0073] In an optional embodiment, the source adaptive region 30 includes a first conductive type doping region 31 and a second conductive type doping region 32, the second conductive type doping region 32 is located in the first conductive type source region 22, and the first conductive type doping region 31 is located between the second conductive type doping region 32 and the second conductive type well region 21.

[0074] In one embodiment, forming the source adaptive region 30 in the initial source region 220 comprises the following steps:

[0075] like Figure 6 As shown, the second conductive type doping region 32 is formed in the initial source region 220. Figure 7 As shown, the first conductive type source region 22 is formed in the peripheral area of ​​the initial source region 220 located in the second conductive type doping region 32. The portion of the initial source region 220 located below the second conductive type doping region 32 constitutes the first conductive type doping region 31. In this embodiment, the doping concentration of the initial source region 220 is the same as the doping concentration of the first conductive type doping region 31, and the second conductive type doping region 32 can be formed by impurity compensation, which only involves one impurity compensation process, and it is easy to ensure the product yield.

[0076] In another embodiment, forming the source adaptive region 30 in the initial source region 220 includes the following steps (not shown):

[0077] The first conductive type doping region 31 is formed in the initial source region 220; the second conductive type doping region 32 is formed above the first conductive type doping region 31; the area of ​​the initial source region 220 other than the first conductive type doping region 31 and the second conductive type doping region 32 constitutes the first conductive type source region 22. In this embodiment, the doping concentration of the initial source region 220 is the same as the doping concentration of the first conductive type source region 22, and the first conductive type doping region 31 and the second conductive type doping region 32 can be formed by impurity compensation. Compared with the previous embodiment, the first conductive type doping region 31 and the second conductive type doping region 32 can be formed by ion implantation based on the same mask, which can save process costs.

[0078] In an optional embodiment, please combine Figure 1 and Figure 3The manufacturing method further includes the steps of forming a gate 40 and a source metal 60. The steps of forming the gate 40 are adjusted based on the type of the gate 40. For example, if the gate 40 is a trench gate, the first conductive type drift region can be etched to form a trench, and then a thermal oxidation or deposition process is performed to form a gate dielectric 41 covering the inner wall of the trench and a portion of the surface of the drift region near the trench, and then a gate electrode 42 is formed, and then an interlayer dielectric layer 50 is formed to cover the gate electrode 42. The interlayer dielectric layer 50 is then etched and the source metal 60 is deposited.

[0079] The method for manufacturing a semiconductor device provided in an embodiment of the present application forms a source adaptive region in a first conductive type source region so that the source adaptive region and a second conductive type well region form a source adaptive resistor, thereby effectively improving the short-circuit current capability of the semiconductor device. The manufacturing method has simple steps, low cost, and is easy to achieve large-scale production.

[0080] In summary, the semiconductor device of the present application forms a source adaptive region in the first conductive type source region, so that the source adaptive region and the second conductive type well region constitute a source adaptive resistor to limit the short-circuit current flowing through the first conductive type source region. The source adaptive resistor can play a good limiting role on the short-circuit current when the device is in a short-circuit condition, which not only improves the stability of the semiconductor device under short-circuit conditions and prolongs the short-circuit current tolerance time of the device, but also effectively improves the reliability and durability of the circuit while maintaining the high efficiency of the device, which helps to expand the application scenarios of semiconductor devices. The method for manufacturing a semiconductor device of the present application forms a source adaptive region in the first conductive type source region, so that the source adaptive region and the second conductive type well region constitute a source adaptive resistor, so that the short-circuit current capacity of the semiconductor device is effectively improved. The manufacturing method has simple steps, low cost, and is easy to achieve large-scale production. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0081] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A semiconductor device, characterized in that: include: a first conductivity type drift region; A source region, located in the first conductive type drift region, the source region comprising a second conductive type well region and a first conductive type source region, the first conductive type source region being located in the second conductive type well region; A source adaptive region is located in the first conductive type source region, and the source adaptive region is also adjacent to the second conductive type well region; wherein, The source adaptive region and the second conductive type well region form a source adaptive resistor to limit a short-circuit current flowing through the first conductive type source region.

2. The semiconductor device according to claim 1, wherein: The source adaptive region includes a first conductive type doping region and a second conductive type doping region, the second conductive type doping region is located in the first conductive type source region, and the first conductive type doping region is located between the second conductive type doping region and the second conductive type well region.

3. The semiconductor device according to claim 2, wherein: The doping concentration of the first conductive type doping region is less than the doping concentration of the first conductive type source region.

4. The semiconductor device according to claim 2, wherein: The doping concentration range of the first conductive type doping region is 8e15 cm -3 ~3e16 cm -3 The doping concentration range of the second conductive type doping region is 8e16 cm -3 ~3e17cm -3 The doping concentration range of the second conductivity type well region is 8e17 cm -3 ~3e18 cm -3 .

5. The semiconductor device according to claim 2, wherein: The ratio of the thickness of the first conductive type doping region to the thickness of the second conductive type doping region is in the range of 1.5 to 2.

5.

6. The semiconductor device according to claim 1, wherein: The ratio of the width of the first conductive type source region to the width of the source adaptive region is in the range of 2.6 to 3.

2.

7. The semiconductor device according to claim 1, wherein: The source adaptive region separates the first conductive type source region into a first sub-source region and a second sub-source region on a current flow path, and the source adaptive resistor is used to limit a short-circuit current flowing between the first sub-source region and the second sub-source region.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a source metal, wherein the source metal is located above the first conductive type drift region and is connected to a portion of the first conductive type source region and the second conductive type doped region.

9. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a gate, and the gate comprises at least one of a planar gate and a trench gate.

10. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: forming a first conductivity type drift region; forming a source region in the first conductive type drift region, the source region comprising a second conductive type well region and a first conductive type source region, the first conductive type source region being located in the second conductive type well region; A source adaptive region is formed in the first conductive type source region, and the source adaptive region is also adjacent to the second conductive type well region; wherein, The source adaptive region and the second conductive type well region form a source adaptive resistor to limit a short-circuit current flowing through the first conductive type source region.

Images