SiC wafer structure back silver defect improvement method and SiC device manufactured by same

Abstract

The invention discloses a method for improving back silver defects of a SiC wafer structure and a SiC device manufactured by the method, and belongs to the technical field of semiconductor device processing. The method comprises the following steps: S1, processing on the front surface of a SiC substrate and forming a front surface process film layer; s2, processing a back ohmic metal layer on the back of the SiC substrate; s3, back-gilding an intermediate metal layer on the surface of the ohmic metal layer; s4, a first silver layer is plated on the surface of the middle metal layer in a low-temperature processing mode; and S5, plating a second silver layer on the surface of the first silver layer in a high-temperature processing manner. In the invention, the second silver layer of the back gold in the high-temperature processing mode is more compact, the resistance to high-temperature test roughening is stronger, but the stress is large; therefore, the rough first silver layer with small stress is processed in a low-temperature processing mode, and the purpose of gradually releasing the stress is achieved. Therefore, the SiC wafer structure after back gold plating does not present macroscopic macroscopic white spot defects in the subsequent electrical performance parameter CP test and wafer reliability test processes.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor device processing, and in particular relates to a method for improving back silver defects of a SiC wafer structure and a SiC device manufactured by the method. Background Art

[0002] At present, with the rise of SiC materials, many silicon-based semiconductor devices are gradually being replaced by SiC devices. For example, traditional silicon-based IGBTs dominate high-voltage and high-current scenarios, but silicon-based IGBTs cannot withstand high-frequency conditions and have high power consumption. SiC has the characteristics of high voltage and high temperature resistance, which allows it to cover the voltage resistance level of silicon-based IGBTs with only simpler MOSFET devices, while avoiding the shortcomings of high energy consumption of silicon-based IGBTs. Under the same environment, SiC-based MOSFETs reduce energy losses by 66% compared to silicon-based IGBTs of the same specifications, mainly due to a significant reduction in switching losses. In addition, in industries such as new energy vehicles, SiC-based devices can be used to drive and control motor inverters, on-board chargers, and fast charging piles; in photovoltaic power generation, photovoltaic inverter manufacturers have currently widely adopted SiC-based power devices to replace silicon-based devices.

[0003] See also Figure 1 As shown, the manufacturing process of the existing SiC-based MOS is as follows:

[0004] (1) Wafer front side process;

[0005] (2) Wafer thinning operation;

[0006] (3) Ohmic metal on the back;

[0007] (4) Back gold process;

[0008] (5) Wafer CP test and reliability test;

[0009] (6) Divide into multiple Dies.

[0010] Although SiC-based power devices have many advantages, they also have some specific defects. For example, when most SiC power devices implement the back-gold process (i.e., the process of depositing metal on the back of the wafer), the bottom back-gold uses a silver (Ag) layer, which has good conductivity and low overall cost; however, due to its more active characteristics, during the subsequent electrical performance parameter CP test and wafer reliability test, due to the influence of high temperature, N2 gas flow and power-on test, the Ag layer becomes rough on the surface and presents white spots visible to the naked eye, and such white spots appear regularly on a single semiconductor chip (Die) on the wafer.

[0011] See also Figure 2As shown, taking the processing of SiC MOS devices as an example, after the wafer back gold process is completed, the subsequent electrical performance parameter CP test and wafer reliability test are carried out; on the back silver layer of the bottom layer of the wafer, corresponding to the source pad area 11 and the drain pad area 12 of each semiconductor chip (Die) 10, white spot defects 100 are regularly formed, and the gate pad area 13 is not seen. This white spot defect will affect the conductive efficiency, reliability and durability of each die. However, the industry currently has no good solution to this white spot defect on the back silver. Summary of the invention

[0012] The purpose of the present invention is to provide a method for improving the back silver defect of SiC wafer structure and a SiC device made therefrom, aiming to solve the white spot defect of the back silver of SiC wafer structure during the processing of SiC device. The present invention is achieved by the following scheme:

[0013] A first aspect of the present invention provides a method for improving back silver defects in a SiC wafer structure, comprising:

[0014] S1, processing and forming a front process film layer on the front side of the SiC substrate;

[0015] S2, processing a back ohmic metal layer on the back side of the SiC substrate;

[0016] S3, a gold-backed intermediate metal layer on the surface of the ohmic metal layer;

[0017] It is characterized by further comprising:

[0018] S4, back-golding the first silver layer on the surface of the intermediate metal layer by low temperature processing;

[0019] S5, back-golding a second silver layer on the surface of the first silver layer by high temperature processing.

[0020] As a preferred technical solution, the low-temperature processing method adopts a sputtering process, and the temperature of the SiC wafer structure is controlled between 100-150°C.

[0021] As a preferred technical solution, the high temperature processing method adopts a sputtering process, and the temperature of the SiC wafer structure is controlled between 250-300°C.

[0022] As a preferred technical solution, in step S3, a gold-backed intermediate metal layer is formed on the surface of the ohmic metal layer, specifically comprising:

[0023] S3a, a Ti metal layer is formed on the back ohmic metal surface;

[0024] S3b, a Ni metal layer is formed on the surface of the Ti metal layer.

[0025] As a preferred technical solution, the thickness H of the Ti metal layer isTi =50-150nm, the thickness of the Ni metal layer H Ni =100-600nm, the thickness H1 of the first silver layer =200-750nm, the thickness H1 of the first silver layer is 20-40% of H1+H2, and the thickness H2 of the second silver layer is 60-80% of H1+H2.

[0026] As a preferred technical solution, in step S3, when a gold-backed Ti metal layer is formed on the back ohmic metal surface and a gold-backed Ni metal layer is formed on the Ti metal layer surface, a sputtering process is adopted, and the temperature of the SiC wafer structure is controlled within 80°C.

[0027] As a preferred technical solution, the method for improving back silver defects in SiC wafer structure also includes:

[0028] S6. Performing an annealing operation on the SiC wafer structure after the back-gold operation, wherein the annealing temperature of the annealing operation is 150-350° C., the annealing time is 10-60 min, and high-purity N2 gas is introduced during the annealing.

[0029] As a preferred technical solution, the method for improving the back silver defect of SiC wafer structure also includes:

[0030] S7. Perform wafer CP test and reliability test on the SiC wafer structure that has completed the annealing operation; wherein, the nitrogen holes of the wafer carrier in the CP & reliability test are configured to be distributed only along the edge of the wafer carrier, and the nitrogen holes only blow toward the area of ​​the SiC wafer structure where no Die is distributed.

[0031] As a preferred technical solution, the method for improving back silver defects in SiC wafer structure also includes:

[0032] S8. Divide the SiC wafer structure that has completed the wafer CP test and reliability test into multiple dies and package them into SiC devices respectively.

[0033] A second aspect of the present invention provides a SiC device, wherein the SiC device is manufactured by the SiC wafer structure back silver defect improvement method described above.

[0034] The method for improving the back silver defect of SiC wafer structure provided by the present invention adopts a double Ag layer distribution as the bottom back gold layer; wherein, the second silver layer of the back gold by high temperature processing is more dense, and has a stronger ability to resist the roughening test under high temperature, but the stress is large; therefore, a rough but low-stress first silver layer is first processed by low temperature processing to achieve the purpose of gradually releasing the stress; and, although the two silver layers are processed in different ways, the bonding degree is good, and the silver layer will not fall off at high temperature. In this way, the SiC wafer structure after back gold will not show macroscopic white spot defects visible to the naked eye during the subsequent electrical performance parameter CP test and wafer reliability test. In addition, the SiC device manufactured based on the above-mentioned method for improving the back silver defect of SiC wafer structure has the advantages of good stability and high durability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The figure is a process flow chart of processing a wafer into a single Die in the prior art.

[0036] Figure 2 This is an example diagram of a back silver defect in a wafer structure in the prior art.

[0037] Figure 3 A flow chart of a method for improving back silver defects in a SiC wafer structure provided by an embodiment of the present invention.

[0038] Figure 4 A schematic diagram of completing front side process, thinning and ohmic process on a SIC substrate in a method for improving back side silver defects of a SiC wafer structure provided in an embodiment of the present invention.

[0039] Figure 5 A schematic diagram of processing a Ti metal layer on the surface of an ohmic metal layer in a method for improving back silver defects of a SiC wafer structure provided in an embodiment of the present invention.

[0040] Figure 6 A schematic diagram of processing a Ni metal layer on the surface of a Ti metal layer in a method for improving back silver defects in a SiC wafer structure provided by an embodiment of the present invention.

[0041] Figure 7 A schematic diagram of forming a first silver layer with back-gold on the surface of an intermediate metal layer by low-temperature processing in a method for improving back-gold defects in a SiC wafer structure provided by an embodiment of the present invention.

[0042] Figure 8 A schematic diagram of processing a second silver layer on the surface of a first silver layer in a method for improving back silver defects of a SiC wafer structure provided by an embodiment of the present invention.

[0043] Fig. 9 The corresponding data comparison diagram of the warpage of the SiC wafer structure with a thickness of 110um under the traditional process and the process of the embodiment of the present invention.

[0044] Fig.10 It is a comparison chart of the roughness data of the outer surface of the silver layer of the SiC wafer structure under the traditional process and the process of the embodiment of the present invention.

[0045] Fig.11 Schematic diagram of the distribution of nitrogen holes in a conventional wafer carrier.

[0046] Fig.12 Schematic diagram of the nitrogen hole distribution of the wafer carrier newly configured in this embodiment of the present invention. DETAILED DESCRIPTION

[0047] The technical solutions of the embodiments of the present invention are explained and described below in conjunction with the drawings of the embodiments of the present invention, but the following embodiments are only preferred embodiments of the present invention, not all of them. In the description of the present invention, the terms "first" and "second" are only used for the purpose of distinction in the description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more, unless otherwise clearly defined.

[0048] The specific implementation modes of the present invention are described in detail below with reference to the accompanying drawings. Under the premise that there is no conflict between them, the technical features of each specific implementation mode can be inherited and used interchangeably.

[0049] The present embodiment provides a method for improving the back silver defect of a SiC wafer structure and a SiC device manufactured therefrom, aiming to solve the white spot defect that occurs on the back silver of a SiC wafer structure during the processing of SiC devices.

[0050] Combination Figure 3 As shown, the method for improving the back silver defect of SiC wafer structure provided in this embodiment includes the following steps:

[0051] S1, processing and forming a front process film layer on the front side of the SiC substrate;

[0052] S2, processing a back ohmic metal layer on the back side of the SiC substrate;

[0053] S3, a gold-backed intermediate metal layer on the surface of the ohmic metal layer;

[0054] S4, back-golding the first silver layer on the surface of the intermediate metal layer by low temperature processing;

[0055] S5, back-golding a second silver layer on the surface of the first silver layer by high temperature processing;

[0056] S6, performing annealing operation on the SiC wafer structure after the back-gold operation;

[0057] S7, performing wafer CP test and reliability test on the SiC wafer structure that has completed the annealing operation;

[0058] S8. Divide the SiC wafer structure that has completed the wafer CP test and reliability test into multiple dies and package them into SiC devices respectively.

[0059] The following is a detailed description of each step of the above-mentioned method for improving the back silver defect of SiC wafer structure in conjunction with the accompanying drawings:

[0060] First, see Figure 4 As shown, the front process, thinning and ohmic process are completed on the SIC substrate, that is, steps S1-S2 are completed, which belongs to the present embodiment and will not be described in detail.

[0061] Next, see Figure 5 and Figure 6 As shown, a gold-backed intermediate metal layer is formed on the surface of the ohmic metal layer, i.e., step S3. The intermediate metal layer includes a Ti metal layer and a Ni metal layer; therefore, step S3 specifically includes:

[0062] S3a, on the surface of the back ohmic metal layer, the back gold Ti metal layer, see Figure 5 ; Wherein, the thickness of the Ti metal layer H Ti =50-150nm, processed by sputtering process, and the temperature of SiC wafer structure is controlled within 80℃; of course, the electron beam evaporation process with the same process effect can also be used to form the Ti metal layer;

[0063] S3b, a Ni metal layer is formed on the surface of the Ti metal layer, see Figure 6 ; Wherein, the thickness of the Ni metal layer H Ni =100-600nm, that is, the thickness of the Ni metal layer is 2-4 times the thickness of the Ti metal layer; the Ni metal layer adopts the sputtering process, and the temperature of the SiC wafer structure is also controlled within 80°C; of course, the electron beam evaporation process with the same process effect can also be used to form the Ni metal layer.

[0064] Next, see Figure 7 As shown, the first silver layer is back-golded on the surface of the intermediate metal layer by low-temperature processing, that is, step S4. The low-temperature processing method adopts a sputtering process, the temperature of the SiC wafer structure is controlled between 100-150°C, and the thickness of the first silver layer H1=200-750nm, that is, the thickness of the first silver layer is 4-5 times the thickness of the Ti metal layer. Of course, an electron beam evaporation process with the same process effect can also be used to form the first silver layer.

[0065] Next, see Figure 8As shown, a second silver layer is back-golded on the surface of the first silver layer by high-temperature processing, i.e., step S5. The high-temperature processing method adopts a sputtering process, the temperature of the SiC wafer structure is controlled between 250-300°C, and the thickness of the second silver layer H2=600-1600nm; the thickness H1 of the first silver layer is 20-40% of H1+H2, and the thickness H2 of the second silver layer is 60-80% of H1+H2. Of course, an electron beam evaporation process with the same process effect can also be used to form the second silver layer.

[0066] In the above scheme, a double-layer Ag distribution is adopted. The second silver layer is denser and has a stronger ability to resist roughening under high temperature test, but the stress is large. Therefore, the first silver layer, which is relatively rough and has low stress, is deposited at low temperature before the second silver layer to achieve the purpose of gradual stress release.

[0067] Fig. 9 The corresponding data of the warpage of the SiC wafer structure with a thickness of 110um under the traditional process and the process of this embodiment are given, which can indirectly reflect that the double-layer Ag layer used in this embodiment has a significantly better stress release effect. In addition, Fig.10 The roughness data comparison of the outer surface of the silver layer of the SiC wafer structure under the traditional process and the process of this embodiment is given. It can be clearly seen that the double-layer Ag layer used in this embodiment has better compactness and stronger ability to resist roughening under high temperature test. In this way, the SiC wafer structure after back-gold will not show macroscopic white spot defects visible to the naked eye during the subsequent electrical performance parameter CP test and wafer reliability test. However, the stress is large; therefore, a rough but low-stress first silver layer is first processed by low-temperature processing to achieve the purpose of gradually releasing stress. Moreover, although the two silver layers formed in this embodiment are processed in different ways, they have good bonding and the silver layer will not fall off at high temperatures.

[0068] Then, the SiC wafer structure after the back-gold operation is annealed, i.e., step S6. The annealing temperature of the annealing operation is 150-350°C, the annealing time is 10-60min, and high-purity N2 gas is introduced during annealing. The above annealing operation exposes the SiC wafer structure after the back-gold operation to high temperature for a period of time, and then slowly cools it, which can further release stress and increase the ductility and toughness of the material.

[0069] After that, the SiC wafer structure that has completed the annealing operation is subjected to a CP& reliability test, i.e., step S7. In order to further reduce the risk of back Ag whitening and even the risk of Ag layer peeling, the nitrogen holes of the wafer carrier in the CP& reliability test are configured to be distributed only along the edge of the wafer carrier, and the nitrogen holes are only blown to the area where the SiC wafer structure is not distributed with Die. Specifically, see Fig.11 and Fig.12 , Fig.11 The figure shows the distribution of nitrogen holes in a conventional wafer carrier, wherein the nitrogen holes are dispersedly distributed over the entire surface of the carrier; Fig.12 The figure shows the nitrogen hole distribution of the newly configured wafer carrier plate in this embodiment, wherein the nitrogen holes are only arranged at the edge of the plate surface. For example, there will be no chips Die distributed within about 1-3 mm of the wafer edge. In this way, the performance of the usable chips Die in the wafer will not be affected by excessive nitrogen, and at the same time, the nitrogen can still play the role of isolation and protection.

[0070] Finally, the SiC wafer structure that has completed the wafer CP test and the reliability test is divided into a plurality of dies and packaged into SiC devices respectively, that is, step S8.

[0071] This embodiment also provides a SiC device, which is manufactured by the SiC wafer structure back silver defect improvement method described above. The SiC device manufactured based on the SiC wafer structure back silver defect improvement method has the advantages of good stability and high durability.

[0072] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A method for improving back silver defects of SiC wafer structure, comprising: S1, processing and forming a front process film layer on the front side of the SiC substrate; S2, processing a back ohmic metal layer on the back side of the SiC substrate; S3, a gold-backed intermediate metal layer on the surface of the ohmic metal layer; It is characterized by further comprising: S4, back-golding the first silver layer on the surface of the intermediate metal layer by low temperature processing; S5, back-golding a second silver layer on the surface of the first silver layer by high temperature processing.

2. The method for improving back silver defects of SiC wafer structure according to claim 1, characterized in that: The low temperature processing method adopts a sputtering process, and the temperature of the SiC wafer structure is controlled between 100-150°C.

3. The method for improving back silver defects of SiC wafer structure according to claim 2, characterized in that: The high temperature processing method adopts a sputtering process, and the temperature of the SiC wafer structure is controlled between 250-300°C.

4. The method for improving back silver defects of SiC wafer structure according to claim 1, characterized in that: In step S3, a gold-backed intermediate metal layer is formed on the surface of the ohmic metal layer, specifically comprising: S3a, a Ti metal layer is formed on the back ohmic metal surface; S3b, a Ni metal layer is formed on the surface of the Ti metal layer.

5. The method for improving back silver defects of SiC wafer structure according to claim 4, characterized in that: The thickness H of the Ti metal layer Ti =50-150nm, the thickness of the Ni metal layer H Ni =100-600nm, the thickness H1 of the first silver layer =200-750nm, the thickness H1 of the first silver layer is 20-40% of H1+H2, and the thickness H2 of the second silver layer is 60-80% of H1+H2.

6. The method for improving back silver defects of SiC wafer structure according to claim 4, characterized in that: In step S3, when a gold Ti metal layer is formed on the back ohmic metal surface and a gold Ni metal layer is formed on the back Ti metal layer surface, a sputtering process is adopted, and the temperature of the SiC wafer structure is controlled within 80°C.

7. The method for improving back silver defects of SiC wafer structure according to claim 1, characterized in that: The method for improving back silver defects of SiC wafer structure also includes: S6. Performing annealing operation on the SiC wafer structure after the back-gold operation, wherein the annealing temperature of the annealing operation is 150-350° C., the annealing time is 10-60 min, and high-purity N2 gas is introduced during annealing.

8. The method for improving back silver defects of SiC wafer structure according to claim 7, characterized in that: The method for improving back silver defects of SiC wafer structure also includes: S7. Perform wafer CP test and reliability test on the SiC wafer structure that has completed the annealing operation; wherein, the nitrogen holes of the wafer carrier in the wafer CP test and reliability test are configured to be distributed only along the edge of the wafer carrier, and the nitrogen holes only blow toward the area of ​​the SiC wafer structure where no Die is distributed.

9. The method for improving back silver defects of SiC wafer structure according to claim 8, characterized in that: The method for improving back silver defects of SiC wafer structure also includes: S8. Divide the SiC wafer structure that has completed the wafer CP test and reliability test into multiple dies and package them into SiC devices respectively.

10. A SiC device, characterized in that: The SiC device is manufactured by the method for improving back silver defects of a SiC wafer structure according to any one of claims 1 to 9.

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