Thin film transistor, preparation method and display panel

Abstract

The invention provides a thin film transistor, a preparation method and a display panel. The thin film transistor comprises a substrate, an active layer and a gate electrode, the active layer is located on the substrate and comprises a channel region, a source region and a drain region, and the source region and the drain region are located on the two opposite sides of the channel region respectively; the gate electrode is located on one side, close to the substrate, of the active layer or on one side, away from the substrate, of the active layer, and a first slope angle of one side, close to the source region, of the gate electrode is smaller than a second slope angle of one side, close to the drain region, of the gate electrode. Through the design, the performance difference between the S end and the D end of the thin film transistor is improved and even eliminated by only adjusting the slope angles of the two sides of the gate electrode, so that the performance of the thin film transistor is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor, a preparation method and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) display technology is regarded as the most promising new flat panel display technology of the next generation. Compared with liquid crystal display technology, OLED display technology has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed. However, the performance of thin film transistors used to drive organic light emitting diodes in current display panels needs to be improved.

[0003] To this end, existing display panels need to be improved. Summary of the invention

[0004] In view of this, the purpose of the present application is to propose a thin film transistor, a preparation method, and a display panel, aiming to improve the process performance of the display panel.

[0005] To achieve the above object, the present application provides a thin film transistor, which includes:

[0006] substrate;

[0007] An active layer, located on the substrate, the active layer comprising a channel region and a source region and a drain region respectively located on both sides of the channel region;

[0008] The gate electrode is located on a side of the active layer close to the substrate, or on a side of the active layer away from the substrate, and a first slope angle of the gate electrode close to the source region is smaller than a second slope angle of the gate electrode close to the drain region.

[0009] In one embodiment, the angle between the side surface of the gate electrode close to the source region and the plane where the substrate is located is a first slope angle, and the angle between the side surface of the gate electrode close to the drain region and the plane where the substrate is located is a second slope angle;

[0010] Preferably, the ratio of the second slope angle to the first slope angle is between 1.2-1.01;

[0011] Preferably, the ratio of the second slope angle to the first slope angle is between 1.1 and 1.01.

[0012] In one embodiment, the difference between the second slope angle and the first slope angle is greater than or equal to 5°;

[0013] Preferably, the difference between the second slope angle and the first slope angle is greater than 5° and less than or equal to 25°.

[0014] In one embodiment, the first slope angle is between 40° and 70°;

[0015] Preferably, the first slope angle is between 45° and 65°;

[0016] Preferably, the first slope angle is between 45° and 55°.

[0017] In one embodiment, the second slope angle is between 55° and 80°;

[0018] Preferably, the second slope angle is between 60° and 70°.

[0019] In one embodiment, it further comprises:

[0020] a gate insulating layer, the gate insulating layer being located on a side of the active layer away from the substrate and on a side of the gate electrode close to the substrate, or being located on a side of the active layer close to the substrate and covering the gate electrode;

[0021] A buffer layer, located on the substrate and on a side of the active layer close to the substrate;

[0022] Preferably, the material of the gate insulating layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof;

[0023] Preferably, the material of the buffer layer includes at least one of silicon oxide, silicon nitride or a combination thereof;

[0024] Preferably, the buffer layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer which are stacked.

[0025] Based on the same inventive concept, the present application also provides a method for preparing a thin film transistor, the method comprising:

[0026] forming a substrate;

[0027] An active layer is formed on one side of the substrate, wherein the active layer includes a channel region and a source region and a drain region respectively located on both sides of the channel region;

[0028] A gate electrode is formed on a side of the active layer away from the substrate, and a first slope angle of the gate electrode close to the source region is smaller than a second slope angle of the gate electrode close to the drain region, or,

[0029] forming a substrate;

[0030] A gate electrode is formed on one side of the substrate,

[0031] An active layer is formed on a side of the gate electrode away from the substrate, the active layer comprising a channel region and a source region and a drain region respectively located on both sides of the channel region, and a first slope angle of the gate electrode close to the source region is smaller than a second slope angle of the gate electrode close to the drain region.

[0032] In one embodiment, forming a gate electrode on a side of the active layer away from the substrate specifically includes:

[0033] forming a gate electrode layer on a side of the active layer away from the substrate, and patterning the gate electrode layer to form a gate electrode,

[0034] Or the forming of a gate electrode on one side of the substrate specifically includes:

[0035] forming a gate electrode layer on one side of the substrate, and patterning the gate electrode layer to form a gate electrode;

[0036] Preferably, the step of patterning the gate electrode layer comprises patterning the gate electrode layer using a mask plate to form a gate electrode.

[0037] Preferably, the gate electrode is patterned using a grayscale mask to form the gate electrode;

[0038] Preferably, the gate electrode is patterned using a semi-transparent mask to form the gate electrode.

[0039] In one embodiment, before the step of forming a gate electrode on a side of the active layer away from the substrate, the step further includes:

[0040] forming a gate insulating layer on a side of the active layer away from the substrate; or, before the step of forming an active layer on a side of the gate electrode away from the substrate, the method further comprises:

[0041] forming a gate insulating layer on a side of the gate electrode away from the substrate;

[0042] Preferably, a gate electrode is formed on a side of the gate insulating layer away from the substrate; or an active layer is formed on a side of the gate insulating layer away from the substrate.

[0043] Based on the same inventive concept, the present application also provides a display panel, which includes the thin film transistor as described above.

[0044] Compared with the prior art, the thin film transistor proposed in the present application increases the second slope angle in disguise by adjusting the first slope angle on the source region side of the gate electrode corresponding to the source region and the second slope angle on the drain region side of the gate electrode, thereby reducing the aggregation of the D-end edge taper and reducing the electrode size, thereby improving the electrode performance of the D-end of the TFT (thin film transistor) device, improving or even eliminating the electrode performance difference between the S-end and the D-end of the thin film transistor, thereby improving the performance of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a schematic cross-sectional view of a conventional thin film transistor;

[0047] Figure 2 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present application;

[0048] Figure 3 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present application;

[0049] Figure 4 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present application;

[0050] Figure 5 A schematic cross-sectional view of a thin film transistor with a bottom-mounted gate according to an embodiment of the present application;

[0051] Figure 6 The process diagram of the method for preparing the thin film transistor of the embodiment of the present application is shown in FIG. Figure 1 ;

[0052] Figure 7 The process diagram of the method for preparing the thin film transistor of the embodiment of the present application is shown in FIG. Figure 2 . DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0054] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0055] The display panel includes a substrate, a driving layer and a light-emitting functional layer. The driving layer is arranged on the substrate. The driving layer includes a pixel driving circuit, which is electrically connected to the corresponding light-emitting unit in the light-emitting functional layer and driven by the pixel driving circuit to light up the light-emitting unit. The pixel driving circuit includes a plurality of thin-film transistors (TFTs) and capacitors. The performance of thin-film transistors directly affects the image quality of the screen display.

[0056] The applicant discovered during the study of the structure of the thin film transistor of the existing pixel driving circuit that Figure 1 As shown, the thin film transistor includes an active layer, a gate insulating layer 150 and a gate layer electrode 160 stacked on one side of a substrate 110, the active layer includes a channel region 120 and a source region 130 and a drain region 140 arranged on opposite sides of the channel region 120, the electrode performance of the source region (Source, S end) of the thin film crystal is better than the electrode performance of the drain region (Drain, D end), that is, there is a difference in electrical polarity between the S end and the D end, and the difference affects the characteristics of the thin film transistor. If the thin film transistor is a driving transistor, it affects the light-emitting quality of the corresponding light-emitting unit and thus affects the displayed image quality.

[0057] Based on this discovery, the applicant improved the structure of the thin film transistor to reduce or even eliminate the difference in electrical polarity between the S end and the D end of the thin film crystal, so as to improve the display quality.

[0058] Next, the thin film transistor, manufacturing method, display panel and display device proposed in the present application are described in conjunction with the accompanying drawings.

[0059] like Figure 2 FIG. 4 is a schematic diagram of a thin film transistor according to an embodiment of the present application.

[0060] The thin film transistor comprises:

[0061] The thin film transistor includes an active layer 20, a gate insulating layer 15 and a gate electrode 16 (also called a gate electrode) stacked on one side of a substrate 11; the active layer 20 includes a channel region 12 and a source region 13 (Source, S end) and a drain region 14 (Drain, D end) located on opposite sides of the channel region 12.

[0062] The angle between the side surface 161 of the gate electrode 16 close to the source region and the plane where the substrate 11 is located is a first slope angle α, and the angle between the side surface 162 of the gate electrode 16 close to the drain region 13 and the plane where the substrate 11 is located is a second slope angle β, wherein the first slope angle α of the gate electrode 16 close to the source region 13 is smaller than the second slope angle β of the gate electrode 16 close to the drain region 14. Through such a design, only the slope angle between the side surfaces on the opposite sides of the gate electrode and the plane where the substrate 11 is located (the first slope angle α and the second slope angle β are collectively referred to as the taper angle) is adjusted to improve the electrode performance difference between the S end / D end of the thin film transistor (the thickness of the gate electrode is not changed at this time). In this way, the existing process can be unchanged, and the performance of the thin film transistor can be improved without additionally increasing the cost. In this embodiment, the thin film transistor adopts a gate top type (that is, the gate electrode is located on the upper side of the S end / D end). By adjusting the slope angle in this way, the overlapping area between the gate electrode and the drain region can be improved, thereby adjusting the parasitic capacitance Cgs, improving the risk of flickering during display and the signal delay caused by changes in the cross-sectional area of ​​the gate electrode (resistance change).

[0063] In one embodiment, the first slope angle α of the gate electrode 16 close to the source region 13 is smaller than the second slope angle β of the gate electrode 16 close to the drain region 14. Preferably, the first slope angle α is between 40°-70°, and further, the first slope angle α is between 45°-65°. Further, the first slope angle α is between 55°-65°. The second slope angle β is between 55°-80° (such as 55°, 60°, 65°, 70°, 75°, 80°); further, the second slope angle β is between 60°-75°. Further, the second slope angle β is between 60°-70°. Such a design is used to improve the electrode performance difference between the S-end / D-end of the thin film transistor. The second slope angle β should not exceed 80°, otherwise the dielectric deposited there may be discontinuous in the subsequent process (there is gate electrode metal exposed on this side), which may short-circuit the subsequent metal layer. In addition, the dielectric discontinuity at this location may easily cause peeling problems.

[0064] In one embodiment, the active layer may include a channel region 12 containing a lanthanide metal doping material; the lanthanide metal element in the lanthanide metal doping material may form a trap state in the active layer, and when the active layer is illuminated, photogenerated electrons are generated, and the photogenerated electrons can be captured by the trap state, thereby improving the light stability of the active layer. In one embodiment, the active layer may include a light shielding protective layer, and the light shielding protective layer includes indium zinc oxide (Ln-IZO) doped with a lanthanide metal (the lanthanide metal may include praseodymium (Pr)) or indium gallium zinc oxide (Ln-IGZO) doped with a lanthanide metal.

[0065] In one embodiment, the first slope angle α of the gate electrode 16 close to the source region 13 is maintained, and the second slope angle β (the taper angle of the gate electrode close to the drain region) is increased, so that the electrode at the D end is reduced, while the taper angle at the S end remains unchanged, which will cause the electrode strength at the D end to weaken, so as to achieve the purpose of reducing the difference in electrode performance at the S / D ends.

[0066] In one embodiment, the ratio of the second slope angle β to the first slope angle α is between 1.2 and 1.01. Such a design is used to improve the electrode performance difference between the S-end and the D-end of the thin film transistor. Such a design relatively increases the slope angle (taper angle) on the D-end side, reduces the aggregation of the taper at the edge of the D-end and reduces the electrode size, thereby improving the electrode performance at the D-end of the TFT device, thereby improving the electrode performance difference between the S-end and the D-end of the thin film transistor.

[0067] In one embodiment, the difference between the second slope angle β and the first slope angle α is greater than or equal to 5° and less than or equal to 25° (eg, the difference between the second slope angle and the first slope angle is 5°, 10°, 15°, 20°, 25°).

[0068] In one embodiment, a gate insulating layer 15 is further included, and the gate insulating layer is located between the active layer 20 and the gate electrode 16. In this embodiment, the gate insulating layer 15 is located on the side of the active layer 20 away from the substrate 11, and is located on the side of the gate electrode 16 close to the substrate 11. The thickness of the gate insulating layer 15 can be 3500 angstroms-8000 angstroms. Preferably, the thickness of the gate insulating layer is 3500 angstroms-4500 angstroms. The material of the gate insulating layer 15 can be at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0069] As Figure 2 Variations of the embodiments, such as Figure 3 As shown, Figure 2 The difference between the embodiments is that a buffer layer 17 is stacked on the substrate 11, and the material of the buffer layer 17 includes at least one of silicon oxide and silicon nitride or a combination thereof.

[0070] As Figure 3Variations of the embodiments, such as Figure 4 As shown, the buffer layer includes a first silicon oxide layer 171, a silicon nitride layer 172 and a second silicon oxide layer 173, and the thickness of the first silicon oxide layer 171 can be different from or the same as the thickness of the second silicon oxide layer 173. The first silicon oxide layer and the second silicon oxide layer 173 are collectively referred to as silicon oxide layers.

[0071] As Figure 2 Variations of the embodiments, such as Figure 5 , which is a schematic diagram of a thin film transistor according to another embodiment of the present application (the thin film transistor may also adopt a bottom-mounted gate type (ie, the gate electrode is located on a side of the active layer close to the substrate).

[0072] The thin film transistor includes: a gate electrode 26 (also called a gate electrode) stacked on one side of a substrate 21, a gate insulator 25 and an active layer, the active layer includes a channel region 22 and a source region 23 (Source, S end) and a drain region 24 (Drain, D end) respectively located on opposite sides of the channel region 22, and the first slope angle α of the gate electrode 26 (also called a gate electrode) close to the source region 23 is smaller than the second slope angle β of the gate electrode 26 close to the drain region 24. Preferably, the first slope angle α is between 40° and 65°, and further, the first slope angle α is between 40° and 55°. The second slope angle β is between 55° and 80° (such as 55°, 60°, 65°, 70°, 75°, 80°); further, the second slope angle β is between 60° and 70°. By relatively increasing the slope angle (taper angle) of the D end through such a design, the taper aggregation of the D end edge can be reduced to reduce the electrode size, thereby improving the electrode performance of the D end of the TFT device, and improving the electrode performance difference between the S end and the D end of the thin film transistor. The second slope angle should not exceed 80°, because in the subsequent process, the dielectric deposited there is likely to be discontinuous (there is gate electrode metal exposed on this side), short-circuiting with the subsequent metal layer, and the dielectric discontinuity at this location is likely to cause peeling problems.

[0073] In one embodiment, a gate insulating layer 25 is further included, and the gate insulating layer 25 is located between the active layer and the gate electrode 26. In this embodiment, the gate insulating layer 25 is located on the side of the active layer 20 close to the substrate and is located to cover the gate electrode 26. The thickness of the gate insulating layer 25 can be 3500 angstroms-8000 angstroms. Preferably, the thickness of the gate insulating layer is 3500 angstroms-4500 angstroms. The material of the gate insulating layer can be at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0074] Combine the following Figure 6-Figure 7 The preparation process of the thin film transistor of the present application is described in detail. It can be understood that

[0075] refer to Figure 6, an embodiment of the present application provides a method for preparing a thin film transistor, the method comprising:

[0076] S10: forming a substrate;

[0077] S20: forming an active layer on one side of the substrate, the active layer comprising a channel region and a source region and a drain region respectively located on both sides of the channel region, and the material of the active layer may comprise an oxide semiconductor material;

[0078] S30: forming a gate electrode on a side of the active layer away from the substrate, wherein a first slope angle of a side of the gate electrode close to the source region is smaller than a second slope angle of a side of the gate electrode close to the drain region;

[0079] Specifically, the step of forming a gate electrode on a side of the active layer away from the substrate specifically includes:

[0080] S31: forming a gate electrode layer on a side of the active layer away from the substrate,

[0081] S32: Patterning the gate electrode layer to form a gate electrode, wherein the first slope angle of the gate electrode near the source region is smaller than the second slope angle of the gate electrode near the drain region. By such a design, the slope angle of the D-end side is relatively increased to reduce the concentration of the taper at the edge of the D-end and reduce the electrode, thereby improving the electrode performance of the D-end of the thin film transistor, and improving or even eliminating the electrode performance difference between the S-end / D-end of the thin film transistor.

[0082] In one embodiment, forming the gate electrode includes sputtering, evaporating or depositing a gate electrode layer (metal layer) on the side of the active layer away from the substrate (ie, on the gate insulating layer). Sputtering, evaporation, deposition, etc. are all mature preparation processes in the relevant technology.

[0083] In one embodiment, a gray-tone mask (GTM) is used to pattern the gate electrode layer to prepare the gate electrode. The gray-tone mask generates images of different gray levels during the exposure process through the interference and diffraction principles of light. Alternatively, a half-tone mask (HTM) is used to pattern the gate electrode layer to prepare the gate electrode. In this embodiment, the gate electrode is processed by the HTM / GTM method. After etching under different light, the D-end taper will increase, and the S-end taper will remain unchanged.

[0084] In one embodiment, before step S30, the method further includes:

[0085] S300: forming a gate insulating layer on a side of the active layer away from the substrate, wherein the thickness of the gate insulating layer may be 3500 angstroms to 8000 angstroms, preferably, the thickness of the gate insulating layer is 3500 angstroms to 4500 angstroms, and the material of the gate insulating layer may be at least one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.

[0086] Further, S30 specifically includes forming a gate electrode on a side of the gate insulating layer away from the substrate.

[0087] refer to Figure 7 The present invention provides a method for preparing a thin film transistor, the method comprising:

[0088] S10: forming a substrate;

[0089] S20: forming a gate electrode on one side of the substrate;

[0090] S30: An active layer is formed on a side of the gate electrode away from the substrate, the active layer comprising a channel region and a source region and a drain region respectively located on both sides of the channel region, the material of the active layer may comprise an oxide semiconductor material, and a first slope angle on a side of the gate electrode close to the source region is smaller than a second slope angle on a side of the gate electrode close to the drain region; by such a design, the slope angle on the D-end side is relatively increased to reduce the aggregation of the taper at the edge of the D-end and reduce the electrode, thereby improving the electrode performance of the D-end of the thin film transistor, and improving or even eliminating the electrode performance difference between the S-end / D-end of the thin film transistor.

[0091] In one embodiment, before step S30, the method further includes:

[0092] S300: forming a gate insulating layer on a side of the gate electrode away from the substrate. Further, step S30 specifically includes forming an active layer on a side of the gate insulating layer away from the substrate.

[0093] An embodiment of the present application provides a display panel, the display panel comprising:

[0094] The substrate is a flexible substrate, and its material can be selected from polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), etc. The material can also be a mixed material of the above materials, or the substrate can be a hard substrate, and its material can be selected from glass.

[0095] A driving layer is provided on the substrate, the driving layer includes a pixel driving circuit located in the display area, and the driving layer also includes a first metal wiring located in the non-display area. The pixel driving circuit may include, for example, 2T1C (i.e., 2 transistors (TFT) and 1 capacitor (C)), 3T1C, 7T1C or 7T2C. The pixel driving circuit is electrically connected to the light-emitting unit to control the switching state and light brightness of the light-emitting unit.

[0096] In one embodiment, the driving layer may include a data line and a scan line. The data line and the gate line may be coupled to at least one thin film transistor in the pixel driving circuit and configured to write an electrical signal to the thin film transistor. When the thin film transistor is in an on state, the electrical signal on the data line may be written to the pixel electrode through the thin film transistor, thereby driving the sub-pixel to emit light.

[0097] It should be noted that the display panel can also be configured to include other functional structures, for example, the display panel can also include an identification structure to have a fingerprint identification function. For example, the identification structure can be a touch panel or a touch layer, and the touch panel can be arranged in the display panel by bonding, for example, the touch layer can be directly prepared on the encapsulation layer of the display panel, so as to facilitate the thin and light design of the display panel.

[0098] Another preferred embodiment of the present disclosure discloses a display device, which includes the substrate in the above embodiment. Further, the display device includes a mobile phone, VR equipment, computer, television, car display equipment, etc.

[0099] Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0100] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0101] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A thin film transistor, characterized in that: include: substrate; An active layer, located on the substrate, the active layer comprising a channel region and a source region and a drain region respectively located on both sides of the channel region; The gate electrode is located on a side of the active layer close to the substrate, or on a side of the active layer away from the substrate, and a first slope angle of the gate electrode close to the source region is smaller than a second slope angle of the gate electrode close to the drain region.

2. The thin film transistor according to claim 1, wherein: The angle between the side surface of the gate electrode close to the source region and the plane where the substrate is located is a first slope angle, and the angle between the side surface of the gate electrode close to the drain region and the plane where the substrate is located is a second slope angle; Preferably, the ratio of the second slope angle to the first slope angle is between 1.2 and 1.

01. Preferably, the ratio of the second slope angle to the first slope angle is between 1.1 and 1.

01.

3. The thin film transistor according to claim 1, wherein: The difference between the second slope angle and the first slope angle is greater than or equal to 5°; Preferably, the difference between the second slope angle and the first slope angle is greater than 5° and less than or equal to 25°.

4. The thin film transistor according to claim 1, wherein: The first slope angle is between 40° and 70°; Preferably, the first slope angle is between 45° and 65°; Preferably, the first slope angle is between 45° and 55°.

5. The thin film transistor according to claim 1, wherein: The second slope angle is between 55° and 80°; Preferably, the second slope angle is between 60° and 70°.

6. The thin film transistor according to claim 1, wherein: Also includes: a gate insulating layer, the gate insulating layer being located on a side of the active layer away from the substrate and on a side of the gate electrode close to the substrate, or being located on a side of the active layer close to the substrate and covering the gate electrode; A buffer layer, located on the substrate and on a side of the active layer close to the substrate; Preferably, the material of the gate insulating layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof; Preferably, the material of the buffer layer includes at least one of silicon oxide, silicon nitride or a combination thereof; Preferably, the buffer layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer which are stacked.

7. A method for preparing a thin film transistor, characterized in that: forming a substrate; An active layer is formed on one side of the substrate, wherein the active layer includes a channel region and a source region and a drain region respectively located on both sides of the channel region; A gate electrode is formed on a side of the active layer away from the substrate, and a first slope angle of the gate electrode close to the source region is smaller than a second slope angle of the gate electrode close to the drain region, or forming a substrate; forming a gate electrode on one side of the substrate; An active layer is formed on a side of the gate electrode away from the substrate, the active layer comprising a channel region and a source region and a drain region respectively located on both sides of the channel region, and a first slope angle of the gate electrode close to the source region is smaller than a second slope angle of the gate electrode close to the drain region.

8. The method for preparing a thin film transistor according to claim 7, characterized in that: The forming of a gate electrode on a side of the active layer away from the substrate specifically includes: forming a gate electrode layer on a side of the active layer away from the substrate, and patterning the gate electrode layer to form a gate electrode, Or, the forming of the gate electrode on one side of the substrate specifically includes: forming a gate electrode layer on one side of the substrate, and patterning the gate electrode layer to form a gate electrode; Preferably, the step of patterning the gate electrode layer comprises patterning the gate electrode layer using a mask plate to form a gate electrode. Preferably, the gate electrode is patterned using a grayscale mask to form the gate electrode; Preferably, the gate electrode is patterned using a semi-transparent mask to form the gate electrode.

9. The method for preparing a thin film transistor according to claim 7, wherein: Before the step of forming a gate electrode on a side of the active layer away from the substrate, the method further comprises: forming a gate insulating layer on a side of the active layer away from the substrate; or, before the step of forming an active layer on a side of the gate electrode away from the substrate, the method further comprises: forming a gate insulating layer on a side of the gate electrode away from the substrate; Preferably, a gate electrode is formed on a side of the gate insulating layer away from the substrate; or an active layer is formed on a side of the gate insulating layer away from the substrate.

10. A display panel, characterized in that: include: A thin film transistor as claimed in any one of claims 1 to 6.

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