Formation method of semiconductor structure
By adjusting the formation of light doped drain regions by using the difference in side wall thickness during the formation of semiconductor structures, the problem of lower PMOS performance than NMOS is solved, and the effect of improving PMOS performance while ensuring that NMOS performance remains unchanged is achieved.
Patent Information
- Application Number
- CN202510096876.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-04-25
AI Technical Summary
In semiconductor devices in the deep submicron range, PMOS performance is lower than NMOS, and it is difficult for the prior art to improve PMOS performance while ensuring that NMOS performance remains unchanged.
During the formation of the semiconductor structure, discretely arranged gate layers are formed on the substrate surfaces of the NMOS and PMOS regions, and side walls are formed on the side walls of the gate layer, and multiple ion implantation is performed to form a light doped drain region. The overlapping surface between the light doped drain region and the bottom of the gate layer is adjusted by using the thickness difference of the side walls.
On the premise of ensuring that NMOS performance remains unchanged, the formation of light doped leakage regions is adjusted through the difference in side wall thickness, which significantly improves the performance of PMOS, reduces leakage current, and improves the isolation and reliability of the device.
Smart Images
Figure CN119894080A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] As the size of semiconductor devices enters the deep submicron channel length range, the electric field strength inside the device also increases. In particular, there is a strong electric field near the drain junction. The carriers obtain higher energy in this strong electric field and become hot carriers. Hot carriers have a certain impact on device performance. On the one hand, hot carriers cross the Si-SiO2 barrier and are injected into the oxide layer. They accumulate continuously, change the threshold voltage and thus affect the device life. On the other hand, they collide with the lattice in the depletion region near the drain to produce electron-hole pairs. For NMOS tubes, the electrons generated by the collision form additional leakage current, and the holes are collected by the substrate to form substrate current, making the total current the sum of the saturated leakage current and the substrate current. The larger the substrate current, the more collisions occur in the channel, and the more serious the corresponding hot carrier effect. The hot carrier effect is one of the basic factors that limit the maximum operating voltage of the device.
[0003] In order to weaken the electric field in the drain region and improve the hot carrier injection effect, the prior art adopts an LDD (Lightly Doped Drain) structure in MOSFET, that is, a low-doped drain region is set near the drain in the channel, so that the low-doped drain region also bears part of the voltage. This structure can prevent the hot carrier injection effect. In the actual manufacturing process, the source and drain ends will use the sidewall layer process to form LDD, but the width of the sidewall layer of PMOS and NMOS in the traditional process is the same.
[0004] As the feature size of ultra-large-scale integrated circuits develops according to Moore's Law, it has now developed to a feature size of 20 nanometers and below, so as to increase the capacity of semiconductor devices in a smaller area and reduce costs, forming semiconductor devices with better performance and lower power consumption. As we all know, NMOS and PMOS have the same spacer size before ion implantation in the source and drain regions, but for PMOS, because the mass of boron atoms is small and they diffuse quickly, the performance of the device is easily affected by the size of the spacer; for NMOS, because the atomic mass of phosphorus atoms is large, it is not easily affected by the size of the spacer.
[0005] Therefore, how to improve PMOS performance while ensuring that NMOS performance remains unchanged is a technical problem that needs to be solved urgently. Summary of the invention
[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region and a second device region adjacent to the first device region; forming discretely arranged gate layers on the surface of the substrate in the first device region and the second device region respectively; forming a first sidewall on the sidewall of the gate layer; performing a first ion implantation on the substrate on both sides of the first sidewall of the first device region; forming a second sidewall on the sidewall of the first sidewall; and performing a second ion implantation on the substrate on both sides of the second sidewall of the second device region.
[0008] Optionally, after the first ion implantation, a first lightly doped drain region is formed in the substrate on both sides of the first side wall of the first device region, and the overlap surface between the first lightly doped drain region and the bottom of the gate layer is negatively correlated with the thickness of the first side wall; after the second ion implantation, a second lightly doped drain region is formed in the substrate on both sides of the second side wall of the second device region, and the overlap surface between the second lightly doped drain region and the bottom of the gate layer is negatively correlated with the sum of the thicknesses of the first side wall and the second side wall.
[0009] Optionally, the ion type of the first ion implantation is opposite to the ion type of the second ion implantation.
[0010] Optionally, before forming the first sidewall spacer and performing the first ion implantation, the method further includes: forming a first mask layer on the substrate surface of the second device region, the sidewall of the first sidewall spacer of the second device region, and the top surface of the gate layer.
[0011] Optionally, after performing the first ion implantation and before forming the second sidewall spacer, the method further includes: removing the first mask layer.
[0012] Optionally, after forming the second sidewall and before performing the second ion implantation, the method further includes: forming a second mask layer on the substrate surface of the first device region, the sidewall of the second sidewall of the first device region, and the top surface of the gate layer.
[0013] Optionally, after the second ion implantation, the method further includes: removing the second mask layer.
[0014] Optionally, the thickness of the first sidewall spacer ranges from 55 angstroms to 65 angstroms.
[0015] Optionally, the thickness of the second sidewall spacer is in a range of 20 angstroms to 30 angstroms.
[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0017] In the method for forming a semiconductor structure of the present invention, after forming a gate layer, a first sidewall is formed on the sidewall of the gate layer, a first ion implantation is performed on the substrate of the first device region, a second sidewall is formed on the sidewall of the first sidewall, and a second ion implantation is performed on the substrate of the second device region; during the first ion implantation in the first device region, a first sidewall is formed on the sidewall of the gate layer in the first device region, and during the second ion implantation in the second device region, a second sidewall is formed on the sidewall of the gate layer in the second device region. By utilizing the difference in the sidewalls between the first device region and the second device region during the ion implantation process, the performance of the device formed in the second device region can be improved while ensuring that the performance of the device formed in the first device region remains unchanged, and the method has a wider range of applications.
[0018] Furthermore, after the first ion implantation, a first lightly doped drain region is formed in the substrate on both sides of the first sidewall of the first device region, and the overlap surface between the first lightly doped drain region and the bottom of the gate layer is negatively correlated with the thickness of the first sidewall; after the second ion implantation, a second lightly doped drain region is formed in the substrate on both sides of the second sidewall of the second device region, and the overlap surface between the second lightly doped drain region and the bottom of the gate layer is negatively correlated with the sum of the thicknesses of the first sidewall and the second sidewall; after the ion implantation, a lightly doped drain region is formed in the substrate on both sides of the gate layer, but if the overlap surface between the lightly doped drain region and the bottom of the gate layer is larger, it is easier to form a current channel, which This will affect the isolation of the device, so the overlapping surface between the first lightly doped drain region and the bottom of the gate layer is negatively correlated with the thickness of the first side wall, so as to ensure that the overlapping area between the first lightly doped drain region formed after the first ion injection and the bottom of the gate layer is as small as possible, thereby not easily forming a current channel, thereby ensuring the isolation of the device; similarly, the overlapping surface between the second lightly doped drain region and the bottom of the gate layer is negatively correlated with the sum of the thicknesses of the first side wall and the second side wall, thereby ensuring that the overlapping area between the second lightly doped drain region formed after the second ion injection and the bottom of the gate layer is as small as possible, thereby not easily forming a current channel, thereby ensuring the isolation of the device, and having a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figures 1 to 3 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment;
[0020] Figures 4 to 9 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION
[0021] As mentioned in the background technology, the performance of PMOS still needs to be improved. Figures 1 to 3 Provide explanation.
[0022] First, please refer to Figure 1 , providing a substrate 100, the substrate 100 includes an NMOS region and a PMOS region, an isolation structure 101 is formed between the NMOS region and the PMOS region, and discretely arranged gate layers 102 are respectively formed on the NMOS region and the PMOS region; an initial spacer layer 103 is formed on the surface of the substrate 100 and the sidewall and top surface of the gate layer 102.
[0023] Please refer to Figure 2 , etching the initial spacer layer 103 , and forming a spacer 104 on the sidewall of the gate layer 102 .
[0024] Please refer to Figure 3 , a first ion implantation is performed on the substrate 100 on both sides of the sidewall 104 of the NMOS to form a first lightly doped drain region 105 , and a second ion implantation is performed on the substrate 100 on both sides of the sidewall 104 of the PMOS to form a second lightly doped drain region 106 .
[0025] The inventors found that the sidewalls of NMOS and PMOS are formed simultaneously through a process, and the thickness of the sidewalls of NMOS and PMOS are the same. However, due to the abnormal diffusion effect of different types of doping particles, when the performance of PMOS is improved, the performance of NMOS will deteriorate.
[0026] The inventors have discovered through research that after a first sidewall is formed on the sidewall of the gate layer in the first device area, a first ion implantation is performed on the substrate on both sides of the gate layer in the first device area; then a second sidewall is formed on the sidewall of the first sidewall, and a second ion implantation is performed on the substrate on both sides of the gate layer in the second device area. In view of the abnormal diffusion effects of different types of doped particles, the sidewalls of the first device area and the second device area are set to be different during the ion implantation process, thereby being able to improve the performance of the devices in the second device area while ensuring that the performance of the devices in the first device area remains unchanged, and having a wider range of applications.
[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0028] First, please refer to Figure 4 , providing a substrate 200.
[0029] The substrate 200 includes a first device region I and a second device region II adjacent to the first device region I.
[0030] In this embodiment, the first device region I is used to form an NMOS device, and the second device region II is used to form a PMOS device.
[0031] In other embodiments, the first device region I may also be used to form a PMOS device, and the second device region II is used to form an NMOS device.
[0032] In this embodiment, the material of the substrate 200 is single crystal silicon.
[0033] In other embodiments, the material of the substrate 200 may also be semiconductor materials such as polycrystalline silicon, amorphous silicon, germanium, silicon germanium, and gallium arsenide.
[0034] In this embodiment, a first well region is formed in the first device region I, and a second well region is formed in the second device region II. The first well region has first doping ions, and the second well region has second doping ions. The first doping ions and the second doping ions are of different types.
[0035] In this embodiment, the first well region is a P-well, and the first doping ion is boron.
[0036] In this embodiment, the second well region is an N-well, and the second doping ion is phosphorus.
[0037] In this embodiment, an isolation structure 201 is further formed in the substrate 200 , and the isolation structure 201 is located between the first device region I and the second device region II.
[0038] In this embodiment, the isolation structure 201 is formed before the first well region and the second well region.
[0039] In this embodiment, the method for forming the isolation structure 201 includes: etching the substrate 200 to form a shallow trench (not shown in the figure) in the substrate 200 ; and depositing silicon oxide in the shallow trench to form the isolation structure 201 .
[0040] In this embodiment, before depositing silicon oxide, the sidewalls of the shallow trench are thermally oxidized so that the corners of the shallow trench become rounded after thermal oxidation, which can avoid inversion of the sidewalls of the shallow trench, ensure that the subthreshold leakage current of the device is not too large, and improve the performance of the final device.
[0041] In this embodiment, before forming the isolation structure 201, a pre-oxide layer is formed on the surface of the substrate 200 to improve the surface quality of the substrate 200 and lay a foundation for subsequent gate oxide layer formation by removing impurities and increasing a certain oxide layer.
[0042] Please continue to refer to Figure 4, discretely arranged gate layers 202 are formed on the surface of the substrate 200 in the first device region I and the second device region II, respectively.
[0043] In this embodiment, before forming the gate layer 202 , a gate oxide layer 203 is further formed on the surface of the substrate 200 .
[0044] In this embodiment, the material of the gate layer 202 is polysilicon.
[0045] Please continue to refer to Figure 4 An initial first spacer layer 204 is formed on the surface of the substrate 200 and the sidewalls and top surface of the gate layer 202 .
[0046] In this embodiment, the initial first spacer layer 204 is formed by a chemical vapor deposition process.
[0047] In other embodiments, the initial first spacer layer 204 may be formed by a physical vapor deposition process.
[0048] In this embodiment, the material of the initial first spacer layer 204 is silicon nitride.
[0049] In other embodiments, the material of the initial first spacer layer 204 may also be silicon oxide, silicon carbide, etc.
[0050] Please refer to Figure 5 , the initial first spacer layer 204 on the surface of the substrate 200 and the top surface of the gate layer 202 is removed by etching, and a first spacer 205 is formed on the sidewall of the gate layer 202 .
[0051] In this embodiment, the initial first spacer layer 204 is etched by a dry etching process to form the first spacer 205 on the sidewall of the gate layer 202 .
[0052] In this embodiment, the thickness direction of the first spacer 205 is parallel to the direction of the channel.
[0053] In this embodiment, the thickness of the first sidewall 205 cannot be too thin or too thick. The thickness (d1) of the first sidewall 205 is in the range of 55-65 angstroms. The first sidewall 205 within this thickness (d1) range can not only control the current well and reduce the leakage current, thereby improving the performance and reliability of the transistor, but also reduce the overlapping area between the bottom of the gate layer 202 of the first device region I and the lightly doped drain region in the subsequent first ion implantation process to form the lightly doped drain region, thereby avoiding conduction between the gate layer 202 and the lightly doped drain region, thereby helping to reduce leakage.
[0054] Please refer to Figure 6A first mask layer 206 is formed on the surface of the substrate 200 in the second device region II, the sidewalls of the first spacer 205 in the second device region II, and the top surface of the gate layer 202 .
[0055] In this embodiment, the material of the first mask layer 206 is photoresist.
[0056] In other embodiments, the material of the first mask layer 206 may also be other materials, such as silicon oxide.
[0057] Please continue to refer to Figure 6 , a first ion implantation is performed on the substrate 200 on both sides of the first sidewall 205 of the first device region I.
[0058] In this embodiment, the direction of the thickness is parallel to the direction of the channel.
[0059] In this embodiment, after the first ion implantation is performed on the substrate 200 , a first lightly doped drain region 207 is formed in the substrate 200 on both sides of the first sidewall 205 of the first device region I.
[0060] In this embodiment, since the overlapping surface between the first lightly doped drain region 207 and the bottom of the gate layer 202 is negatively correlated with the thickness of the first side wall 205, the overlapping surface between the first lightly doped drain region 207 and the bottom of the gate layer 202 is reasonably controlled, and the overlapping surface between the first lightly doped drain region 207 and the bottom of the gate layer 202 is minimized, reducing the formation of a path between the bottom of the gate layer 202 and the first lightly doped drain region 207, which helps to reduce leakage.
[0061] In this embodiment, the process parameters of the first ion implantation match the thickness of the first side wall 205, so that the first ion implantation forms a very precise first lightly doped drain region 207 on the surface of the substrate 200, thereby effectively controlling the size of the overlapping area between the first lightly doped drain region 207 and the bottom of the gate layer 202, thereby ensuring the performance of the formed device.
[0062] Please refer to Figure 7 , remove the first mask layer 206.
[0063] In this embodiment, an ashing process is used to remove the first mask layer 206 .
[0064] In other embodiments, an etching process may be used to remove the first mask layer 206 .
[0065] Please continue to refer to Figure 7An initial second spacer layer 208 is formed on the surface of the substrate 200 , the sidewall of the first spacer 205 , and the top surface of the gate layer 202 .
[0066] In this embodiment, the initial second spacer layer 208 is formed by a chemical vapor deposition process.
[0067] In other embodiments, the initial second spacer layer 208 may be formed by a physical vapor deposition process or an atomic layer deposition process.
[0068] In this embodiment, the material of the initial second spacer layer 208 is the same as the material of the initial first spacer layer 204 .
[0069] In other embodiments, the material of the initial second spacer layer 208 may be different from the material of the initial first spacer layer 204 .
[0070] Please refer to Figure 8 , the initial second spacer layer 208 on the surface of the substrate 200 and the top surface of the gate layer 202 is removed by etching, and a second spacer 209 is formed on the sidewall of the first spacer 205 .
[0071] In this embodiment, a dry etching process is used to etch away the initial second spacer layer 208 on the surface of the substrate 200 and the top surface of the gate layer 202 to form the second spacer 209 .
[0072] In other embodiments, a wet etching process may be used to remove the initial second spacer layer 208 on the surface of the substrate 200 and the top surface of the gate layer 202 to form the second spacer 209 .
[0073] In this embodiment, the thickness (d2) of the second sidewall spacer 209 is in the range of 20 angstroms to 30 angstroms. Within this range, the second sidewall spacer 209 can not only ensure the voltage between the gates and improve the reliability of the device, but also match the lateral diffusion distance of ions in the subsequent second ion implantation, effectively reducing the generation of device leakage, and has a wider range of applications.
[0074] Please refer to Fig. 9 A second mask layer (not shown in the figure) is formed on the surface of the substrate 200 in the first device area I, the side walls of the second sidewall 209 in the first device area I, and the top surface of the gate layer 202, and a second ion implantation is performed on the substrate 200 on both sides of the second sidewall 209 in the second device area II.
[0075] In this embodiment, after the second ion implantation is performed on the substrate 200 of the second device region II, a second lightly doped drain region 210 is formed in the substrate 200 on both sides of the second sidewall 209 of the second device region II.
[0076] In this embodiment, the material of the second mask layer is photoresist.
[0077] In this embodiment, the overlapping surface between the second lightly doped drain region 210 and the bottom of the gate layer 202 is negatively correlated with the sum of the thicknesses of the first side wall 205 and the second side wall 209. The overlapping surface between the second lightly doped drain region 210 and the bottom of the gate layer 202 is reasonably controlled, and the overlapping surface between the second lightly doped drain region 210 and the bottom of the gate layer 202 is reduced as much as possible, thereby reducing the formation of a path between the bottom of the gate layer 202 and the second lightly doped drain region 210, which helps to reduce leakage.
[0078] In this embodiment, the process parameters of the second ion implantation match the sum of the thickness of the first side wall 205 and the thickness of the second side wall 209, so that the second ion implantation forms a very precise second lightly doped drain region 210 on the surface of the substrate 200, thereby effectively controlling the size of the overlapping area between the second lightly doped drain region 210 and the bottom of the gate layer 202, thereby ensuring the performance of the formed device.
[0079] In this embodiment, after the second ion implantation is performed, the second mask layer is removed.
[0080] In this embodiment, the second mask layer is removed by an ashing process.
[0081] In this embodiment, since the lateral diffusion capabilities of ions in the first lightly doped drain region 207 and the second lightly doped drain region 210 are different, the overlapping areas of the first lightly doped drain region 207 and the second lightly doped drain region 210 with the corresponding bottom of the gate layer 202 are also different. Therefore, after forming the first side wall 205, ions are first implanted into the substrate 200 on both sides of the first side wall 205 of the first device region I; after forming the second side wall 209, ions are implanted into the substrate 200 on both sides of the second side wall 209 of the second device region II. In this way, taking into account the differences in ion diffusion effects, the performance of the device formed in the second device region II can be improved while ensuring that the performance of the device formed in the first device region I remains unchanged, and the device has a wider range of applicability.
[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first device region and a second device region adjacent to the first device region; Forming discretely arranged gate layers on the surface of the substrate in the first device region and the second device region respectively; forming a first spacer on a sidewall of the gate layer; Performing a first ion implantation on the substrate at both sides of the first sidewall of the first device region; forming a second side wall on a side wall of the first side wall; A second ion implantation is performed on the substrate at both sides of the second sidewall of the second device region.
2. The method for forming a semiconductor structure according to claim 1, wherein: After the first ion implantation, a first lightly doped drain region is formed in the substrate on both sides of the first side wall of the first device region, and the overlap surface between the first lightly doped drain region and the bottom of the gate layer is negatively correlated with the thickness of the first side wall; after the second ion implantation, a second lightly doped drain region is formed in the substrate on both sides of the second side wall of the second device region, and the overlap surface between the second lightly doped drain region and the bottom of the gate layer is negatively correlated with the sum of the thicknesses of the first side wall and the second side wall.
3. The method for forming a semiconductor structure according to claim 1, wherein: The ion type of the first ion implantation is opposite to the ion type of the second ion implantation.
4. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first sidewall spacer and performing the first ion implantation, the method further includes: forming a first mask layer on the substrate surface of the second device region, the sidewall of the first sidewall spacer of the second device region, and the top surface of the gate layer.
5. The method for forming a semiconductor structure according to claim 4, wherein: After performing the first ion implantation and before forming the second sidewall spacer, the method further includes: removing the first mask layer.
6. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second sidewall spacer and before performing the second ion implantation, the method further includes: forming a second mask layer on the substrate surface of the first device region, the sidewall of the second sidewall spacer of the first device region, and the top surface of the gate layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: After the second ion implantation is performed, the method further includes: removing the second mask layer.
8. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first spacer is in a range of 55 angstroms to 65 angstroms.
9. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second sidewall spacer is in a range of 20 angstroms to 30 angstroms.