Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with an LDMOS region and a JFET region which are adjacent in a first direction; forming an epitaxial layer on the substrate; performing first ion implantation processing on the epitaxial layer to form first well regions located in the epitaxial layer at two ends of the LDMOS region and a second well region located in the epitaxial layer on the JFET region; second ion implantation processing is carried out in the epitaxial layer and the second well region to form a second gate implantation region located in the second well region, and the second gate implantation region and the second well region at the bottom of the second gate implantation region form a first PN junction; and third ion implantation processing is carried out on the surface of the second well region to form a third gate implantation region, and the third gate implantation region and the second well region at the bottom of the third gate implantation region form a second PN junction. The width of the depletion region is controlled by the two PN junctions, so that the JFET device can be controlled to be in a channel pinch-off state under a relatively low turn-off voltage, and the turn-off voltage of the JFET device and the power consumption of the JFET device are reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Junction Field-Effect Transistor (JFET) is a commonly used semiconductor device, a type of field effect transistor (FET). JFET uses the junction as the gate of the device to control the opening and closing of the channel. When a negative junction bias is applied to the gate, both sides of the junction are depleted. When the channel is completely depleted, the device is in a channel pinch-off state and the device is cut off; conversely, the device is turned on. JFET has a higher input impedance, which can reduce the signal source load and is suitable for processing weak signals.

[0003] In the BCD process, LDMOS has strong current drive and high reverse breakdown voltage, and is suitable for handling high voltage and high current. Integrating JFET devices on the high-voltage BCD platform can improve the overall performance and efficiency of the circuit, reduce the use of external components, increase chip integration, and reduce circuit mismatch.

[0004] However, the performance of current JFET devices integrated on high-voltage BCD platforms needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is how to improve the performance of JFET devices.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has an adjacent LDMOS region and a JFET region in a first direction, wherein the first direction is parallel to the surface of the substrate; using an epitaxial growth process to form an epitaxial layer on the substrate; forming a first photoresist layer on the substrate; performing an exposure and development process on the first photoresist layer to expose the surfaces at both ends of the LDMOS region and the surface of the JFET region, thereby forming a first photoresist layer having a first well region pattern and a second well region pattern; using the first photoresist layer having the first well region pattern and the second well region pattern as a mask, performing a first ion implantation process on the epitaxial layer to form a The method comprises the steps of: forming a first well region located in the epitaxial layer at both ends of the LDMOS region and a second well region located in the epitaxial layer on the JFET region; performing a second ion implantation process in the epitaxial layer and the second well region to form a first gate implantation region located on the LDMOS region and a second gate implantation region located in the second well region, wherein the second gate implantation region forms a first PN junction with the second well region at the bottom of the second gate implantation region; performing a third ion implantation process on the surface of the second well region to form a third gate implantation region, wherein the third gate implantation region is located on the second gate implantation region, and the third gate implantation region forms a second PN junction with the second well region at the bottom of the third gate implantation region.

[0007] Optionally, the epitaxial layer has a thickness ranging from 12 microns to 15 microns.

[0008] Optionally, before the step of forming an epitaxial layer on the substrate, the step also includes: forming a second photoresist layer on the substrate; exposing and developing the second photoresist layer to form a second photoresist layer having a first buried layer pattern; using the second photoresist layer having the first buried layer pattern as a mask, performing a fourth ion implantation treatment on the substrate to form a first buried layer; performing a fifth ion implantation treatment on the substrate to form a second buried layer, wherein the ion type in the first buried layer is opposite to the ion type in the second buried layer.

[0009] Optionally, the method for forming the semiconductor structure also includes: forming a third photoresist layer on the substrate; exposing and developing the third photoresist layer to form a third photoresist layer having a first isolation structure pattern; using the third photoresist layer having the isolation structure pattern as a mask, sequentially etching the well region, the first buried layer and the substrate on the LDMOS region to form a first isolation trench; forming a fourth photoresist layer on the substrate; exposing and developing the fourth photoresist layer to form a fourth photoresist layer having a second isolation structure pattern; using the fourth photoresist layer having the isolation structure pattern as a mask, sequentially etching the well region and a portion of the second buried layer on the JFET region to form a second isolation trench; filling the first isolation trench and the second isolation trench with an insulating oxide layer and a polysilicon gate layer in turn to form a first isolation structure located in the first isolation trench and a second isolation structure located in the second isolation trench.

[0010] Optionally, the depth of the first isolation structure ranges from 20 microns to 25 microns, the depth of the second isolation structure ranges from 8 microns to 12 microns, and the first isolation structure and the second isolation structure include an insulating oxide layer and a polysilicon gate layer.

[0011] Optionally, before the step of forming the first isolation structure and the second isolation structure, it also includes: forming a fifth photoresist layer on the substrate; exposing and developing the fifth photoresist layer to form a fifth photoresist layer having a shallow isolation structure pattern; using the fifth photoresist layer having the shallow isolation structure pattern as a mask, etching the well region and the epitaxial layer to form a plurality of shallow isolation trenches; filling the shallow isolation trenches with isolation material to form a shallow isolation structure.

[0012] Optionally, the method for forming the semiconductor structure also includes: performing a sixth ion implantation treatment on the first well region and the second well region to form a third well region located on the LDMOS region and a source / drain region located on the JFET region; performing a seventh ion implantation treatment on the epitaxial layer on the LDMOS region to form a fourth well region, wherein the ion type in the third well region is opposite to the ion type in the fourth well region, and the fourth well region is electrically connected to the first gate injection region in the LDMOS region; performing an eighth ion implantation treatment on the epitaxial layer on the LDMOS region to form a drift region; and performing a ninth ion implantation treatment on the epitaxial layer between adjacent drift regions to form a high-voltage well region.

[0013] Optionally, the method for forming the semiconductor structure also includes: forming a gate material layer on the substrate; forming a sixth photoresist layer on the gate material layer; exposing and developing the sixth photoresist layer to form a sixth photoresist layer having a gate layer pattern; using the sixth photoresist layer having the gate layer pattern as a mask, etching the gate material layer to form a plurality of first gate layers located on the shallow trench isolation on the LDMOS region, on the drift region, and on the high-voltage well region, and a plurality of second gate layers located on the shallow trench isolation on the JFET region and on the second well region.

[0014] Optionally, the method for forming the semiconductor structure also includes: performing a tenth ion implantation treatment on the surface of the third well region, the surface of the drift region, a portion of the surface of the high-voltage well region, and the surface of the source / drain region to form a first lead-out region; performing an eleventh ion implantation treatment on the surface of the fourth well region, a portion of the surface of the high-voltage well region, the surface of the polysilicon gate layer in the first isolation structure, and the surface of the polysilicon gate layer in the second isolation structure to form a second lead-out region, wherein the ion type in the first lead-out region is opposite to the ion type in the second lead-out region.

[0015] Correspondingly, the technical solution of the present invention also provides a semiconductor structure including: a substrate, the substrate having adjacent LDMOS regions and JFET regions in a first direction, the first direction being parallel to the substrate surface; an epitaxial layer, the epitaxial layer being located on the substrate; a first well region, the first well region being located in the epitaxial layers at both ends of the LDMOS region; a second well region, the second well region being located in the epitaxial layer on the JFET region; a first gate injection region, the gate injection region being located in the epitaxial layer on the LDMOS region; a second gate injection region, the second gate injection region being located in the second well region, and the second gate injection region and the second well region at the bottom of the second gate injection region form a first PN junction; a third gate injection region, the third gate injection region being located on the surface of the second well region, the third gate injection region being located on the second gate injection region, and the third gate injection region and the second well region at the bottom of the third gate injection region form a second PN junction.

[0016] Optionally, the epitaxial layer has a thickness ranging from 12 microns to 15 microns.

[0017] Optionally, the semiconductor structure further includes: a first buried layer, the first buried layer being located on the LDMOS region; and a second buried layer, the second buried layer being located on the JFET region, wherein the ion type in the first buried layer is opposite to the ion type in the second buried layer.

[0018] Optionally, the semiconductor structure also includes: a first isolation structure, which is located at both ends of the LDMOS region and passes through the well region, the first buried layer and the substrate on the LDMOS region; and a second isolation structure, which is located at both ends of the JFET region and passes through the well region and a portion of the second buried layer on the JFET region.

[0019] Optionally, the depth of the first isolation structure ranges from 20 microns to 25 microns, the depth of the second isolation structure ranges from 8 microns to 12 microns, and the first isolation structure and the second isolation structure include an insulating oxide layer and a polysilicon gate layer.

[0020] Optionally, the semiconductor structure further includes: a shallow isolation structure, wherein the shallow isolation structure is located in the well region and in the epitaxial layer.

[0021] Optionally, the semiconductor structure also includes: a third well region, the third well region is located in the first well region; a source / drain region, the source / drain region is located in the second well region; a fourth well region, the fourth well region is located in the epitaxial layer on the LDMOS region, wherein the ion type in the third well region is opposite to the ion type in the fourth well region, and the fourth well region is electrically connected to the first gate injection region in the LDMOS region; a drift region, the drift region is located in the epitaxial layer on the LDMOS region; and a high-voltage well region, the high-voltage well region is located in the epitaxial layer between adjacent drift regions.

[0022] Optionally, the semiconductor structure also includes: a first gate layer, the first gate layer is located on the shallow trench isolation on the LDMOS region, on the drift region and on the high-voltage well region; a second gate layer, the second gate layer is located on the shallow trench isolation on the JFET region and on the second well region.

[0023] Optionally, the semiconductor structure also includes: a first lead-out region, the first lead-out region is located on the surface of the third well region, the surface of the drift region, a portion of the surface of the high-voltage well region, and the surface of the source / drain region; a second lead-out region is located on the surface of the fourth well region, a portion of the surface of the high-voltage well region, the surface of the polysilicon gate layer in the first isolation structure, and the surface of the polysilicon gate layer in the second isolation structure, and the ion type in the first lead-out region is opposite to the ion type in the second lead-out region.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] The method for forming the semiconductor structure in the technical solution of the present invention forms a second gate injection region in the second well region, and the second gate injection region forms a first PN junction with the second well region at the bottom of the second gate injection region; forms a third gate injection region on the surface of the second well region, and the third gate injection region forms a second PN junction with the second well region at the bottom of the third gate injection region, so as to achieve control of the width of the depletion region by two PN junctions in a JFET device, thereby controlling the opening or pinching off of the JFET device, thereby enabling the JFET device to be controlled to be in a channel pinching-off state at a lower turn-off voltage, reducing the turn-off voltage of the JFET device and the power consumption of the JFET device, and improving the performance of the JFET device; in addition, the first gate injection region in the LDMOS region and the second gate injection region in the JFET region in the present invention are formed simultaneously, reducing additional process steps and reducing process costs.

[0026] Furthermore, the technical solution of the present invention realizes isolation between adjacent devices through a first isolation structure and a second isolation structure having an insulating oxide layer and a polysilicon gate layer, thereby ensuring electrical isolation between adjacent devices on a high-voltage BCD platform, thereby improving the reliability of the device.

[0027] In the semiconductor structure described in the technical solution of the present invention, the second gate injection region is located in the second well region, and the second gate injection region forms a first PN junction with the second well region at the bottom of the second gate injection region; the third gate injection region is located on the surface of the second well region, and the third gate injection region forms a second PN junction with the second well region at the bottom of the third gate injection region, so that the width of the depletion region is controlled by two PN junctions in a JFET device, thereby controlling the opening or pinching off of the JFET device, thereby enabling the JFET device to control the JFET device to be in a channel pinching-off state at a lower turn-off voltage, reducing the turn-off voltage of the JFET device and the power consumption of the JFET device, and improving the performance of the JFET device; in addition, the first gate injection region in the LDMOS region and the second gate injection region of the JFET region in the present invention are formed simultaneously, reducing additional process steps and reducing process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0029] Figures 2 to 8 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0031] Please refer to Figure 1 , Figure 1 The present invention is a schematic diagram of a formation process of a semiconductor structure, comprising: providing a substrate (not shown in the figure); performing ion implantation on the substrate to form a buried layer 100; using an epitaxial growth process to form an epitaxial layer on the substrate; performing ion implantation on the epitaxial layer to form a well region 101; performing ion implantation on the epitaxial layer to form a doped region 102, wherein the doped region 102 forms a PN junction with the well region 101 at the bottom of the doped region 102; performing ion implantation on the well region 101 on both sides of the doped region 102 to form a source / drain region 103; and forming a gate layer 104 on the well region 101 between the doped region 102 and the source / drain region 103.

[0032] In this embodiment, the thickness of the well region 101 ranges from 4 micrometers to 6 micrometers.

[0033] In this embodiment, the method for forming the semiconductor structure is used to form a JFET device. JFET uses a junction as the gate of the device to control the opening and closing of the channel. When a negative junction bias is applied to the gate, both sides of the junction are depleted. When the channel is completely depleted, the device is in a channel pinch-off state and the device is cut off. On the contrary, the device is turned on. JFET has a higher input impedance, which can reduce the signal source load and is suitable for processing weak signals.

[0034] It can be seen from the above scheme that currently in the high-voltage BCD process, such as the BCD platform with a voltage range of 60V to 120V, the formation of the epitaxial layer needs to be thickened to 12 microns to 19 microns, which makes the subsequently formed JFET device require a large gate-source voltage to pinch off the channel (or even fail to pinch off), resulting in high power consumption of the JFET device and reduced performance of the JFET device.

[0035] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, wherein a second gate injection region is formed in a second well region, and the second gate injection region forms a first PN junction with the second well region at the bottom of the second gate injection region; a third gate injection region is formed on the surface of the second well region, and the third gate injection region forms a second PN junction with the second well region at the bottom of the third gate injection region, so that the width of the depletion region is controlled by two PN junctions in a JFET device, thereby controlling the opening or pinching off of the JFET device, thereby enabling the JFET device to be controlled to be in a channel pinching-off state at a lower turn-off voltage, thereby reducing the turn-off voltage of the JFET device and the power consumption of the JFET device, and improving the performance of the JFET device; in addition, the first gate injection region in the LDMOS region and the second gate injection region in the JFET region in the present invention are formed simultaneously, thereby reducing additional process steps and reducing process costs.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Please refer to Figure 2 , providing a substrate 200 , wherein the substrate 200 has adjacent LDMOS regions and JFET regions in a first direction X, and the first direction X is parallel to a surface of the substrate 200 .

[0038] In this embodiment, the material of the substrate 200 is silicon.

[0039] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0040] In some embodiments of the present invention, the LDMOS region is used to form an LDMOS device, and the JFET region is used to form a JFET device.

[0041] In some embodiments of the present invention, it also includes: forming a second photoresist layer (not shown in the figure) on the substrate 200; exposing and developing the second photoresist layer to form a second photoresist layer having a first buried layer 202 pattern; using the second photoresist layer having the first buried layer 202 pattern as a mask, performing a fourth ion implantation treatment on the substrate 200 to form the first buried layer 202; performing a fifth ion implantation treatment on the substrate 200 to form a second buried layer 201, wherein the ion type in the first buried layer 202 is opposite to the ion type in the second buried layer 201.

[0042] The first buried layer 202 is located on the LDMOS region, and the second buried layer 201 is located on the JFET region.

[0043] In some embodiments of the present invention, the implantation concentration range of the fourth ion implantation process is 1E14 ions / cm 2 To 1E15 ions / cm 2 The implantation concentration range of the fifth ion implantation treatment is 1E12 ions / cm 2 To 1E13ions / cm 2 .

[0044] The ion type of the fourth ion implantation process is opposite to the ion type of the fifth ion implantation process.

[0045] In some embodiments of the present invention, the type of the first ion is N-type, and the type of the second ion is P-type.

[0046] Among them, when the ion type in the first buried layer 202 is N-type, the first buried layer 202 is a boron nitride buried layer NBL, and the boron nitride buried layer NBL is used to reduce parasitic resistance effects and prevent impurity ions from penetrating from the wafer surface into the device structure, thereby improving the performance stability and reliability of the device; when the ion type in the second buried layer 201 is P-type, the second buried layer 201 is a boron phosphide buried layer PBL, and the boron phosphide buried layer PBL is used to provide a conductivity type opposite to that of the boron nitride buried layer NBL to achieve specific circuit functions or isolation requirements. The boron phosphide buried layer PBL is used in combination with the boron nitride buried layer NBL to further reduce parasitic effects and improve device performance.

[0047] In other embodiments, the type of the first ion is P type, and the type of the second ion is N type.

[0048] Please refer to Figure 3 , an epitaxial layer 203 is formed on the substrate 200 using an epitaxial growth process.

[0049] In some embodiments of the present invention, the thickness of the epitaxial layer 203 is in a range of 12 micrometers to 15 micrometers.

[0050] In this embodiment, the method for forming the epitaxial layer 203 is a vapor phase epitaxial process, and the process parameters of the vapor phase epitaxial process are: an epitaxial rate of 0.1 μm / min-0.5 μm / min, and an epitaxial time of 3 seconds to 10 seconds.

[0051] The epitaxial layer 203 is a P-type semiconductor or an N-type semiconductor.

[0052] Please refer to Figure 4 , forming a first photoresist layer (not shown in the figure) on the substrate 200; performing exposure and development treatment on the first photoresist layer until the surfaces at both ends of the LDMOS region and the surface of the JFET region are exposed, forming a first photoresist layer (not shown in the figure) having a first well region 2031 pattern and a second well region 2032 pattern; using the first photoresist layer having the first well region 2031 pattern and the second well region 2032 pattern as a mask, performing a first ion implantation treatment on the epitaxial layer 203, forming a first well region 2031 located in the epitaxial layer 203 at both ends of the LDMOS region, and a second well region 2032 located in the epitaxial layer 203 on the JFET region.

[0053] In some embodiments of the present invention, the concentration range of the first ion implantation process is 2.0E4 ions / cm 2 To 5.0E7 ions / cm 2 , the implanted ion type is P type or N type.

[0054] In other embodiments, after the step of forming the first well region and the second well region, the step further includes: annealing the first well region, the second well region and the epitaxial layer. Since high-energy ions bombard the silicon wafer during the first ion implantation process, the lattice structure is destroyed to form an amorphous region. The annealing treatment can rearrange the atoms in the amorphous region through high-temperature treatment to restore the order of the lattice.

[0055] Please refer to Figure 5 , forming a fifth photoresist layer (not shown in the figure) on the substrate 200; exposing and developing the fifth photoresist layer to form a fifth photoresist layer having a shallow isolation structure 204 pattern; using the fifth photoresist layer having the shallow isolation structure 204 pattern as a mask, etching the well region and the epitaxial layer 203 to form a plurality of shallow isolation trenches (not shown in the figure); filling the shallow isolation trenches with isolation material to form a shallow isolation structure 204.

[0056] In some embodiments of the present invention, the process of forming the shallow isolation trench is: etching the well region and the epitaxial layer 203 using a dry etching process.

[0057] In some embodiments of the present invention, the shallow isolation trench is used to accommodate a shallow isolation structure 204 formed subsequently.

[0058] In some embodiments of the present invention, the depth of the shallow isolation trench ranges from 0.3 micrometers to 0.35 micrometers.

[0059] In this embodiment, the process of filling the shallow isolation trench with isolation material to form the shallow isolation structure 204 is one or more of thermal oxidation, rapid thermal annealing, chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition.

[0060] After the step of forming the shallow isolation structure 204 , the method further includes: performing a planarization process on the shallow isolation structure 204 .

[0061] In this embodiment, the planarization method includes: a chemical mechanical polishing process.

[0062] In this embodiment, the material of the shallow isolation structure 204 includes silicon oxide.

[0063] In some embodiments of the present invention, an active region 205 is located between adjacent shallow isolation structures 204 .

[0064] Please refer to Figure 6, forming a third photoresist layer (not shown in the figure) on the substrate 200; exposing and developing the third photoresist layer to form a third photoresist layer having a first isolation structure 206 pattern; using the third photoresist layer having the isolation structure pattern as a mask, sequentially etching the well region on the LDMOS region, the first buried layer 202 and the substrate 200 to form a first isolation trench (not shown in the figure); forming a fourth photoresist layer (not shown in the figure) on the substrate 200; exposing and developing the fourth photoresist layer to form a fourth photoresist layer having a second isolation structure 207 pattern; using the fourth photoresist layer having the isolation structure pattern as a mask, sequentially etching the well region on the JFET region and a portion of the second buried layer 201 to form a second isolation trench (not shown in the figure); sequentially filling the first isolation trench and the second isolation trench with an insulating oxide layer and a polysilicon gate layer to form a first isolation structure 206 located in the first isolation trench and a second isolation structure 207 located in the second isolation trench.

[0065] In some embodiments of the present invention, the depth of the first isolation structure 206 ranges from 20 micrometers to 25 micrometers, and the depth of the second isolation structure 207 ranges from 8 micrometers to 12 micrometers.

[0066] In some embodiments of the present invention, the process for forming the first isolation trench and the second isolation trench is a dry etching process, and the process parameters of the dry etching process are: the chamber pressure is 5 mT to 15 mT, the source power is 350W to 1200W, the bias voltage is 150 V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

[0067] Specifically, the process for forming the first isolation trench is: using a dry etching process to etch the first buried layer 202 and the substrate 200 to form a first isolation trench; the process for forming the second isolation trench is: using a dry etching process to etch the well region on the JFET region and part of the second buried layer 201 to form a second isolation trench.

[0068] In a specific embodiment, the first isolation structure 206 includes: a first insulating oxide layer 2061 located on the side wall surface of the first isolation trench, and a first polysilicon gate layer 2062 located between adjacent first insulating oxide layers 2061; the second isolation structure 207 includes: a second insulating oxide layer 2071 located on the side wall surface of the second isolation trench, and a second polysilicon gate layer 2072 located between adjacent second insulating oxide layers 2071.

[0069] In the above scheme, the technical solution of the present invention realizes isolation between adjacent devices through the first isolation structure 206 and the second isolation structure 207 having an insulating oxide layer and a polysilicon gate layer, thereby ensuring electrical isolation between adjacent devices on a high-voltage BCD platform, thereby improving device reliability.

[0070] Please refer to Figure 7 , performing a sixth ion implantation process on the first well region 2031 and the second well region 2032 to form a third well region 2081 located on the LDMOS region and a source / drain region 2082 located on the JFET region; performing a seventh ion implantation process on the epitaxial layer 203 on the LDMOS region to form a fourth well region 209, wherein the ion type in the third well region 2081 is opposite to the ion type in the fourth well region 209, and the fourth well region 209 is electrically connected to the first gate implantation region 212 in the LDMOS region; performing an eighth ion implantation process on the epitaxial layer 203 on the LDMOS region to form a drift region 210; performing a ninth ion implantation process on the epitaxial layer 203 between adjacent drift regions 210 to form a high-voltage well region 211.

[0071] In some embodiments of the present invention, the implantation concentration range of the sixth ion implantation treatment is 1.5E12ions / cm 2 Up to 2.5E12 ions / cm 2 The ion type of the sixth ion implantation process is N-type, and the epitaxial layer 203 is a P-type semiconductor.

[0072] The ion type of the sixth ion implantation process is opposite to the semiconductor type of the epitaxial layer 203 .

[0073] In some embodiments of the present invention, the seventh ion implantation treatment has an implantation concentration range of 1E12 ions / cm 2 To 1E13 ions / cm 2 , the ion type of the seventh ion implantation treatment is N type.

[0074] The ion type of the seventh ion implantation process is the same as the ion type of the sixth ion implantation process.

[0075] In some embodiments of the present invention, the implantation concentration range of the eighth ion implantation process is 1E12 ions / cm 2 To 5E12 ions / cm 2 .

[0076] In some embodiments of the present invention, the ninth ion implantation treatment has an implantation concentration range of 1E12 ions / cm 2to 7E13 ions / cm 2 .

[0077] In some embodiments of the present invention, the drift region 210 is used to improve the voltage resistance of the device. When the LDMOS device is in the cut-off state, the depletion layer mainly expands in the drift region 210, thereby improving the breakdown voltage of the device.

[0078] In some embodiments of the present invention, the high-voltage well region 211 is used to isolate different voltage regions, prevent leakage current or noise in the high-voltage region from propagating to the low-voltage region through the substrate 200, thereby protecting low-voltage devices and circuits, and is used to withstand high voltage so that the LDMOS device can operate normally under high voltage.

[0079] In some embodiments of the present invention, it also includes: performing a second ion implantation process on the epitaxial layer 203 and the second well region 2032 to form a first gate implantation region 212 located on the LDMOS region, and a second gate implantation region 213 located in the second well region 2032, and the second gate implantation region 213 forms a first PN junction with the second well region 2032 at the bottom of the second gate implantation region 213.

[0080] The second ion implantation treatment has an implantation concentration range of 2E12 ions / cm 2 To 5E12 ions / cm 2 .

[0081] Please refer to Figure 8 , forming a gate material layer on the substrate 200; forming a sixth photoresist layer (not shown in the figure) on the gate material layer; exposing and developing the sixth photoresist layer to form a sixth photoresist layer having a gate layer pattern; using the sixth photoresist layer having the gate layer pattern as a mask, etching the gate material layer to form a plurality of first gate layers 2171 located on the shallow trench isolation on the LDMOS region, on the drift region 210 and on the high-voltage well region 211, and a plurality of second gate layers 2172 located on the shallow trench isolation on the JFET region and on the second well region 2032.

[0082] In a specific embodiment, a gate oxide material layer (not shown in the figure) is formed on the substrate 200; a gate material layer (not shown in the figure) is formed on the gate oxide material layer; a photolithography process is adopted, and a sixth photoresist layer having a gate layer pattern is used as a mask to sequentially etch the gate oxide material layer and the gate material layer to form a plurality of first gate layers 2171 and a plurality of second gate layers 2172, as well as a gate oxide layer (not shown in the figure) located at the bottom of the first gate layer 2171 and the plurality of second gate layers 2172.

[0083] In this embodiment, the thickness of the gate oxide layer ranges from 120 angstroms to 150 angstroms.

[0084] In this embodiment, the material of the gate oxide layer is silicon nitride, silicon oxide or borophosphosilicate glass.

[0085] In this embodiment, the material of the first gate layer 2171 and the second gate layer 2172 is single crystal silicon or polycrystalline silicon.

[0086] In other embodiments, after the step of forming the first gate layer and the second gate layer, the step further includes: depositing a sidewall structure on the sidewall surfaces of the first gate layer and the second gate layer.

[0087] The process method for forming the sidewall structure is a chemical vapor deposition process or a physical vapor deposition process; the material of the sidewall structure is silicon nitride and silicon oxide.

[0088] In some embodiments of the present invention, it also includes: performing a tenth ion implantation treatment on the surface of the third well region 2081, the surface of the drift region 210, a portion of the surface of the high-voltage well region 211, and the surface of the source / drain region 2082 to form a first lead-out region 214; performing an eleventh ion implantation treatment on the surface of the fourth well region 209, a portion of the surface of the high-voltage well region 211, the surface of the polysilicon gate layer in the first isolation structure 206, and the surface of the polysilicon gate layer in the second isolation structure 207 to form a second lead-out region 216, and the ion type in the first lead-out region 214 is opposite to the ion type in the second lead-out region 216.

[0089] In some embodiments of the present invention, it also includes: performing a third ion implantation treatment on the surface of the second well region 2032 to form a third gate implantation region 215, wherein the third gate implantation region 215 is located on the second gate implantation region 213, and the third gate implantation region 215 forms a second PN junction with the second well region 2032 at the bottom of the third gate implantation region 215.

[0090] The implantation concentration range of the tenth ion implantation treatment is 1E14 ions / cm 2 To 6E15 ions / cm 2 The implantation concentration range of the eleventh ion implantation treatment is 1E13 ions / cm 2 To 3E15 ions / cm 2 The implantation concentration range of the third ion implantation treatment is 1E13 ions / cm 2 To 3E15 ions / cm 2 .

[0091] In a specific embodiment, when a reverse voltage is applied between the gate (not shown in the figure) and the source / drain region 2082 on the JFET region, the first PN junction and the second PN junction will be reverse biased, resulting in the formation of a depletion region. As the reverse voltage increases, the depletion region continues to expand until the channel is completely depleted and the channel resistance tends to infinity. The gate voltage at this time is called the pinch-off voltage. When the gate voltage reaches the pinch-off voltage, the depletion region completely covers the channel, electrons cannot pass through the depletion region, and the drain current is zero. This state is called pinch-off or cut-off.

[0092] In some embodiments of the present invention, the length and width of the second gate implantation region 213 can be optimized according to simulation data and silicon data to achieve a suitable pinch-off voltage and a breakdown voltage BV of the JFET device.

[0093] In the above scheme, when the thickness of the epitaxial layer 203 is 12 microns to 15 microns, the width of the depletion region is controlled by two PN junctions, thereby controlling the opening or pinching off of the JFET device, so that the JFET device can be controlled to be in a channel pinching-off state at a lower turn-off voltage, thereby reducing the turn-off voltage of the JFET device and the power consumption of the JFET device, and improving the performance of the JFET device; and the first gate injection region 212 in the LDMOS region and the second gate injection region 213 in the JFET region in the present invention are formed at the same time, reducing additional process steps and reducing process costs.

[0094] Accordingly, the present invention also provides a semiconductor structure, please refer to Figure 8 , comprising: a substrate 200, the substrate 200 having adjacent LDMOS regions and JFET regions in a first direction X, the first direction X being parallel to the surface of the substrate 200; an epitaxial layer 203, the epitaxial layer 203 being located on the substrate 200; a first well region 2031, the first well region 2031 being located in the epitaxial layer 203 at both ends of the LDMOS region; a second well region 2032, the second well region 2032 being located in the epitaxial layer 203 on the JFET region; a first gate injection region 212, the gate injection region being located in the epitaxial layer 203 on the LDMOS region 03; a second gate injection region 213, the second gate injection region 213 is located in the second well region 2032, and the second gate injection region 213 forms a first PN junction with the second well region 2032 at the bottom of the second gate injection region 213; a third gate injection region 215, the third gate injection region 215 is located on the surface of the second well region 2032, the third gate injection region 215 is located on the second gate injection region 213, and the third gate injection region 215 forms a second PN junction with the second well region 2032 at the bottom of the third gate injection region 215.

[0095] In some embodiments of the present invention, the thickness of the epitaxial layer 203 is in a range of 12 micrometers to 15 micrometers.

[0096] In some embodiments of the present invention, the semiconductor structure also includes: a first isolation structure 206, the first isolation structure 206 is located at both ends of the LDMOS region, and the first isolation structure 206 penetrates the well region on the LDMOS region, the first buried layer 202 and the substrate 200; a second isolation structure 207, the second isolation structure 207 is located at both ends of the JFET region, and the second isolation structure 207 penetrates the well region on the JFET region and a portion of the second buried layer 201.

[0097] In some embodiments of the present invention, the semiconductor structure also includes: the depth of the first isolation structure 206 ranges from 20 microns to 25 microns, the depth of the second isolation structure 207 ranges from 8 microns to 12 microns, and the first isolation structure 206 and the second isolation structure 207 include an insulating oxide layer and a polysilicon gate layer.

[0098] In the above solution, isolation between adjacent devices is achieved through the first isolation structure 206 and the second isolation structure 207 having an insulating oxide layer and a polysilicon gate layer, thereby ensuring electrical isolation between adjacent devices on a high-voltage BCD platform, thereby improving device reliability.

[0099] In some embodiments of the present invention, the semiconductor structure further includes: a shallow isolation structure 204 , wherein the shallow isolation structure 204 is located in the well region and in the epitaxial layer 203 .

[0100] In some embodiments of the present invention, the semiconductor structure also includes: a third well region 2081, wherein the third well region 2081 is located in the first well region 2031; a source / drain region 2082, wherein the source / drain region 2082 is located in the second well region 2032; a fourth well region 209, wherein the fourth well region 209 is located in the epitaxial layer 203 on the LDMOS region, wherein the ion type in the third well region 2081 is opposite to the ion type in the fourth well region 209, and the fourth well region 209 is electrically connected to the first gate injection region 212 in the LDMOS region; a drift region 210, wherein the drift region 210 is located in the epitaxial layer 203 on the LDMOS region; and a high-voltage well region 211, wherein the high-voltage well region 211 is located in the epitaxial layer 203 between adjacent drift regions 210.

[0101] In some embodiments of the present invention, the semiconductor structure also includes: a first gate layer 2171, the first gate layer 2171 is located on the shallow trench isolation on the LDMOS region, on the drift region 210 and on the high-voltage well region 211; a second gate layer 2172, the second gate layer 2172 is located on the shallow trench isolation on the JFET region and on the second well region 2032.

[0102] In some embodiments of the present invention, the semiconductor structure also includes: a first lead-out region 214, the first lead-out region 214 is located on the surface of the third well region 2081, the surface of the drift region 210, part of the surface of the high-voltage well region 211 and the surface of the source / drain region 2082; a second lead-out region 216, located on the surface of the fourth well region 209, part of the surface of the high-voltage well region 211, the surface of the polysilicon gate layer in the first isolation structure 206 and the surface of the polysilicon gate layer in the second isolation structure 207, and the ion type in the first lead-out region 214 is opposite to the ion type in the second lead-out region 216.

[0103] In summary, the second gate injection region 213 is located in the second well region 2032, and the second gate injection region 213 forms a first PN junction with the second well region 2032 at the bottom of the second gate injection region 213; the third gate injection region 215 is located on the surface of the second well region 2032, and the third gate injection region 215 forms a second PN junction with the second well region 2032 at the bottom of the third gate injection region 215, so that the width of the depletion region is controlled by two PN junctions in a JFET device, thereby controlling the opening or pinching off of the JFET device, thereby enabling the JFET device to control the JFET device to be in a channel pinching-off state at a lower turn-off voltage, reducing the turn-off voltage of the JFET device and the power consumption of the JFET device, and improving the performance of the JFET device; in addition, the first gate injection region 212 in the LDMOS region and the second gate injection region 213 in the JFET region in the present invention are formed simultaneously, reducing additional process steps and reducing process costs.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has an LDMOS region and a JFET region adjacent to each other in a first direction, wherein the first direction is parallel to a surface of the substrate; forming an epitaxial layer on the substrate by using an epitaxial growth process; forming a first photoresist layer on the substrate; Performing exposure and development processing on the first photoresist layer until the surfaces at both ends of the LDMOS region and the surface of the JFET region are exposed, so as to form a first photoresist layer having a first well region pattern and a second well region pattern; Using a first photoresist layer having a first well region pattern and a second well region pattern as a mask, performing a first ion implantation process on the epitaxial layer to form a first well region located in the epitaxial layer at both ends of the LDMOS region and a second well region located in the epitaxial layer on the JFET region; Performing a second ion implantation process in the epitaxial layer and the second well region to form a first gate implantation region located on the LDMOS region and a second gate implantation region located in the second well region, wherein the second gate implantation region forms a first PN junction with the second well region at the bottom of the second gate implantation region; A third ion implantation process is performed on the surface of the second well region to form a third gate implantation region, wherein the third gate implantation region is located on the second gate implantation region and forms a second PN junction with the second well region at the bottom of the third gate implantation region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the epitaxial layer is in a range of 12 micrometers to 15 micrometers.

3. The method for forming a semiconductor structure according to claim 1, wherein: Before the step of forming an epitaxial layer on the substrate, the method further comprises: forming a second photoresist layer on the substrate; exposing and developing the second photoresist layer to form a second photoresist layer having a first buried layer pattern; Using the second photoresist layer having the first buried layer pattern as a mask, performing a fourth ion implantation process on the substrate to form a first buried layer; A fifth ion implantation process is performed on the substrate to form a second buried layer, wherein the ion type in the first buried layer is opposite to the ion type in the second buried layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: forming a third photoresist layer on the substrate; exposing and developing the third photoresist layer to form a third photoresist layer having a first isolation structure pattern; Using the third photoresist layer having the isolation structure pattern as a mask, sequentially etching the well region on the LDMOS region, the first buried layer and the substrate to form a first isolation trench; forming a fourth photoresist layer on the substrate; exposing and developing the fourth photoresist layer to form a fourth photoresist layer having a second isolation structure pattern; Using the fourth photoresist layer having the isolation structure pattern as a mask, sequentially etching the well region on the JFET region and a portion of the second buried layer to form a second isolation trench; An insulating oxide layer and a polysilicon gate layer are sequentially filled into the first isolation trench and the second isolation trench to form a first isolation structure located in the first isolation trench and a second isolation structure located in the second isolation trench.

5. The method for forming a semiconductor structure according to claim 4, wherein: The depth of the first isolation structure ranges from 20 microns to 25 microns, and the depth of the second isolation structure ranges from 8 microns to 12 microns. The first isolation structure and the second isolation structure include an insulating oxide layer and a polysilicon gate layer.

6. The method for forming a semiconductor structure according to claim 4, wherein: Before the step of forming the first isolation structure and the second isolation structure, the method further includes: forming a fifth photoresist layer on the substrate; exposing and developing the fifth photoresist layer to form a fifth photoresist layer having a shallow isolation structure pattern; Using the fifth photoresist layer having the shallow isolation structure pattern as a mask, etching the well region and the epitaxial layer to form a plurality of shallow isolation trenches; An isolation material is filled into the shallow isolation trench to form a shallow isolation structure.

7. The method for forming a semiconductor structure according to claim 4, wherein: Also includes: Performing a sixth ion implantation process in the first well region and the second well region to form a third well region located on the LDMOS region and a source / drain region located on the JFET region; Performing a seventh ion implantation process in the epitaxial layer on the LDMOS region to form a fourth well region, wherein the ion type in the third well region is opposite to the ion type in the fourth well region, and the fourth well region is electrically connected to the first gate implantation region in the LDMOS region; Performing an eighth ion implantation process in the epitaxial layer on the LDMOS region to form a drift region; A ninth ion implantation process is performed in the epitaxial layer between adjacent drift regions to form a high-voltage well region.

8. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: forming a gate material layer on the substrate; forming a sixth photoresist layer on the gate material layer; exposing and developing the sixth photoresist layer to form a sixth photoresist layer having a gate layer pattern; Using the sixth photoresist layer having a gate layer pattern as a mask, the gate material layer is etched to form a plurality of first gate layers located on the shallow trench isolation on the LDMOS region, on the drift region and on the high-voltage well region, and a plurality of second gate layers located on the shallow trench isolation on the JFET region and on the second well region.

9. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: Performing a tenth ion implantation process on the surface of the third well region, the surface of the drift region, a portion of the surface of the high-voltage well region, and the surface of the source / drain region to form a first lead-out region; An eleventh ion implantation treatment is performed on the surface of the fourth well region, a portion of the surface of the high-voltage well region, the surface of the polysilicon gate layer in the first isolation structure, and the surface of the polysilicon gate layer in the second isolation structure to form a second lead-out region, wherein the ion type in the first lead-out region is opposite to the ion type in the second lead-out region.

10. A semiconductor structure, characterized in that: include: A substrate having an LDMOS region and a JFET region adjacent to each other in a first direction, wherein the first direction is parallel to a surface of the substrate; an epitaxial layer, the epitaxial layer being located on the substrate; A first well region, wherein the first well region is located in the epitaxial layer at both ends of the LDMOS region; a second well region, the second well region being located in the epitaxial layer on the JFET region; A first gate injection region, the gate injection region being located in an epitaxial layer on the LDMOS region; a second gate injection region, wherein the second gate injection region is located in the second well region, and the second gate injection region forms a first PN junction with the second well region at the bottom of the second gate injection region; A third gate injection region, the third gate injection region is located on the surface of the second well region, the third gate injection region is located on the second gate injection region, and the third gate injection region forms a second PN junction with the second well region at the bottom of the third gate injection region.

11. The semiconductor structure according to claim 10, wherein: The thickness of the epitaxial layer is in a range of 12 micrometers to 15 micrometers.

12. The semiconductor structure according to claim 10, wherein: Also includes: a first buried layer, wherein the first buried layer is located on the LDMOS region; A second buried layer, wherein the second buried layer is located on the JFET region, wherein the ion type in the first buried layer is opposite to the ion type in the second buried layer.

13. The semiconductor structure according to claim 12, wherein: Also includes: a first isolation structure, wherein the first isolation structure is located at two ends of the LDMOS region, and the first isolation structure runs through the well region on the LDMOS region, the first buried layer, and the substrate; A second isolation structure is located at two ends of the JFET region, and the second isolation structure runs through the well region on the JFET region and a portion of the second buried layer.

14. The semiconductor structure according to claim 13, wherein: The depth of the first isolation structure ranges from 20 microns to 25 microns, and the depth of the second isolation structure ranges from 8 microns to 12 microns. The first isolation structure and the second isolation structure include an insulating oxide layer and a polysilicon gate layer.

15. The semiconductor structure according to claim 13, wherein: Also includes: A shallow isolation structure is located in the well region and in the epitaxial layer.

16. The semiconductor structure according to claim 13, wherein: Also includes: a third well region, the third well region being located in the first well region; a source / drain region, the source / drain region being located in the second well region; a fourth well region, the fourth well region being located in the epitaxial layer on the LDMOS region, wherein the ion type in the third well region is opposite to the ion type in the fourth well region, and the fourth well region is electrically connected to the first gate implantation region in the LDMOS region; A drift region, wherein the drift region is located in an epitaxial layer on the LDMOS region; A high-voltage well region is located in the epitaxial layer between adjacent drift regions.

17. The semiconductor structure according to claim 16, wherein: Also includes: A first gate layer, wherein the first gate layer is located on the shallow trench isolation on the LDMOS region, on the drift region, and on the high-voltage well region; A second gate layer is located on the shallow trench isolation on the JFET region and on the second well region.

18. The semiconductor structure according to claim 17, wherein: Also includes: A first lead-out region, the first lead-out region is located on the surface of the third well region, the surface of the drift region, a portion of the surface of the high-voltage well region, and the surface of the source / drain region; The second lead-out region is located on the surface of the fourth well region, part of the surface of the high-voltage well region, the surface of the polysilicon gate layer in the first isolation structure, and the surface of the polysilicon gate layer in the second isolation structure. The ion type in the first lead-out region is opposite to the ion type in the second lead-out region.

Images