Preparation method of semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure, and the method comprises the steps: forming a substrate which covers an NMOS region, a first sacrificial gate, a first mask layer, a substrate which covers a PMOS region, and a target anti-reflection coating which covers a part of the side wall of a second sacrificial gate, after the thickness of the target anti-reflection coating on the top surface of the substrate in the PMOS region is equal to that of the target anti-reflection coating on the top surface of the first mask layer, removing part of the target anti-reflection coating, and exposing the top surface of the substrate in the PMOS region and the top surface of the first mask layer; removing part of the target reflective coating to expose the top surface of the substrate in the PMOS region and the top surface of the first mask layer; etching the substrate at the two sides of the second sacrificial gate in the PMOS region, forming a groove in the substrate, and etching to remove the residual target anti-reflection coating, the first mask layer with partial thickness and the second mask layer with partial thickness in the NMOS region at the same time; and forming a silicon germanium layer in the groove. The technological process is simplified, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] In the manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, improving the performance of MOS transistors through stress has become an increasingly common method. Specifically, by properly controlling stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, thereby increasing the drive current, thereby greatly improving the performance of MOS transistors.

[0003] At present, embedded silicon germanium (Embedded SiGe) technology is used to improve the mobility of holes in the channel region of the PMOS transistor, that is, grooves are first formed in the area where the source region and the drain region need to be formed, and then a silicon germanium layer is formed in the groove. The silicon germanium layer is formed to introduce compressive stress formed by the lattice mismatch between silicon and silicon germanium (SiGe) to improve the performance of the PMOS transistor.

[0004] When the existing semiconductor device is manufactured, the PMOS transistor and the NMOS transistor are manufactured synchronously in the PMOS region and the NMOS region of the substrate respectively. During the manufacturing process, after the grooves and the silicon germanium layer located in the grooves are formed in the substrate on both sides of the sacrificial gate structure of the PMOS region, the height of the sacrificial gate of the PMOS region and the height of the sacrificial gate of the NMOS region will be inconsistent, which seriously affects the subsequent process and process integration. At this time, additional masking process and etching process are required to flatten the height difference of the sacrificial gate of the PMOS region and the sacrificial gate of the NMOS region, but this will increase the cost, affect the efficiency, and the effect is not good.

[0005] ‌ Summary of the invention

[0006] Based on this, the present application provides a method for preparing a semiconductor structure, which ensures that the height of the first sacrificial gate in the NMOS region and the second sacrificial gate in the PMOS region are consistent when a silicon germanium layer is formed in the PMOS region, while simplifying the process flow, increasing efficiency, reducing costs, and improving the effect.

[0007] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, including:

[0008] Providing a substrate, the substrate comprising an NMOS region and a PMOS region, the top surface of the NMOS region comprising a first sacrificial gate and a first mask layer sequentially stacked along a first direction perpendicular to the top surface of the substrate, the top surface of the PMOS region comprising a second sacrificial gate and a second mask layer sequentially stacked along the first direction, the thickness of the first sacrificial gate is the same as the thickness of the second sacrificial gate, and the material and thickness of the first mask layer are the same as the material and thickness of the second mask layer;

[0009] Forming a target anti-reflection coating, wherein the target anti-reflection coating covers the substrate of the NMOS region, the first sacrificial gate, the first mask layer, the substrate of the PMOS region, and a portion of the sidewall of the second sacrificial gate, and the thickness of the target anti-reflection coating on the top surface of the substrate of the PMOS region is equal to the thickness of the target anti-reflection coating on the top surface of the first mask layer;

[0010] removing a portion of the target reflective coating to expose a top surface of the substrate in the PMOS region and a top surface of the first mask layer;

[0011] Etching the substrate on both sides of the second sacrificial gate of the PMOS region to form a groove in the substrate, and simultaneously etching away a portion of the thickness of the first mask layer, a portion of the thickness of the second mask layer, and the remaining target anti-reflection coating of the NMOS region;

[0012] A silicon germanium layer is formed in the groove.

[0013] In some embodiments of the present application, the substrate of the NMOS region and the PMOS region includes a shallow trench isolation structure; the substrate of the PMOS region on both sides of the second sacrificial gate is etched, and when a groove is formed in the substrate of the PMOS region, the shallow trench isolation structure in the substrate of the PMOS region and the second mask layer are used as masks during etching.

[0014] In some embodiments of the present application, the process of forming the target reflective coating includes: forming an anti-reflective coating covering the first mask layer, the second mask layer, the first sacrificial gate and the second sacrificial gate on the top surface of the substrate;

[0015] forming a patterned photoresist layer on the top surface of the anti-reflective coating, wherein the patterned photoresist layer exposes the top surface of the anti-reflective coating on the PMOS region;

[0016] Using the patterned photoresist layer as a mask, etching away a portion of the thickness of the anti-reflective coating on the PMOS region, so that the thickness of the remaining anti-reflective coating on the PMOS region is equal to the thickness of the anti-reflective coating on the top surface of the first mask layer on the NMOS region, to form the target reflective coating;

[0017] The patterned photoresist layer is removed.

[0018] In some embodiments of the present application, the patterned photoresist layer is removed by using an exposure and development process.

[0019] In some embodiments of the present application, the substrate of the PMOS region on both sides of the second sacrificial gate is etched, and when a groove is formed in the substrate of the PMOS region, the etching amount of the first mask layer and the second mask layer is the same, so that the thickness of the remaining first mask layer and the thickness of the remaining second mask layer are the same, so that the top surface of the first mask layer remaining on the top surface of the first sacrificial gate is flush with the top surface of the second mask layer remaining on the top surface of the second sacrificial gate.

[0020] In some embodiments of the present application, the patterned photoresist layer is used as a mask and an anisotropic plasma etching process is adopted to remove a portion of the thickness of the anti-reflective coating on the PMOS region; and / or an anisotropic plasma etching process is adopted to remove a portion of the target reflective coating to expose the top surface of the substrate in the PMOS region and the top surface of the first mask layer.

[0021] In some embodiments of the present application, the groove is in a “Σ” shape.

[0022] In some embodiments of the present application, the process of forming the groove includes: first using anisotropic plasma etching process to etch the substrate of the PMOS region on both sides of the second sacrificial gate to form an initial groove in the substrate of the PMOS region; using a wet etching process to etch the initial groove to form the groove.

[0023] In some embodiments of the present application, the first sacrificial gate and the second sacrificial gate both include a gate dielectric layer located on the top surface of the substrate and a sacrificial layer located on the top surface of the gate dielectric layer.

[0024] In some embodiments of the present application, it also includes: forming an interlayer dielectric layer covering the first sacrificial gate, the second sacrificial gate and the remaining first mask layer and the second mask layer on the top surface of the substrate; performing a chemical mechanical polishing process on the interlayer dielectric layer and the remaining first mask layer and the second mask layer to expose the top surfaces of the first sacrificial gate and the second sacrificial gate; replacing the first sacrificial gate with a first metal gate structure, and replacing the second sacrificial gate with a second metal gate structure.

[0025] The embodiments of the present application may or at least have the following advantages:

[0026] In an embodiment of the present application, a method for preparing a semiconductor structure forms a substrate, a first sacrificial gate, and a first mask layer covering an NMOS region, and a target anti-reflective coating covering the substrate of the PMOS region and a portion of the sidewall of the second sacrificial gate, and after the thickness of the target anti-reflective coating on the top surface of the substrate of the PMOS region is equal to the thickness of the target anti-reflective coating on the top surface of the first mask layer, a portion of the target anti-reflective coating is removed to expose the top surface of the substrate of the PMOS region and the top surface of the first mask layer, that is, the anti-reflective coating on the PMOS region and the NMOS region is removed by the same thickness, and the top surface of the first mask layer on the top surface of the first sacrificial gate on the NMOS region is exposed, so that the substrate of the PMOS region is continuously etched, and the substrate on both sides of the second sacrificial gate of the PMOS region is During the process of forming the groove, the exposed first mask layer and the second mask layer are etched simultaneously, and the etching amount can be ensured to be the same, thereby improving the etching and flattening effect. That is, after the groove is formed, the top surface of the first mask layer remaining on the top surface of the first sacrificial gate is flush with the top surface of the second mask layer remaining on the top surface of the second sacrificial gate, so that the total height of the first sacrificial gate and the remaining first mask layer is consistent with the total height of the second sacrificial gate and the remaining second mask layer, thereby preventing a height difference between the two and facilitating subsequent processes and process integration. In the present application, in the aforementioned specific process in which the height of the first sacrificial gate and the height of the second sacrificial gate can be kept consistent, there is no need to perform an additional masking and etching process after the groove is formed, thereby simplifying the process flow, increasing efficiency, and reducing costs.

[0027] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1-Figure 6 A schematic diagram of a cross-sectional structure at each stage in the formation process of a semiconductor structure provided by the present application;

[0030] Figure 7-Figure 13 Schematic diagram of the cross-sectional structure at various stages in the formation process of the semiconductor structure provided in some embodiments of the present application. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations due to, for example, manufacturing technology.

[0037] It can be understood that in the drawings of the present application, some adjacent film layers with the same processed film material are drawn to be connected to make them close to the actual structure.

[0038] During the manufacturing process of PMOS transistors and NMOS transistors, after grooves and silicon germanium layers located in the grooves are formed in the substrate on both sides of the sacrificial gate structure of the PMOS region, the height of the sacrificial gate of the PMOS region and the height of the sacrificial gate of the NMOS region will be inconsistent (the height of the sacrificial gate of the NMOS region is higher than the height of the sacrificial gate of the PMOS region), which seriously affects the subsequent process and process integration. At this time, additional masking and etching processes are required to flatten the height difference between the sacrificial gate of the PMOS region and the sacrificial gate of the NMOS region, but this will increase costs, affect efficiency, and have poor results. For the specific manufacturing process, please refer to Figure 1-Figure 6 First, please refer to Figure 1, providing a substrate 101, the substrate 101 includes an NMOS region 11 and a PMOS region 12, the top surface of the substrate of the NMOS region 11 has a first sacrificial gate, the first sacrificial gate includes a first gate dielectric layer 103 and a first sacrificial layer 104 located on the top surface of the first gate dielectric layer 103, the top surface of the first sacrificial gate also has a first mask layer, the first mask layer includes a first sub-mask layer 107 located on the top surface of the first sacrificial layer 104 and a second sub-mask layer 108 located on the top surface of the first sub-mask layer 107, the top surface of the substrate of the PMOS region It has a second sacrificial gate, which includes a second gate dielectric layer 105 and a second sacrificial layer 106 located on the top surface of the second gate dielectric layer 105. The top surface of the second sacrificial gate also has a second mask layer, and the second mask layer includes a third sub-mask layer 109 located on the top surface of the second sacrificial layer 106 and a fourth sub-mask layer 110 located on the top surface of the third sub-mask layer 109. The top surface of the substrate 101 also has a sidewall material layer 112 covering the sidewall surfaces of the first and second sacrificial gates and the sidewall surfaces and top surfaces of the first and second mask layers.

[0039] refer to Figure 2 A first anti-reflective coating 113 covering the first mask layer, the second mask layer, the first sacrificial gate and the second sacrificial gate is formed on the top surface of the substrate 101; a patterned first photoresist layer 114 is formed on the top surface of the first anti-reflective coating 113, and the patterned first photoresist layer 114 exposes the top surface of the first anti-reflective coating 113 on the PMOS region 12.

[0040] refer to Figure 3, using the patterned first photoresist layer 114 as a mask, etching away the first anti-reflective coating 113 on the PMOS region to expose the substrate 101 on both sides of the second sacrificial gate (105, 106) of the PMOS region 12, and etching the exposed substrate 101 to form grooves 115 in the substrate 101 on both sides of the second sacrificial gate. In the process of etching the substrate 101, the patterned first photoresist layer 114 and the first anti-reflective coating 113 of the NMOS region 11 are etched synchronously, and in the aforementioned etching process, the second sacrificial gate (105, 106) is 6) The second mask layer (109, 110) on the top surface will be exposed before the first mask layer (107, 108) on the top surface of the first sacrificial gate (103, 104), so the second mask layer (109, 110) on the top surface of the second sacrificial gate (105, 106) will be over-etched during the etching process, so that after the groove 115 is formed, the height of the second sacrificial gate (including the remaining second mask layer (109, 110)) on the PMOS region will be lower than the height of the first sacrificial gate (including the first mask layer (107, 108)) on the NMOS region.

[0041] refer to Figure 4 , forming a silicon germanium layer 116 that fills the groove.

[0042] refer to Figure 5 A second anti-reflective coating 117 covering the first mask layer, the second mask layer, the first sacrificial gate and the second sacrificial gate is formed on the top surface of the substrate 101; a patterned second photoresist layer 118 is formed on the top surface of the second anti-reflective coating 117, and the patterned second photoresist layer 118 exposes the top surface of the second anti-reflective coating 117 on the NMOS region 11.

[0043] refer to Figure 6 , using the patterned second photoresist layer 118 as a mask, etching away a portion of the second anti-reflective coating 117 on the NMOS region 11 to expose the top surface of the first mask layer (specifically, the second sub-mask layer 108) on the top surface of the first sacrificial gate of the NMOS region 11, and continuing to etch away a portion of the thickness of the first mask layer (specifically, the second sub-mask layer 108), so that the height of the remaining first mask layer on the top surface of the first sacrificial gate of the NMOS region 11 is consistent with the height of the remaining second mask layer on the top surface of the second sacrificial gate of the PMOS region.

[0044] As can be seen from the above, in order to flatten the height difference between the second sacrificial gate of the PMOS region 12 and the first sacrificial gate of the NMOS region 11, it is necessary to additionally form a second anti-reflective coating 117 and a patterned second photoresist layer 118 in the aforementioned process, and an additional etching process is required, which will increase the cost, affect the efficiency, and the flattening effect is not good.

[0045] To this end, an embodiment of the present application provides a method for preparing a semiconductor structure, which ensures that the height of the first sacrificial gate in the NMOS region and the second sacrificial gate in the PMOS region are consistent when a silicon germanium layer is formed in the PMOS region, while simplifying the process flow, increasing efficiency, reducing costs, and improving the flattening effect.

[0046] The specific process of the method for preparing the semiconductor structure is described in detail below with reference to the accompanying drawings.

[0047] Figure 7-Figure 12 Schematic diagram of the cross-sectional structure at various stages in the formation process of the semiconductor structure provided in some embodiments of the present application.

[0048] First, refer to Figure 7 , providing a substrate 201, the substrate 201 comprising an NMOS region 21 and a PMOS region 22, a portion of the top surface of the NMOS region 21 comprising a first sacrificial gate (203, 204) and a first mask layer (207, 208) sequentially stacked along a first direction perpendicular to the top surface of the substrate, a portion of the top surface of the PMOS region 22 comprising a second sacrificial gate (205, 206) and a second mask layer (209, 210) sequentially stacked along the first direction, the thickness of the first sacrificial gate (203, 204) being the same as the thickness of the second sacrificial gate (205, 206), and the material and thickness of the first mask layer (207, 208) being the same as the material and thickness of the second mask layer (209, 210).

[0049] The material of the substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide. Certain doping ions may also be injected into the substrate 201 according to design requirements to change electrical parameters.

[0050] The substrate 201 includes an NMOS region 21 and a PMOS region 22. An NMOS transistor is subsequently formed in the NMOS region 21, and a PMOS transistor is subsequently formed in the PMOS region. The NMOS region 21 and the PMOS region 22 may be adjacent or non-adjacent. The number of the NMOS region 21 may be one or more, and the number of the PMOS region 22 may also be one or more. It should be noted that Figure 7 The example in which the substrate 201 has an NMOS region 21 and a PMOS region 22 and the PMOS region 22 is located on one side of the NMOS region 21 is used for illustration only, which should not limit the protection scope of the present application.

[0051] In some embodiments, the substrate 201 further includes a shallow trench isolation structure 202. Specifically, the substrate 201 in both the NMOS region and the PMOS region includes a shallow trench isolation structure 202. The first sacrificial gate (203, 204) is formed on the top surface of the substrate 201 between adjacent shallow trench isolation structures 202 in the NMOS region. The second sacrificial gate (205, 206) is formed on the top surface of the substrate 201 between adjacent shallow trench isolation structures 202 in the PMOS region. The shallow trench isolation structure 201 is used to isolate adjacent transistors (such as adjacent NMOS transistors and PMOS transistors) to prevent electrical connection between adjacent transistors. In a specific example, the material of the shallow trench isolation structure 202 can be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0052] The first sacrificial gate (203, 204) serves as a sacrificial layer when a first metal gate structure of an NMOS transistor is subsequently formed in the NMOS region 21. The position and size of the first sacrificial gate (203, 204) determine the position and size of the first metal gate formed subsequently. In some embodiments, the first sacrificial gate (203, 204) includes a gate dielectric layer 203 located on the top surface of the substrate 201 in the NMOS region 11, and a sacrificial layer 204 located on the top surface of the gate dielectric layer 203. The material of the gate dielectric layer 203 may be silicon oxide, and the material of the sacrificial layer 204 may be polysilicon or other suitable sacrificial materials, such as amorphous silicon, amorphous carbon, etc.

[0053] The second sacrificial gate (209, 210) serves as a sacrificial layer when a second metal gate structure of a PMOS transistor is subsequently formed in the PMOS region 22. The position and size of the second sacrificial gate (209, 210) determine the position and size of the second metal gate formed subsequently. In some embodiments, the second sacrificial gate (209, 210) includes a gate dielectric layer 205 located on the top surface of the substrate 201 in the NMOS region 11, and a sacrificial layer 206 located on the top surface of the gate dielectric layer 205. The material of the gate dielectric layer 205 may be silicon oxide, and the material of the sacrificial layer 205 may be polysilicon or other suitable sacrificial materials, such as amorphous silicon, amorphous carbon, etc.

[0054] The first mask layer (207, 208) is used as a mask when forming a first sacrificial gate, and the second mask layer (209, 210) is used as a mask when forming a second sacrificial gate. The first mask layer (207, 208) and the second mask layer (209, 210) can be a single-layer or multi-layer stacked structure. In some embodiments, the first mask layer (207, 208) includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polysilicon, or a combination thereof, and the second mask layer (209, 210) includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polysilicon, or a combination thereof. In a specific example, the first mask layer (207, 208) includes a first sub-mask layer 207 located on the top surface of the sacrificial layer 204 and a second sub-mask layer 208 located on the top surface of the first sub-mask layer 207, the first sub-mask layer 207 and the second sub-mask layer 208 are made of different materials, and the thickness of the first sub-mask layer 207 is less than the thickness of the second sub-mask layer 208. The second mask layer (209, 210) includes a third sub-mask layer 209 located on the top surface of the sacrificial layer 206 and a third sub-mask layer 209 located on the top surface of the third sub-mask layer 209, the third sub-mask layer 209 and the third sub-mask layer 209 are made of different materials, and the thickness of the third sub-mask layer 209 is less than the thickness of the third sub-mask layer 209.

[0055] In some embodiments, the sidewall surfaces of the first sacrificial gate (203, 204), the second sacrificial gate (205, 206), the first mask layer (207, 208) and the second mask layer (209, 210) also have a sidewall material layer 212. In a specific example, the sidewall material layer 212 can also cover the first mask layer (207, 208), the second mask layer (209, 210) and the top surface of the substrate 201. The material of the sidewall material layer 212 is different from the material of the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206), for example, it can be silicon nitride, silicon oxynitride or silicon carbide. After the interlayer dielectric layer covering the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206) is subsequently formed, when the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206) are removed by an etching process to form a first opening and a second opening correspondingly, the etching rate of the sidewall material layer 212 on the sidewall surface of the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206) is low or small, so that the formed first opening and the second opening have a better sidewall morphology.

[0056] Next, refer to Fig.10 , forming a target anti-reflection coating 213, the target anti-reflection coating 213 covers the substrate 201 of the NMOS region 21, the first sacrificial gate (203, 204), the first mask layer (207, 208), and part of the side walls of the second sacrificial gate (205, 206), and the thickness D1 of the target anti-reflection coating 213 on the top surface of the substrate 201 of the PMOS region 22 is equal to the thickness D2 of the target anti-reflection coating 213 on the top surface of the first mask layer (207, 208).

[0057] In some embodiments below, Figure 8-Figure 10 The formation process of the target anti-reflection coating 213 is described in detail.

[0058] refer to Figure 8 An anti-reflective coating 211 is formed on the top surface of the substrate 201, covering the first mask layer (207, 208), the second mask layer (209, 210), the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206); a patterned photoresist layer 214 is formed on the top surface of the anti-reflective coating 211, and the patterned photoresist layer 214 exposes the top surface of the anti-reflective coating 211 on the PMOS region 22.

[0059] On the one hand, the anti-reflective coating 211 is used to fill the area between the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206) to provide a flat surface for forming a photoresist layer; on the other hand, the anti-reflective coating 211 can reduce the reflection of the exposure light when exposing the photoresist layer, ensuring that the photoresist can be accurately exposed, thereby forming an accurate pattern. In a specific example, the material of the anti-reflective coating 211 can be an organic material, and the anti-reflective coating 211 is formed by a spin coating process.

[0060] The patterned photoresist layer 214 is used as a mask for subsequent etching of the anti-reflective coating 211 of the PMOS region 22. In some embodiments, the process of forming the patterned photoresist layer 214 includes: forming a photoresist layer on the top surface of the anti-reflective coating 211 by a spin coating process; exposing and developing the photoresist layer of the PMOS region 22, removing the photoresist layer of the PMOS region 22, and retaining the photoresist layer of the NMOS region, so as to form a patterned photoresist layer 214 on the top surface of the anti-reflective coating 211 of the NMOS region 21; and baking after development to solidify the patterned photoresist layer 214. In some embodiments, the patterned photoresist layer 214 is made of positive photoresist. After etching away a portion of the thickness of the anti-reflective coating 211 on the PMOS region 22, there is no need to use a mask or a mask plate. The patterned photoresist layer 214 on the NMOS region 21 is directly exposed and developed, and the patterned photoresist layer 214 on the NMOS region 21 can be directly removed, which simplifies the process and reduces costs.

[0061] Next, refer to Fig. 9 , using the patterned photoresist layer 214 as a mask, etching away a portion of the thickness of the anti-reflective coating 211 on the PMOS region 22 (refer to Figure 8 ), so that the thickness D1 of the remaining anti-reflection coating on the PMOS region 22 is equal to the thickness D2 of the anti-reflection coating on the top surface of the first mask layer (207, 208) on the NMOS region 21, forming the target anti-reflection coating 213.

[0062] In one embodiment, the patterned photoresist layer 214 is used as a mask and an anisotropic plasma etching process is used to etch away a portion of the thickness of the anti-reflection coating 213 on the PMOS region 22. In a specific example, the etching gas used in the anisotropic plasma etching process is a gas containing oxygen and / or chlorine, such as oxygen-containing gas O2 or O3, and chlorine-containing gas Cl2 or HCl. When etching away a portion of the thickness of the anti-reflection coating 213 on the PMOS region 22, the anisotropic plasma etching process has a lower etching rate for the second mask layer (209, 210) on the PMOS region 22 (when the sidewall material layer 212 is included, the etching rate for the sidewall material layer 212 is lower), so that the thickness of the second mask layer (209, 210) (sidewall material layer 212) remains unchanged or changes slightly.

[0063] In the present application, the anti-reflection coating 213 of a part of the thickness on the PMOS region 22 is removed by etching, so that the thickness D1 of the target anti-reflection coating 213 formed on the PMOS region 22 is equal to the thickness D2 of the target anti-reflection coating 213 formed on the top surface of the first mask layer (207, 208) on the NMOS region 21. Subsequently, after removing the patterned photoresist layer 214 on the NMOS region 21 (refer to Fig.10 ), the target anti-reflective coating 213 is continuously etched away until the top surface of the substrate 201 is exposed (when the sidewall material layer 212 is included, the top surface of the sidewall material layer 212 on the top surface of the substrate 201 of the PMOS region 22 is exposed), and at the same time, the target anti-reflective coating 213 on the NMOS region 21 is also removed by the same thickness, exposing the top surface of the first mask layer (207, 208) on the top surface of the first sacrificial gate on the NMOS region 21 (when the sidewall material layer 212 is included, the top surface of the sidewall material layer 212 on the first mask layer (207, 208) of the NMOS region 21 is exposed) (reference Fig.11 ), so that the substrate 201 of the PMOS region 22 is subsequently etched, and in the process of forming the groove 215 in the substrate 201 on both sides of the second sacrificial gate of the PMOS region 22 (refer to Fig.12), the exposed first mask layer (207, 208) and the second mask layer (209, 210) are etched synchronously, and the etching amount can be ensured to be the same, thereby improving the etching and flattening effect, that is, after the groove 215 is formed, the top surface of the first mask layer (207, 208) remaining on the top surface of the first sacrificial gate (203, 204) is flush with the top surface of the second mask layer (209, 210) remaining on the top surface of the second sacrificial gate (205, 206), that is, the first sacrificial gate (203, 204) is 4) and the total height of the remaining first mask layer (207, 208) is consistent with the total height of the second sacrificial gate (205, 206) and the remaining second mask layer (209, 210), thereby preventing a height difference between the two and facilitating subsequent processes and process integration. In the present application, in the aforementioned specific process in which the height of the first sacrificial gate and the height of the second sacrificial gate can be kept consistent, there is no need to perform an additional masking and etching process after forming the groove, thereby simplifying the process flow, increasing efficiency and reducing costs.

[0064] Next, refer to Fig.10 , remove the patterned photoresist layer 214.

[0065] The patterned photoresist layer 214 is removed by an exposure and development process. When performing the exposure, a mask or a mask plate is not required, and the patterned photoresist layer 214 on the NMOS region 21 is directly exposed, and then developed to remove the patterned photoresist layer 214. The exposure and development process will not affect or have little effect on the target anti-reflection coating 213, thereby ensuring the accuracy of the thickness of the target anti-reflection coating 213 on the PMOS region 22 and the NMSO region 21.

[0066] Next, refer to Fig.11 After removing the patterned photoresist layer 214, a portion of the target reflective coating 213 is removed to expose the top surface of the substrate 201 of the PMOS region 22 and the top surface of the first mask layer (207, 208).

[0067] In some embodiments, after removing the patterned photoresist layer 214, an anisotropic plasma etching process is used to remove a portion of the target reflective coating 213 to expose the top surface of the substrate 201 of the PMOS region 22 and the top surface of the first mask layer (207, 208). The anisotropic plasma etching process is the same as the anisotropic plasma etching process for removing a portion of the thickness of the anti-reflective coating 213 in the PMOS region 22, and will not be repeated here.

[0068] In some embodiments, a portion of the target reflective coating 213 is removed to directly expose the top surface of the substrate 201 of the PMOS region 22 on both sides of the second sacrificial gate (205, 206) and the top surface of the first mask layer (207, 208) on the NMOS region 21.

[0069] In other embodiments, when a sidewall material layer 212 is included, after a portion of the target reflective coating 213 is removed, the top surface of the sidewall material layer 212 on the substrate 201 of the PMOS region 22 on both sides of the second sacrificial gate (205, 206) and the top surface of the sidewall material layer 212 on the first mask layer (207, 208) on the NMOS region 21 are exposed.

[0070] Next, refer to Fig.12 , etching the substrate 201 on both sides of the second sacrificial gate (205, 206) of the PMOS region 22 to form a groove 215 in the substrate 201, and simultaneously etching away the remaining target anti-reflective coating 213 on the NMOS region 21 and a partial thickness of the first mask layer (207, 208) and the second mask layer (209, 210).

[0071] The substrate 201 of the PMOS region 22 on both sides of the second sacrificial gate (205, 206) is etched, and when a groove 215 is formed in the substrate 201 of the PMOS region 22, the shallow trench isolation structure in the substrate 201 of the PMOS region 22 and the second mask layer (209, 210) are used as masks during etching.

[0072] The substrate 201 of the PMOS region 22 on both sides of the second sacrificial gate (205, 206) is etched. When a groove 215 is formed in the substrate 201 of the PMOS region 22, the etching amount of the first mask layer (207, 208) and the second mask layer (209, 210) are the same, so that the thickness of the remaining first mask layer (207, 208) is the same as the thickness of the remaining second mask layer (209, 210), so that the top surface of the first mask layer (207, 208) remaining on the top surface of the first sacrificial gate (203, 204) is flush with the top surface of the second mask layer (209, 210) remaining on the top surface of the second sacrificial gate (205, 206).

[0073] In some embodiments, when a sidewall material layer 212 is included, the sidewall material layer 212 on the top surface of the substrate 201 and the top surfaces of the first mask layer and the second mask layer in the PMOS region 22 is first etched away to expose the top surface of the substrate 201 and the top surfaces of the first mask layer and the second mask layer in the PMOS region 22. An anisotropic plasma etching process is used to etch away the sidewall material layer 212. In a specific example, the etching gas used in the anisotropic plasma etching process is a gas containing carbon and fluorine, such as one or more of CF4, C4F8, C5F8, and C4F6.

[0074] In some embodiments, the shape of the groove 215 is a “Σ” shape. After a silicon germanium layer is formed in the groove of such a shape, the compressive stress in the channel region of the PMOS transistor can be increased.

[0075] In one embodiment, the formation process of the “Σ”-shaped groove 215 includes: firstly etching the substrate 201 of the PMOS region 22 on both sides of the second sacrificial gate (205, 206) by an anisotropic plasma etching process to form an initial groove 215 in the substrate 201 of the PMOS region 22, wherein the etching gases used in the anisotropic plasma etching process include CF4 and HBr; etching the initial groove 215 by a wet etching process to form the groove 215, wherein the wet etching process uses an etching solution TMAH solution or NH3.H2O solution having different etching rates for different crystal orientations.

[0076] Next, refer to Fig.13 , a silicon germanium layer 216 is formed in the groove 215 .

[0077] The silicon germanium layer 216 may be formed by a selective epitaxial process, that is, the epitaxial growth rate of the silicon germanium layer on the semiconductor material is greater than the epitaxial growth rate on other materials (such as silicon oxide, silicon nitride).

[0078] In some embodiments, when the silicon germanium layer 216 is formed, P-type impurity ions may be in-situ doped into the silicon germanium layer 216 , and the P-type impurity ions are one or more of boron ions, gallium ions, or indium ions.

[0079] In some embodiments, the formation method further includes: forming an interlayer dielectric layer (not shown in the figure) on the top surface of the substrate 201 to cover the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206) and the remaining first mask layer (207, 208) and the second mask layer (209, 210); performing a chemical mechanical polishing process on the interlayer dielectric layer, the sidewall material layer and the remaining first mask layer (207, 208) and the second mask layer (209, 210) to expose the top surfaces of the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206); replacing the first sacrificial gate with a first metal gate structure, and replacing the second sacrificial gate with a second metal gate structure. In some embodiments, the process of replacing the first sacrificial gate with a first metal gate structure and replacing the second sacrificial gate with a second metal gate structure includes: removing the first sacrificial gate (203, 204) and the second sacrificial gate (205, 206), forming a first opening and a second opening (not shown in the figure) at corresponding positions; forming a first metal gate structure (not shown in the figure) in the first opening, and forming a second metal gate structure (not shown in the figure) in the second opening. In some embodiments, the first metal gate structure may include a first high-K gate dielectric layer located on the sidewall and bottom surface of the first opening and a first metal gate electrode located on the surface of the first high-K gate dielectric layer and filling up the first opening; the second metal gate structure may include a second high-K gate dielectric layer located on the sidewall and bottom surface of the second opening and a second metal gate electrode located on the surface of the second high-K gate dielectric layer and filling up the second opening; the material of the first high-K gate dielectric layer and the second high-K gate dielectric layer is one or more of HfO2, Al2O3, ZrO2, HfSiO, HfSiON, HfTaO and HfZrO; the material of the first metal gate electrode and the second metal gate electrode is metal, for example, the material of the gate electrode 203 is one or more of W, Al, Cu, Ti, Ta, Co, TaN, NiSi, CoSi, TiN, TiAl and TaSiN. In some embodiments, a first work function layer may be formed between the first high-K gate dielectric layer and the first metal gate electrode to adjust the work function of the NMOS transistor; a second work function layer may be formed between the second high-K gate dielectric layer and the second metal gate electrode to adjust the work function of the PMOS transistor.

[0080] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an NMOS region and a PMOS region, the top surface of the NMOS region comprising a first sacrificial gate and a first mask layer sequentially stacked along a first direction perpendicular to the top surface of the substrate, the top surface of the PMOS region comprising a second sacrificial gate and a second mask layer sequentially stacked along the first direction, the thickness of the first sacrificial gate is the same as the thickness of the second sacrificial gate, and the material and thickness of the first mask layer are the same as the material and thickness of the second mask layer; Forming a target anti-reflection coating, wherein the target anti-reflection coating covers the substrate of the NMOS region, the first sacrificial gate, the first mask layer, the substrate of the PMOS region, and a portion of the sidewall of the second sacrificial gate, and the thickness of the target anti-reflection coating on the top surface of the substrate of the PMOS region is equal to the thickness of the target anti-reflection coating on the top surface of the first mask layer; removing a portion of the target reflective coating to expose a top surface of the substrate in the PMOS region and a top surface of the first mask layer; Etching the substrate on both sides of the second sacrificial gate of the PMOS region to form a groove in the substrate, and simultaneously etching away a portion of the thickness of the first mask layer, a portion of the thickness of the second mask layer, and the remaining target anti-reflection coating of the NMOS region; A silicon germanium layer is formed in the groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrates of the NMOS region and the PMOS region include shallow trench isolation structures; the substrate of the PMOS region on both sides of the second sacrificial gate is etched, and when a groove is formed in the substrate of the PMOS region, the shallow trench isolation structure in the substrate of the PMOS region and the second mask layer are used as masks during etching.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The process of forming the target reflective coating includes: forming an anti-reflective coating covering the first mask layer, the second mask layer, the first sacrificial gate and the second sacrificial gate on the top surface of the substrate; forming a patterned photoresist layer on the top surface of the anti-reflective coating, wherein the patterned photoresist layer exposes the top surface of the anti-reflective coating on the PMOS region; Using the patterned photoresist layer as a mask, etching away a portion of the thickness of the anti-reflective coating on the PMOS region, so that the thickness of the remaining anti-reflective coating on the PMOS region is equal to the thickness of the anti-reflective coating on the top surface of the first mask layer on the NMOS region, to form the target reflective coating; The patterned photoresist layer is removed.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The patterned photoresist layer is removed by using an exposure and development process.

5. The method for preparing a semiconductor structure according to claim 1 or 3, characterized in that: The substrate of the PMOS region on both sides of the second sacrificial gate is etched. When a groove is formed in the substrate of the PMOS region, the etching amount of the first mask layer and the second mask layer is the same, so that the thickness of the remaining first mask layer is the same as the thickness of the remaining second mask layer, so that the top surface of the first mask layer remaining on the top surface of the first sacrificial gate is flush with the top surface of the second mask layer remaining on the top surface of the second sacrificial gate.

6. The method for preparing a semiconductor structure according to claim 3, characterized in that: Using the patterned photoresist layer as a mask, an anisotropic plasma etching process is used to remove a portion of the thickness of the anti-reflective coating on the PMOS region; and / or an anisotropic plasma etching process is used to remove a portion of the target reflective coating to expose the top surface of the substrate in the PMOS region and the top surface of the first mask layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The shape of the groove is "Σ" shape.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The formation process of the groove includes: firstly etching the substrate of the PMOS region on both sides of the second sacrificial gate by anisotropic plasma etching process to form an initial groove in the substrate of the PMOS region; and etching the initial groove by wet etching process to form the groove.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first sacrificial gate and the second sacrificial gate both include a gate dielectric layer located on the top surface of the substrate and a sacrificial layer located on the top surface of the gate dielectric layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: Also includes: forming an interlayer dielectric layer covering the first sacrificial gate, the second sacrificial gate and the remaining first mask layer and the second mask layer; Performing a chemical mechanical polishing process on the interlayer dielectric layer and the remaining first mask layer and the second mask layer to expose the top surfaces of the first sacrificial gate and the second sacrificial gate; The first sacrificial gate is replaced with a first metal gate structure, and the second sacrificial gate is replaced with a second metal gate structure.

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