Dielectric frame structure for mitigating layout-related effects in semiconductor devices

Abstract

A dielectric frame structure for mitigating layout-related effects in a semiconductor device is provided. The present disclosure describes a semiconductor device having a dielectric frame structure. The semiconductor device includes a channel structure on a substrate and extending in a first direction; a gate structure on the channel structure and extending in a second direction different from the first direction; a dielectric frame structure on the substrate and parallel to the channel structure; and an isolation structure adjacent to the gate structure and extending through the channel structure into the substrate. The dielectric frame structure includes a dielectric material extending through the gate structure to divide the gate structure into two parts. An end of the isolation structure is in contact with the dielectric frame structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor device technology, and more particularly to a dielectric frame structure for mitigating layout-related effects in semiconductor devices. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and gate all-around field effect transistors (GAAFETs). This scaling down increases the complexity of semiconductor manufacturing processes and increases the difficulty of process control in semiconductor devices. Summary of the invention

[0003] In one aspect, an embodiment of the present application provides a semiconductor structure comprising: a channel structure on a substrate and extending along a first direction; a gate structure on the channel structure and extending along a second direction different from the first direction; a dielectric frame structure on the substrate and parallel to the channel structure, wherein the dielectric frame structure comprises a dielectric material extending through the gate structure to divide the gate structure into two parts; and an isolation structure adjacent to the gate structure and extending through the channel structure into the substrate, wherein an end of the isolation structure is in contact with the dielectric frame structure.

[0004] In some implementations, the dielectric material has a Young's modulus greater than about 75 GPa.

[0005] In some implementations, the dielectric frame structure is between the gate structure and the isolation structure.

[0006] In some implementations, top surfaces of the gate structure, the dielectric frame structure, and the isolation structure are substantially coplanar.

[0007] In some implementations, a bottom surface of the dielectric frame structure is higher than a bottom surface of the isolation structure.

[0008] In some implementations, the semiconductor structure further includes: a shallow trench isolation (STI) region on the substrate and surrounding the channel structure, wherein the dielectric frame structure extends through the gate structure into the STI region.

[0009] In some implementations, the isolation structure extends through the STI region into the substrate.

[0010] In some implementations, a portion of the STI region is surrounded by the isolation structure and the substrate.

[0011] In some implementations, the isolation structure includes a liner in contact with the dielectric frame structure and a dielectric filler on the liner.

[0012] On the other hand, an embodiment of the present application provides a semiconductor device, comprising: a plurality of channel structures on a substrate; a gate structure on the substrate and the plurality of channel structures; a plurality of dielectric frame structures comprising a dielectric material and extending through the gate structures to divide the gate structures into isolated portions, wherein the plurality of channel structures and the plurality of dielectric frame structures are arranged in an alternating configuration; and an isolation structure extending along the gate structure and passing through at least one of the plurality of channel structures, wherein the isolation structure is in contact with at least one of the plurality of dielectric frame structures.

[0013] In some implementations, the dielectric material has a Young's modulus greater than about 75 GPa.

[0014] In some implementations, a dielectric frame structure of the plurality of dielectric frame structures is between the gate structure and the isolation structure.

[0015] In some implementations, top surfaces of the gate structure, the plurality of dielectric frame structures, and the isolation structure are substantially coplanar.

[0016] In some implementations, bottom surfaces of the plurality of dielectric frame structures are higher than a bottom surface of the isolation structure.

[0017] In some implementations, the semiconductor device further includes: a shallow trench isolation (STI) region on the substrate and surrounding the plurality of channel structures, wherein the plurality of dielectric frame structures extend through the gate structure into the STI region.

[0018] In some implementations, the isolation structure extends through the STI region into the substrate.

[0019] On the other hand, an embodiment of the present application provides a method, comprising: forming a channel structure extending along a first direction on a substrate; forming a gate structure extending along a second direction different from the first direction on the channel structure; forming an opening in the gate structure; filling the opening with a dielectric material to form a dielectric frame structure parallel to the channel structure, wherein the dielectric frame structure divides the gate structure into two parts; and forming an isolation structure adjacent to the gate structure and extending through the channel structure into the substrate, wherein an end of the isolation structure is in contact with the dielectric frame structure.

[0020] In some implementations, the method further includes forming a shallow trench isolation (STI) region on the substrate surrounding the plurality of channel structures, wherein the dielectric frame structure extends through the gate structure and into the STI region.

[0021] In some embodiments, forming a dielectric frame structure includes: forming a dielectric layer on a gate structure; forming an opening in the dielectric layer and the gate structure, wherein a bottom surface of the opening is lower than a bottom surface of the gate structure; and filling the opening with a dielectric material, wherein the dielectric material has a Young's modulus greater than about 75 GPa.

[0022] In some implementations, forming the isolation structure includes: removing a portion of the gate structure adjacent to the dielectric frame structure to form an opening; removing a portion of the channel structure in the opening, wherein the opening extends into the substrate; and depositing a dielectric material in the opening, wherein the dielectric material contacts the dielectric frame structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0024] Figure 1 A top view of a semiconductor device having a dielectric frame structure according to some embodiments is shown.

[0025] Figure 2 An isometric view of a semiconductor device having a dielectric frame structure is shown in accordance with some embodiments.

[0026] Figure 3 as well as FIG. 4A to FIG. 4B A cross-sectional view of a semiconductor device having a dielectric frame structure according to some embodiments is shown.

[0027] Figure 5 A schematic diagram of a semiconductor device having a dielectric frame structure according to some embodiments is shown.

[0028] Figure 6 is a flow chart of a method for fabricating a semiconductor device having a dielectric frame structure according to some embodiments.

[0029] Figures 7 to 44 Top view, isometric view, and cross-sectional view of a semiconductor device having a dielectric frame structure at various stages of its fabrication are shown in accordance with some embodiments.

[0030] Fig.45 is a flow chart of another method for fabricating a semiconductor device having a dielectric frame structure according to some embodiments.

[0031] Figures 46 to 83 Partial cross-sectional views of a semiconductor device having a dielectric frame structure at various stages of fabrication using another method are shown in accordance with some embodiments.

[0032] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0033] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature and the second feature are formed in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0034] Additionally, spatially relative terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0035] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0036] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the specification is interpreted by persons skilled in the relevant art(s) based on the teachings herein.

[0037] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0038] As the demand for lower power consumption, higher performance and smaller semiconductor devices increases, the size of semiconductor devices is continuously scaled down. The continuous scaling down of device size and the growing demand for device performance may require various process and material improvements, which may have multiple challenges. For example, continuous polysilicon on diffusion edge (CPODE) or continuous metal on diffusion edge (CMODE) processes can be used to pattern nanostructure transistors with trench isolation structures. The trench isolation structure can reduce the leakage current through the source / drain (S / D) epitaxial structure, the transistor channel and the substrate. Nanostructure transistors may include finFETs, GAA FETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanobelt transistors, and other transistors of similar structures. However, CPODE and CMODE processes may generate tensile and / or compressive forces on the surface of the substrate, resulting in deformation of the substrate and causing layout-related effects (LDE) of nanostructure transistors on the substrate. The iso-dense depth loading effect of LDE may increase the leakage current of nanostructure transistors. The iso-dense critical size loading effect of LDE may cause damage to the S / D epitaxial structure. Gate deformation from LDE may cause the threshold voltage (V t )drift.

[0039] Various embodiments of the present disclosure provide methods for forming a dielectric frame structure in a semiconductor device (e.g., a nanostructure transistor) and / or other semiconductor device in an integrated circuit (IC). In some embodiments, a channel structure extending in a first direction may be formed on a substrate. A gate structure extending in a second direction different from the first direction may be formed on the channel structure. An opening may be formed in the gate structure. A dielectric material may be filled in the opening to form a dielectric frame structure parallel to the channel structure and dividing the gate structure into two parts. In some embodiments, the dielectric frame structure may include a hard dielectric material and extend in a first direction. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. An isolation structure may be formed adjacent to the gate structure and may extend through the channel structure into the substrate. In some embodiments, the end of the isolation structure may contact the dielectric frame structure. In some embodiments, the isolation structure may be formed by a CPODE or CMODE process. In some embodiments, the dielectric frame structure can be used as a gate isolation structure, such as a cut polysilicon gate (CPO) or cut metal gate (CMG) dielectric structure. In some embodiments, the dielectric frame structure can reduce deformation of the substrate and minimize the LDE effect of the semiconductor device on the substrate. Therefore, the dielectric frame structure can reduce device leakage current, minimize damage to the S / D epitaxial structure, and reduce the V t drift.

[0040] Figure 1 A top view of a semiconductor device 100 having a dielectric frame structure is shown in accordance with some embodiments. Figure 2 A partial isometric view of a semiconductor device 100 having a dielectric frame structure is shown in accordance with some embodiments. Figure 3 as well as FIG. 4A to FIG. 4B 1 and 2 show the semiconductor device 100 having a dielectric frame structure according to some embodiments. Figure 2 Partial cross-sectional views along lines AA and BB are shown. Figure 5 A schematic diagram of a semiconductor device 100 having a dielectric frame structure according to some embodiments is shown.

[0041] In some embodiments, the semiconductor device 100 may include transistors 102A to 102B, such as Figure 2As shown. In some embodiments, transistors 102A to 102B may include nanostructure transistors. Nanostructure transistors may include finFETs, GAA FETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. Nanostructure transistors may provide channels in a fin structure or a stacked nanosheet / nanowire configuration. In some embodiments, transistors 102A to 102B may be n-type field effect transistors (NFETs). In some embodiments, transistors 102A to 102B may be p-type field effect transistors (PFETs). In some embodiments, any one of transistors 102A to 102B may be an NFET or a PFET. Although Figure 2 Two transistors are shown, but semiconductor device 100 can have any number of transistors. In addition, semiconductor device 100 can be incorporated into an IC by using other structural components (e.g., conductive vias, wires, dielectric layers, passivation layers, and interconnects, which are not shown for simplicity). Unless otherwise noted, the discussion of each element of transistors 102A to 102B with the same annotation applies to each other. In addition, the same reference numerals generally represent the same, functionally similar, and / or structurally similar elements.

[0042] refer to Figures 1 to 5 , a semiconductor device 100 having transistors 102A to 102B may be formed on a substrate 104 and may be isolated by a shallow trench isolation (STI) region 106. Each of the transistors 102A to 102B may include a fin structure 108, nanostructures 122-1, 122-2, and 122-3 (collectively referred to as “nanostructures 122”), a gate dielectric layer 124, a gate structure 112, a gate spacer 114, an internal spacer 121, and an S / D structure 110. In some embodiments, the semiconductor device 100 may also include trench isolation structures 113-1 and 113-2 (collectively referred to as “trench isolation structures 113”), dielectric frame structures 120-1 and 120-2 (collectively referred to as “dielectric frame structures 120”), an etch stop layer (ESL) 116, and an interlayer dielectric (ILD) layer 118.

[0043] refer to Figures 1 to 5, the substrate 104 may include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a silicon wafer). In some embodiments, the substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. In addition, the substrate 104 may be doped, depending on the design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0044] STI regions 106 can provide electrical isolation between transistors 102A-102B, electrical isolation of transistors 102A-102B from adjacent transistors (not shown) on substrate 104, and / or adjacent active and passive components (not shown) integrated with substrate 104 or deposited on substrate 104. STI regions 106 can be made of dielectric materials. In some embodiments, STI regions 106 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In some embodiments, STI regions 106 can include a multilayer structure.

[0045] refer to Figures 1 to 5 , the nanostructure 122 and the fin structure 108 can be formed on the patterned portion of the substrate 104. The embodiments of the nanostructure and the fin structure disclosed herein can be patterned by any suitable method. For example, one or more photolithography processes can be used for patterning (including a double patterning process or a multi-patterning process) to obtain the nanostructure and the fin structure. The double patterning process or the multi-patterning process can combine the photolithography process and the self-alignment process to form a pattern with a spacing smaller than the spacing obtainable using a single direct photolithography process. For example, a sacrificial layer is formed on the substrate and patterned using a photolithography process. A self-alignment process can be used to form a spacer along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure and the fin structure.

[0046] like Figures 1 to 5As shown, the nanostructure 122 and the fin structure 108 may extend along the X-axis. In some embodiments, the nanostructure 122 and the fin structure 108 may be disposed on the substrate 104. The nanostructure 122 may include a stack of nanostructures 122-1, 122-2, and 122-3, which may be in the form of nanosheets, nanowires, or nanoribbons. Each nanostructure 122 may serve as a channel structure and form a channel region below the gate structure 112 of the transistors 102A to 102B. In some embodiments, the nanostructure 122 and the fin structure 108 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon germanium. The semiconductor material of the nanostructure 122 and the fin structure 108 may be undoped or may be in-situ doped during the formation process thereof. In some embodiments, as Figures 2 to 5 As shown, the nanostructure 122 under the gate structure 112 can form a channel region of the semiconductor device 100 and represent a current carrying channel structure of the semiconductor device 100. In some embodiments, the nanostructure 122 can have a thickness in the range of about 5nm to about 8nm along the Z axis. In some embodiments, the nanostructure 122 can have a width in the range of about 15nm to about 50nm along the Y axis. In some embodiments, the nanostructure 122 can have a width in the range of about 15nm to about 25nm along the X axis. In some embodiments, the spacing between adjacent nanostructures 122 can be in the range of about 8nm to about 12nm along the Z axis. Although in Figures 2 to 4B Three layers of nanostructures 122 are shown in FIG. 1 , but transistors 102A to 102B may have any number of nanostructures 122 .

[0047] refer to Figures 2 to 4B , the gate dielectric layer 124 may be disposed on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer, but may include a high-k dielectric layer in direct contact with the nanostructure 122. In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer may have a thickness ranging from about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0048] In some embodiments, Figures 2 to 4BAs shown, the gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and a metal filler. The one or more work function metal layers may include a work function metal to tune the threshold voltage V of the transistors 102A to 102B. t In some embodiments, the gate structures 112 of the NFET and PFET devices may have substantially the same work function metal. In some embodiments, the gate structures 112 of the NFET and PFET devices may have different work function metals. Figures 2 to 4B As shown, each nanostructure 122 may be surrounded by a gate structure 112, and thus, the gate structure 112 may be referred to as a "gate all around (GAA) structure", and the transistors 102A-102B may also be referred to as "GAA FETs 102A-102B". One or more work function metal layers may surround the nanostructure 122, and may include work function metal to tune the V of the transistors 102A-102B. t In some embodiments, transistors 102A-102B may include any number of work function metal layers for V t Tuning (e.g., ultra-low V t , Low V t , and standard V t ). In some embodiments, Figure 4A As shown, gate structure 112 may have a height 112h along the Z-axis above the top surface of STI region 106. In some embodiments, height 112h may be in a range from about 80 nm to about 120 nm.

[0049] In some embodiments, the NFETs 102A to 102B may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium silicon nitride, or other suitable work function metals. In some embodiments, the PFETs 102A to 102B may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium silicon nitride, tantalum nitride, tungsten nitride carbon, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a metal layer stack. The metal layer stack may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0050] refer to Figure 2 and Figure 3According to some embodiments, the gate spacer 114 may be disposed on the sidewall of the gate structure 112 and in contact with the gate dielectric layer 124. The internal spacer 121 may be disposed adjacent to the end of the nanostructure 122 and between the S / D structure 110 and the gate structure 112. The gate spacer 114 and the internal spacer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low-k material, and a combination of the foregoing. In some embodiments, the gate spacer 114 and the internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114 and the internal spacer 121 may include different insulating materials. In some embodiments, the gate spacer 114 and the internal spacer 121 may include a single insulating layer or an insulating layer stack. In some embodiments, the gate spacer 114 and the internal spacer 121 may have a low-k dielectric material having a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8).

[0051] The S / D structure 110 may be disposed on the fin structure 108 and on the opposite side of the gate structure 112. The S / D structure 110 may be used as an S / D region of the transistors 102A to 102B. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, a cone, a rhombus, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material (e.g., silicon germanium) different from the material of the substrate 104, and stress may be applied to the channel region under the gate structure 112. Since the lattice constant of such epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is stressed to increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenide phosphide.

[0052] In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped using n-type dopants (e.g., phosphorus and arsenic) during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors may be used, such as phosphine, arsine, and other n-type doping precursors. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped using p-type dopants (e.g., boron, indium, and gallium) during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors may be used, such as diborane (B2H6), boron trifluoride (BF3), and other p-type doping precursors.

[0053] In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. In some embodiments, each of the one or more epitaxial layers may include Si and may differ from one another based on, for example, doping concentration and / or epitaxial growth process conditions. In some embodiments, each of the one or more epitaxial layers may include silicon germanium and may differ from one another based on, for example, doping concentration, epitaxial growth process conditions, and / or a relative concentration of germanium relative to silicon.

[0054] refer to Figures 1 to 5 , the trench isolation structure 113 may be disposed on the substrate 104 and on the edge between different diffusion regions (e.g., n and p regions). In some embodiments, the trench isolation structure 113 may include a liner 113A and a dielectric filler 113B. In some embodiments, the liner 113A may include silicon nitride, silicon carbonitride, or other suitable dielectric materials. The dielectric filler 113B may include silicon oxide, silicon oxynitride, silicon oxycarbonitride, or other suitable dielectric materials. In some embodiments, the liner 113A may protect the nanostructure 122, the fin structure 108, and the substrate 104 (e.g., to prevent oxidation) during the formation of the dielectric filler 113B. In some embodiments, the trench isolation structure 113 may extend through the gate structure 112, the nanostructure 122, the STI region 106, and the fin structure 108 into the substrate 104. In some embodiments, the trench isolation structure 113 may be formed by a CPODE and / or CMODE process to reduce leakage current flowing through the S / D structure 110, the nanostructure 122, and the substrate 104. In some embodiments, Figure 4A As shown, if the CPODE or CMODE process has a high selective etching, the trench isolation structure 113 may surround a portion of the STI region 106. Figure 4BAs shown, if the CPODE or CMODE process has a low selectivity etch, the trench isolation structure 113 may extend through the STI region 106 into the substrate 104. The bottom surface of the trench isolation structure 113 may have two recesses corresponding to two bumps 128-1 and 128-2 (collectively referred to as "bumps 128") on the substrate 104.

[0055] In some embodiments, Figures 1 to 5 As shown, the trench isolation structure 113 may extend over two fin structures 108. In some embodiments, the trench isolation structure 113 may extend over one or more than two fin structures 108. Figure 3 As shown, the trench isolation structure 113 may have a height 113h from the bottom surface of the trench isolation structure 113 to the top surface of the top nanostructure 122-3 along the Z axis. The height 113h may be in the range from about 100nm to about 200nm. If the height 113h is less than about 100nm, the trench isolation structure 113 cannot extend through the STI region 106 and the leakage current cannot be reduced. If the height 113h is greater than about 200nm, the well structure of the transistors 102A to 102B may be damaged and the device performance may be reduced. In addition, the leakage current cannot be further reduced, and the manufacturing cost may increase.

[0056] refer to Figures 1 to 5 , the dielectric frame structure 120 may be disposed on the STI region 106 and between adjacent nanostructures 122. In some embodiments, as Figure 1 As shown, the dielectric framework structure 120 and the nanostructure 122 may be disposed on the substrate 104 in an alternating configuration. Figures 1 to 5Two dielectric frame structures 120 are shown in FIG, but the semiconductor device 100 may have any number of dielectric frame structures 120. In some embodiments, the dielectric frame structure 120 may include a hard dielectric material. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, or other suitable dielectric materials. In some embodiments, the dielectric frame structure 120 may include a single dielectric layer or a dielectric layer stack having different hard dielectric materials. In some embodiments, the dielectric frame structure 120 may extend through the gate structure 112 in a vertical direction and may be used as a gate isolation structure, such as a CPO or CMG dielectric structure. The dielectric frame structure 120 may electrically isolate the gate structure 112 into multiple parts. In some embodiments, the dielectric frame structure 120 may have a high etch resistance to remain after various etching processes. In some embodiments, the top surfaces of the dielectric frame structure 120, the trench isolation structure 113, the gate structure 112, the ILD layer 118, and the gate spacer 114 may be substantially coplanar. In some embodiments, the end of the trench isolation structure 113 may contact the dielectric frame structure 120.

[0057] In some embodiments, Figure 4A As shown, the dielectric frame structure 120 may have a height 120h in the range of about 100 nm to about 150 nm along the Z axis. In some embodiments, the ratio of the height 120h to the height 112h may be in the range from about 1 to about 1.5. In some embodiments, the dielectric frame structure 120 may have a width 120w in the range of about 10 nm to about 20 nm along the Y axis. In some embodiments, the dielectric frame structure 120 may extend to a depth 120d in the STI region 106 in the range of about 50 nm to about 70 nm along the Z axis. The bottom surface of the dielectric frame structure 120 may be lower than the top surface of the STI region 106. If the bottom surface of the dielectric frame structure 120 is higher than the top surface of the STI region 106, the height 120h is less than about 100 nm, the ratio is less than about 1, or the width 120w is less than about 10 nm, the dielectric frame structure 120 may not electrically isolate the adjacent gate structure 112. If the height 120h is greater than about 150 nm, the ratio is greater than about 1.5, the depth 120d is greater than about 70 nm, or the width 120w is greater than about 20 nm, gate isolation cannot be further improved and manufacturing costs may increase.

[0058] In some embodiments, the dielectric frame structure 120 can reduce deformation of the substrate 104 and minimize the LDE effect of the semiconductor device 100 on the substrate 104. Figure 3 As shown, the gate structure 112 can be substantially vertical relative to the X-axis and the Y-axis (e.g., the top surface of the nanostructure 122). In some embodiments, the gate structure 112 adjacent to the trench isolation structure 113 can be tilted, and the tilt is less than about 2 degrees. In some embodiments, the tilt angle of the gate structure 112 at the isolation area and the dense area can vary, and the variation is less than about 1 degree. Therefore, the dielectric frame structure 120 can reduce the leakage current caused by the equal-density depth loading effect, minimize the damage to the S / D epitaxial structure caused by the equal-density critical dimension loading effect, and reduce the V of the semiconductor device 100 caused by the gate deformation. t drift.

[0059] In some embodiments, the dielectric frame structure 120 may be formed by a CPO process or a CMG process. The trench isolation structure 113 may be formed by a CPODE process or a CMODE process. In some embodiments, the process for forming the dielectric frame structure 120 may be identified from the interface between the gate structure 112 and the dielectric frame structure 120. In addition, the process for forming the trench isolation structure 113 may be identified from the interface between the gate structure 112 and the trench isolation structure 113. For example, Figure 5 As shown, if the sidewall surface of the dielectric frame structure 120 is covered with the gate structure 112, the dielectric frame structure 120 can be formed by a CMG process. If the sidewall surface of the dielectric frame structure 120 is covered with a gate dielectric layer 124, the dielectric frame structure 120 can be formed by a CPO process. If the sidewall surface of the trench isolation structure 113 is covered with the gate structure 112, the trench isolation structure 113 can be formed by a CMODE process. If the sidewall surface of the trench isolation structure 113 is covered with a gate dielectric layer 124, the trench isolation structure 113 can be formed by a CPODE process.

[0060] refer to Figures 2 to 4B, ESL 116 may be disposed on the S / D structure 110 and / or on the sidewalls of the gate spacer 114. The ESL 116 may be configured to protect the S / D structure 110 and / or the gate structure 112 during the formation of an S / D contact structure on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination of the foregoing. In some embodiments, after the S / D structure 110 is formed by an S / D film scheme having high etch resistance, the ESL 116 may be optional and may be skipped. In some embodiments, Figures 21 to 44 as well as Figures 46 to 83 In FIG. 1 , the ESL 116 may not be shown on the S / D structure 110 .

[0061] The ILD layer 118 may be disposed on the ESL 116 above the S / D structure 110. The ILD layer 118 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material. For example, flowable chemical vapor deposition (FCVD) may be used to deposit flowable silicon oxide. In some embodiments, the dielectric material may include silicon oxide.

[0062] In some embodiments, the semiconductor device 100 may further include an S / D contact structure, a gate contact structure, metal lines, metal vias, interconnects, and additional ILD layers, which are not described in detail for clarity.

[0063] Figure 6 is a flow chart of a method 600 for manufacturing a semiconductor device 100 having a dielectric frame structure according to some embodiments. The method 600 may not be limited to nanostructured transistor devices, and may be applied to other devices that benefit from a dielectric frame structure. Additional manufacturing operations may be performed between various operations of the method 600, and may be omitted for clarity and ease of description only. Additional processes may be provided before, during, and / or after the method 600; one or more of these additional processes are briefly described herein. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in parallel. Figure 6 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0064] For the purpose of illustration, reference will be made to Figures 7 to 44 An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Figure 6 The operation shown. Figure 7 A top view of a semiconductor device 100 having a dielectric frame structure is shown in accordance with some embodiments. Figures 8 to 44 A partial isometric view and partial cross-sectional views of a semiconductor device 100 having a dielectric frame structure at various stages of its fabrication are shown in accordance with some embodiments. Figure 8 , Fig.11 , Fig.14 , Fig.17 , Fig. 20 , Fig.23 , Fig.26 , Fig.29 , Fig.32 , Fig.35 , Fig.38 and Fig.41 A partial isometric view of a semiconductor device 100 is shown at various stages of its fabrication, in accordance with some embodiments. Fig. 9 , Fig.12 , Fig.15 , Fig.18 , Fig.21 , Fig.24 , Fig. 27 , Fig.30 , Fig.33 , Fig.36 , Fig.39 and Fig.42 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture along an X-axis (eg, Figure 2 A partial cross-sectional view along line AA) is shown. Fig.10 , Fig.13 , Fig.16 , Fig.19 , Fig. 22 , Fig.25 , Fig.28 , Fig.31 , Fig.34 , Fig.37 , Fig.40 , Fig.43 and Fig.44 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture along the Y-axis (eg, Figure 2 A partial cross-sectional view of line BB) shown. Figures 7 to 44 With Figures 1 to 5 The elements in the annotation are the same as the elements described above.

[0065] refer to Figure 6 The method 600 begins at operation 610 and forms a channel structure extending along a first direction on a substrate. Figures 7 to 10 As shown, a fin structure 108 may be formed on the substrate 104 along the X-axis. Figures 8 to 10As shown, the fin structure 108 can be used as a channel structure and is covered by a protective layer 815. In some embodiments, the protective layer 815 can be conformally deposited on the STI region 106 and the fin structure 108 to protect the fin structure 108 during a subsequent etching process. In some embodiments, the protective layer 815 can include silicon oxide or other suitable dielectric materials. In some embodiments, the channel structure can include a stack of nanostructures 122, as described below. Figure 56 to Figure 83 shown.

[0066] In some embodiments, the fin structure 108 may include a semiconductor material similar to or different from the substrate 104. Embodiments of the fin structure 108 disclosed herein may be patterned by any suitable method. For example, one or more photolithography processes (including a double patterning process or a multi-patterning process) may be used to pattern to obtain a nanostructure. A double patterning process or a multi-patterning process may combine a photolithography process with a self-alignment process to form a pattern having a spacing smaller than that obtainable using a single direct photolithography process, for example. For example, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-alignment process may be used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0067] In some embodiments, Figures 8 to 10As shown, a dielectric fin structure 819 may be formed on the STI region 106 and between adjacent fin structures 108. Capping layers 824 and 826 may be formed on the dielectric fin structure 819. In some embodiments, the dielectric fin structure 819 may include a hard dielectric material having a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material may include silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon, aluminum oxide, or other suitable dielectric materials. In some embodiments, capping layers 824 and 826 may have a high etch resistance to protect the dielectric fin structure 819 during subsequent etching processes. In some embodiments, the capping layer 824 may include silicon oxycarbon nitride or other suitable dielectric materials. In some embodiments, the capping layer 826 may include silicon nitride or other suitable dielectric materials. In some embodiments, one of the capping layer 824 or the capping layer 826 may be formed on the dielectric fin structure 819 to protect the dielectric fin structure 819. In some embodiments, the capping layers 824 and 826 may be optional. The subsequent etching process may be highly selective so that the capping layers 824 and 826 are not required to protect the dielectric fin structure 819. In some embodiments, the dielectric fin structure 819 and the capping layers 824 and 826 are optional, as shown in FIG. Fig.44 shown.

[0068] refer to Figure 6 In operation 620, a sacrificial gate structure extending in a second direction different from the first direction may be formed on the channel structure. Figures 7 to 10 As shown, a sacrificial gate structure 712 extending along the Y-axis may be formed on the fin structure 108. In some embodiments, the sacrificial gate structure 712 may include polysilicon or other suitable materials. In some embodiments, the sacrificial gate structure 712 may be deposited on the protective layer 815 over the fin structure 108, the dielectric fin structure 819, and the STI region 106. In some embodiments, the sacrificial gate structure 712 may be patterned to extend over the fin structure 108 along the Y-axis. In some embodiments, as Figures 8 to 10As shown, after forming the sacrificial gate structure 712, a gate spacer 114 may be formed on the sidewalls of the sacrificial gate structure 712. An ESL 116 and an ILD layer 118 may be formed between adjacent gate structures. In some embodiments, a chemical mechanical planarization (CMP) process may planarize the top surfaces of the sacrificial gate structure 712, the gate spacer 114, the ESL 116, and the ILD layer 118. In some embodiments, a hard mask layer 836 may be deposited on the planarized top surfaces of the sacrificial gate structure 712, the gate spacer 114, the ESL 116, and the ILD layer 118.

[0069] refer to Figure 6 In operation 630, an opening is formed in the sacrificial gate structure. Figures 8 to 16 As shown, an opening 820 may be formed in the sacrificial gate structure 712. In some embodiments, a stack of a bottom layer 838, an intermediate layer 840, and a photoresist 842 may be deposited on the hard mask layer 836. In some embodiments, the photoresist 842 above the sacrificial gate structure 712 may be patterned to obtain the opening 820, such as Figure 8 and Fig.10 After the patterning process, an opening 820 may be formed in the hard mask layer 836 by an etching process, as shown in FIG. Figures 11 to 13 shown.

[0070] In some embodiments, the dry etching process may remove the sacrificial gate structure 712 and extend the opening 820 through the sacrificial gate structure 712, such as Figures 14 to 16 In some embodiments, the opening 820 may expose the capping layer 826 on the dielectric fin structure 819, as shown in FIG. Figures 14 to 16 In some embodiments, without the dielectric fin structure 819 and the capping layers 824 and 826, the opening 820 may extend through the sacrificial gate structure 712 into the STI region 106, as shown in FIG. Figure 2 , FIG. 4A to FIG. 4B as well as Fig.44 As shown in the dielectric frame structure 120.

[0071] In some embodiments, the etching of the sacrificial gate structure 712 can be directional and self-aligned. The etchant can include a hydrogen bromide-based plasma with added oxygen or carbon dioxide. In some embodiments, the hydrogen bromide-based plasma can be a high-density plasma generated by an inductively coupled plasma or a resonant antenna plasma source with a radio frequency (RF) power generator. In some embodiments, the plasma etching process can use a bias power to increase the directionality of the etching process. In some embodiments, the etching process chamber can operate at a temperature from about 10° C. to about 200° C. at a pressure ranging from about 1 mTorr to about 200 mTorr.

[0072] refer to Figure 6 In operation 640, a dielectric material is filled in the opening to form a dielectric frame structure that is parallel to the channel structure and divides the sacrificial gate structure into two parts. Figures 17 to 19 As shown, a hard dielectric material may be blanket deposited on the hard mask layer 836 to fill the opening 820 and form the dielectric frame structure 120. In some embodiments, the dielectric frame structure 120 may extend parallel to the nanostructure 122 along the X-axis. In some embodiments, the dielectric frame structure 120 and the dielectric fin structure 819 may extend through the gate structure 112 in the vertical direction. The dielectric frame structure 120 and the dielectric fin structure 819 may electrically isolate the gate structure 112 into two parts. In some embodiments, as shown in FIG. Figure 2 , FIG. 4A to FIG. 4B as well as Fig.44 As shown in , the dielectric frame structure 120 may extend in a vertical direction through the gate structure 112 into the STI region 106 and may serve as a gate isolation structure, such as a CPO or CMG dielectric structure.

[0073] In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material may include silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon, aluminum oxide, or other suitable low-k dielectric materials. In some embodiments, the dielectric frame structure 120 may have a higher etch resistance and may be retained after etching during CPODE and CMODE processes. After forming the dielectric frame structure 120, a CMP process may be performed to flatten the top surface of the dielectric frame structure 120 and the sacrificial gate structure 712.

[0074] In some embodiments, Fig.17 and Fig.19As shown, the dielectric frame structure 120 and the fin structure 108 may be arranged in an alternating configuration on the substrate 104. In some embodiments, the bottom surface of the dielectric frame structure 120 may be higher than the top surface of the STI region 106, such as Figures 17 to 19 In some embodiments, the bottom surface of the dielectric frame structure 120 may be lower than the top surface of the STI region 106, such as Figure 2 , FIG. 4A to FIG. 4B as well as Fig.44 In some embodiments, the dielectric frame structure 120 can reduce the deformation of the substrate 104 caused by the CPODE or CMODE process and minimize the LDE effect of the semiconductor device 100 on the substrate 104. Therefore, the dielectric frame structure 120 can reduce the leakage current caused by the equal-density depth loading effect, minimize the damage to the S / D epitaxial structure caused by the equal-density critical dimension loading effect, and reduce the V of the semiconductor device 100 caused by the gate deformation. t drift.

[0075] refer to Figure 6 In operation 650, an isolation structure is formed adjacent to the sacrificial gate structure and extending through the channel structure into the substrate. Figures 20 to 43 As shown, a trench isolation structure 113 may be formed adjacent to the sacrificial gate structure 712 and extending through the fin structure 108 into the substrate 104. In some embodiments, an end of the trench isolation structure 113 may contact the dielectric frame structure 120. In some embodiments, the formation of the trench isolation structure 113 may include forming an opening 2313 through the sacrificial gate structure 712 and the fin structure 108 and depositing a dielectric material in the opening 2313. In some embodiments, as Figures 20 to 43 As shown, a protection layer 815 may be formed on the fin structure 108 and the dielectric fin structure 819 without any capping layer to protect the fin structure 108 and the dielectric fin structure 819 during a subsequent etching process. The subsequent etching process may be highly selective so that a capping layer is not needed to protect the dielectric fin structure 819.

[0076] In some embodiments, Figure 20 to Figure 22 As shown, a hard mask layer 2036 may be blanket deposited on the planarized top surface of the dielectric frame structure 120 and the sacrificial gate structure 712. In some embodiments, a stack of a bottom layer 2338, an intermediate layer 2340, and a photoresist 2342 may be deposited on the hard mask layer 2036. In some embodiments, patterning may be performed in the photoresist 2342 above the sacrificial gate structure 712 to obtain an opening 2313, such as Figure 23 to Figure 25 After the patterning process, an opening 2313 may be formed in the hard mask layer 2036 by a first etching process, as shown in FIG. Figure 26 to Figure 28shown.

[0077] In some embodiments, the second etching process may remove the sacrificial gate structure 712 and extend the opening 2313 through the sacrificial gate structure 712, such as Figure 29 to Figure 31 As shown. In some embodiments, the etching of the sacrificial gate structure 712 can be directional and self-aligned. The etchant can include a hydrogen bromide-based plasma with added oxygen or carbon dioxide. In some embodiments, the plasma etching process can use a bias power with zero source power to increase the directionality of the etching process. In some embodiments, the third etching process can remove the protective layer 815 on the fin structure 108 and the STI region 106, such as Figure 32 to Figure 34 In some embodiments, the fourth etching process may etch through the fin structure 108 and extend the opening 2313 into the substrate 104, as shown in FIG. Figure 35 to Figure 37 shown.

[0078] After forming the opening 2313 through the sacrificial gate structure 712 and the fin structure 108, a trench isolation structure 113 may be formed in the opening 2313, such as Figures 38 to 44 As shown. In some embodiments, the trench isolation structure 113 may include a liner 113A and a dielectric filler 113B. The liner 113A may be conformally deposited on the hard mask layer 2036, the substrate 104, the sidewalls of the STI region 106, the sidewalls of the dielectric fin structure 819, the sidewalls of the dielectric frame structure 120, and the sidewalls of the gate spacer 114. The dielectric filler 113B may be blanket deposited on the liner 113A, and the dielectric filler 113B may fill the opening 2313, as shown. Figures 38 to 40 In some embodiments, the CMP process may planarize the top surfaces of the gate spacer 114, the ESL 116, the ILD layer 118, the trench isolation structure 113, the dielectric frame structure 120, and the sacrificial gate structure 712. Fig.44 As shown, the dielectric frame structure 120 may extend through the sacrificial gate structure 712 into the STI region 106 without the dielectric fin structure 819. The dielectric frame structure 120 may contact the ends of the trench isolation structure 113.

[0079] In some embodiments, the trench isolation structure 113 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, or other suitable dielectric materials. In some embodiments, the trench isolation structure 113 may extend through the sacrificial gate structure 712, the STI region 106, and the fin structure 108 into the substrate 104. In some embodiments, the trench isolation structure 113 may be formed by a CPODE process to reduce leakage current flowing through the S / D structure 110, the fin structure 108, and the substrate 104.

[0080] refer to Figure 6 In operation 660, the sacrificial gate structure may be replaced with a metal gate structure. Figures 1 to 5 As shown, the sacrificial gate structure 712 may be replaced with a metal gate structure 112. In some embodiments, the replacement of the gate structure 112 may include removing the sacrificial gate structure 712 and depositing the gate structure 112, the process of which is not described in detail for the sake of clarity. In some embodiments, a trench isolation structure 113 may be formed after the replacement of the gate structure 112, such as Figures 45 to 83 As described.

[0081] Fig.45 is a flow chart of another method 4500 for manufacturing a semiconductor device 100 having a dielectric frame structure according to some embodiments. Method 4500 may not be limited to nanostructured transistor devices and may be applied to other devices that benefit from a dielectric frame structure. Additional manufacturing operations may be performed between various operations of method 4500 and may be omitted solely for clarity and ease of description. Additional processes may be provided before, during, and / or after method 4500; one or more of these additional processes are briefly described herein. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in parallel. Fig.45 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0082] For the purpose of illustration, reference will be made to Figures 46 to 83 An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Fig.45 The operation shown. Figures 46 to 83 Partial cross-sectional views of a semiconductor device 100 having a dielectric frame structure at various stages of fabrication using another method are shown in accordance with some embodiments. Fig.46 , Fig.48 , Fig.50 , Fig.52 , Fig.54 , Fig.64 , Fig.66 , Fig.68 , Fig.70 , Fig.72 , Fig.74 , Fig.76 , Fig.78 , Fig.80 and Fig.82 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of manufacturing using another method along an X-axis (eg, Figure 2 A partial cross-sectional view along line AA) is shown. Fig.47 , Fig.49 , Fig.51 , Fig.53 , Figure 55 to Figure 63 , Fig.65 , Fig.67 , Fig.69 , Fig.71 , Fig.73 , Fig.75 , Fig.77 , Fig.79 , Fig.81 and Fig.83 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of manufacturing using another method along the Y axis (eg, Figure 2 In some embodiments, Fig.56 , Fig.58 , Fig.60 and Fig.62 FIG. 1 shows a partial cross-sectional view of the semiconductor device 100 along the Y-axis above the STI region 106. In some embodiments, Fig.57 , Fig.59 , Fig.61 and Fig.63 A cross-sectional view of the semiconductor device 100 along the Y-axis over the nanostructure 122 is shown. Figures 46 to 83 With Figures 1 to 44 The elements in the annotation are the same as the elements described above.

[0083] refer to Fig.45 The method 4500 begins at operation 4510 and forms a channel structure extending along a first direction on a substrate. Fig.46 and Fig.47 As shown, a fin structure 108 may be formed on the substrate 104 along the X-axis, and the fin structure 108 may be used as a channel structure. Fig.46 and Fig.47 As shown, a gate dielectric layer 124 may be conformally deposited on the STI region 106 and the fin structure 108. In another example, as shown in FIG. Fig.56 and Fig.57 As shown, a stack of nanostructures 122 and fin structure 108 may be formed on substrate 104 along the X-axis, and nanostructures 122 may be used as channel structures. Fig.56 and Fig.57 As shown, a gate dielectric layer 124 may be conformally deposited on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, a highly selective etching process may be used to remove the gate dielectric layer 124 after the gate structure 112 is formed. Fig.56 , Fig.58 , Fig.60 and Fig.62The gate dielectric layer 124 may include a bump in the STI region 106 below the gate structure 112 in the nanostructure 122. In some embodiments, the gate dielectric layer 124 may be a multi-layer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer, but may include a high-k dielectric layer in direct contact with the nanostructure 122. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0084] refer to Fig.45 In operation 4520, a metal gate structure extending in a second direction different from the first direction may be formed on the channel structure. Fig.46 and Fig.47 As shown, a metal gate structure 112 extending along the Y axis may be formed on the fin structure 108. In another example, as shown in FIG. Fig.56 and Fig.57 As shown, the metal gate structure 112 may wrap around the nanostructure 122 and may extend along the Y-axis. In some embodiments, the gate structure 112 may include one or more work function metal layers and a metal filler.

[0085] In some embodiments, Fig.46 and Fig.47 As shown, the gate structure 112 may be deposited on the gate dielectric layer 124 over the fin structure 108, the dielectric fin structure 819, and the STI region 106. In some embodiments, as shown in FIG. Fig.56 and Fig.57 As shown, gate structure 112 may be deposited on gate dielectric layer 124 around nanostructure 122 and on gate dielectric layer 124 above fin structure 108 and STI region 106. In some embodiments, gate structure 112 may be patterned to extend along the Y axis. Fig.46 , Fig.47 , Fig.56 and Fig.57 As shown, gate spacers 114, ESL 116, and ILD layers 118 may be formed between adjacent gate structures 112. In some embodiments, as shown in FIG. Fig.46 and Fig.47 As shown, a hard mask layer 4644 may be formed on the ILD layer 118. In some embodiments, as shown in FIG. Fig.46 and Fig.47 As shown, the CMP process can planarize the top surfaces of the gate structure 112, the ESL 116, and the hard mask layer 4644. In some embodiments, a hard mask layer 4636 can be deposited on the planarized top surfaces of the gate structure 112, the ESL 116, and the hard mask layer 4644. In some embodiments, as shown in FIG. Fig.56 and Fig.57As shown, the CMP process can planarize the top surfaces of the gate structure 112, the gate spacer 114, the ESL 116, and the ILD layer 118. In some embodiments, as shown in FIG. Fig.56 and Fig.57 As shown, a hard mask layer 5636 may be deposited on the planarized top surface of the gate structure 112 , the gate spacers 114 , the ESL 116 , and the ILD layer 118 .

[0086] refer to Fig.45 , in operation 4530, an opening is formed in the metal gate structure. Figures 48 to 51 As shown, an opening 4820 may be formed in the metal gate structure 112. In another example, as shown in FIG. Figure 58 to Figure 61 As shown, an opening 5820 may be formed in the metal gate structure 112. In some embodiments, as shown in FIG. Fig.48 and Fig.49 As shown, a stack of bottom layer 4838, middle layer 4840, and photoresist 4842 may be deposited on hard mask layer 4636. An opening 4820 may be patterned in photoresist 4842 over gate structure 112. After the patterning process, one or more etching processes may remove hard mask layer 4636 and gate structure 112 below opening 4820, and may expose hard mask layer 4644, ESL 116, and dielectric fin structure 819, as shown. Fig.50 and Fig.51 In some embodiments, Fig.58 and Fig.59 As shown, a stack of bottom layer 5838, middle layer 5840, and photoresist 5842 may be deposited on hard mask layer 5836. An opening 5820 may be patterned in photoresist 5842 over gate structure 112. After the patterning process, one or more etching processes may remove hard mask layer 5836 and gate structure 112 below opening 5820, and may expose ILD layer 118 and STI region 106, as shown in FIG. Fig.60 and Fig.61 shown.

[0087] refer to Fig.45 In operation 4540, a dielectric material is filled in the opening to form a dielectric frame structure that is parallel to the channel structure and divides the metal gate structure into two parts. Fig.52 and Fig.53 As shown, a hard dielectric material may be blanket deposited on the hard mask layer 4636 to fill the opening 4820 and form the dielectric frame structure 120. In some embodiments, the dielectric frame structure 120 may extend parallel to the fin structure 108 along the X-axis. Fig.52 and Fig.53As shown, the dielectric frame structure 120 and the dielectric fin structure 819 may extend through the gate structure 112 in the vertical direction. The dielectric frame structure 120 and the dielectric fin structure 819 may electrically isolate the gate structure 112 into two parts. Fig.54 and Fig.55 As shown, a dielectric layer 5446 may be formed on the gate structure 112 for a self-aligned contact (SAC) process. One or more etching processes may etch through the hard mask layer 4636, the dielectric layer 5446, and the gate structure 112 to expose the dielectric fin structure 819. The dielectric frame structure 120 may contact the hard mask layer 4636, the hard mask layer 4644, the dielectric layer 5446, the ILD layer 118, and the dielectric fin structure 819. In another example, as shown in FIG. Fig.62 and Fig.63 As shown, a hard dielectric material may be blanket deposited on the hard mask layer 5636 to fill the opening 5820 and form the dielectric frame structure 120. In some embodiments, as shown in FIG. Figure 62 to Figure 65 As shown, the dielectric frame structure 120 can extend in a vertical direction through the gate structure 112 into the STI region 106 and can be used as a gate isolation structure, such as a CPO or CMG dielectric structure. Fig.65 As shown, the CMP process can planarize the top surface of the hard mask layer 5636 and the dielectric frame structure 120.

[0088] In some embodiments, the hard dielectric material in the dielectric frame structure 120 may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material may include silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon, aluminum oxide, or other suitable low-k dielectric materials. In some embodiments, the dielectric frame structure 120 may have a higher etch resistance and may be retained after etching during the CPODE and / or CMODE process.

[0089] In some embodiments, Fig.53 and Fig.55 As shown, the dielectric frame structure 120 and the fin structure 108 may be disposed on the substrate 104 in an alternating configuration. Figure 53 to Figure 56 As shown, the bottom surface of the dielectric frame structure 120 may be higher than the top surface of the STI region 106. In some embodiments, as shown in FIG. Figure 62 to Figure 65 As shown, the dielectric framework structure 120 and the nanostructure 122 may be arranged in an alternating configuration on the substrate 104. In some embodiments, as Figure 62 to Figure 65 As shown, the bottom surface of the dielectric frame structure 120 may be lower than the top surface of the STI region 106. In some embodiments, the dielectric frame structure 120 may reduce deformation of the substrate 104 caused by the CPODE or CMODE process and minimize the LDE effect of the semiconductor device 100 on the substrate 104. Therefore, the dielectric frame structure 120 may reduce leakage current caused by the equal-density depth loading effect, minimize damage to the S / D epitaxial structure caused by the equal-density critical dimension loading effect, and reduce the V of the semiconductor device 100 caused by gate deformation. t drift.

[0090] refer to Fig.45 In operation 4550, an isolation structure is formed adjacent to the metal gate structure and extending through the channel structure into the substrate. Figure 66 to Figure 83 As shown, a trench isolation structure 113 may be formed adjacent to the metal gate structure 112 and extending through the nanostructure 122 and the fin structure 108 into the substrate 104. In some embodiments, an end of the trench isolation structure 113 may contact the dielectric frame structure 120. In some embodiments, the formation of the trench isolation structure 113 may include forming an opening 6613 through the gate structure 112, the nanostructure 122, and the fin structure 108, and depositing a dielectric material in the opening 6613.

[0091] In some embodiments, Fig.66 and Fig.67 As shown, a stack of bottom layer 6636, middle layer 6640, and photoresist 6642 may be deposited on the planarized top surface of dielectric frame structure 120 and hard mask layer 5636. In some embodiments, patterning may be performed in photoresist 6642 over gate structure 112 to obtain opening 6613, such as Fig.66 and Fig.67 After the patterning process, an opening 6613 may be formed in the hard mask layer 6636 by a first etching process, as shown in FIG. Fig.68 and Fig.69 In some embodiments, the second etching process may remove the gate structure 112 and extend the opening 6613 through the gate structure 112, as shown in FIG. Fig.70 and Fig.71 In some embodiments, the etching of the gate structure 112 can be directional and self-aligned. In some embodiments, the third etching process can etch through the nanostructure 122 and the fin structure 108 and extend the opening 6613 into the substrate 104, as shown. Fig.72 and Fig.73In some embodiments, the second and third etching processes may have high etching selectivity, and the STI regions 106 between the fin structures 108 may not be removed after the third etching process.

[0092] After forming the opening 6613 passing through the gate structure 112, the nanostructure 122 and the fin structure 108, a trench isolation structure 113 may be formed in the opening 6613, such as Fig.74 and Fig.75 As shown. In some embodiments, the trench isolation structure 113 may include a liner 113A and a dielectric filler 113B. The liner 113A may be conformally deposited on the hard mask layer 5636, the substrate 104, the sidewalls of the STI region 106, the sidewalls of the dielectric frame structure 120, and the sidewalls of the gate spacer 114. The dielectric filler 113B may be blanket deposited on the liner 113A, and the dielectric filler 113B may fill the opening 6613, as shown. Fig.74 and Fig.75 In some embodiments, Fig.76 and Fig.77 As shown, the CMP process may planarize the top surfaces of the gate spacers 114, the ESL 116, the ILD layer 118, the trench isolation structure 113, the dielectric frame structure 120, and the gate structure 112. In some embodiments, the dielectric frame structure 120 may contact the ends of the trench isolation structure 113.

[0093] In some embodiments, Figure 78 to Figure 83 As shown, the gate structure 112, the nanostructure 122, and the fin structure 108 can be removed by a low-selectivity etching process. In some embodiments, the low-selectivity etching process can be directional and self-aligned. In some embodiments, the low-selectivity etching process can remove the gate structure 112, the nanostructure 122, and the fin structure 108, and form an opening 6613 to expose the substrate 104. In some embodiments, the low-selectivity etching process can form two bumps 128-1 and 128-2 on the substrate 104. After forming the opening 6613 passing through the gate structure 112, the nanostructure 122, and the fin structure 108, a trench isolation structure 113 can be formed in the opening 6613, as shown in FIG. Fig.80 and Fig.81 In some embodiments, Fig.82 and Fig.83 As shown, the CMP process may planarize the top surfaces of the gate spacers 114, the ESL 116, the ILD layer 118, the trench isolation structure 113, the dielectric frame structure 120, and the gate structure 112. In some embodiments, the dielectric frame structure 120 may contact the ends of the trench isolation structure 113.

[0094] In some embodiments, the trench isolation structure 113 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride or other suitable dielectric materials. In some embodiments, the trench isolation structure 113 may extend through the gate structure 112, the STI region 106 and the fin structure 108 into the substrate 104. In some embodiments, the trench isolation structure 113 may be formed by a CMODE process to reduce leakage current flowing through the S / D structure 110, the fin structure 108 and the substrate 104.

[0095] Various embodiments of the present disclosure provide methods for forming a dielectric frame structure 120 in a semiconductor device 100. In some embodiments, a channel structure extending in a first direction, such as a nanostructure 122 and a fin structure 108, may be formed on a substrate 104. A gate structure 112 extending in a second direction different from the first direction may be formed on the channel structure. Openings 820 and 5820 may be formed in the gate structure 112. Dielectric material may be filled in the openings 820 and 5820 to form a dielectric frame structure 120 that is parallel to the fin structure 108 and divides the gate structure 112 into two parts. In some embodiments, the dielectric frame structure 120 may include a hard dielectric material and extend in a first direction. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. A trench isolation structure 113 may be formed adjacent to the gate structure 112 and may extend through the nanostructure 122 and the fin structure 108 into the substrate 104. In some embodiments, the end of the trench isolation structure 113 may contact the dielectric frame structure 120. In some embodiments, the trench isolation structure 113 may be formed by a CPODE or CMODE process. In some embodiments, the dielectric frame structure 120 may be used as a gate isolation structure, such as a CPO or CMG dielectric structure. In some embodiments, the dielectric frame structure 120 may reduce deformation of the substrate 104 and minimize the LDE effect of the semiconductor device on the substrate 104. Therefore, the dielectric frame structure 120 may reduce device leakage current, minimize damage to the S / D epitaxial structure, and reduce the V t drift.

[0096] In some embodiments, a semiconductor structure includes: a channel structure on a substrate and extending in a first direction; a gate structure on the channel structure and extending in a second direction different from the first direction; a dielectric frame structure on the substrate and parallel to the channel structure; and an isolation structure adjacent to the gate structure and extending through the channel structure into the substrate. The dielectric frame structure includes a dielectric material extending through the gate structure to divide the gate structure into two parts. An end of the isolation structure contacts the dielectric frame structure.

[0097] In some embodiments, a semiconductor device includes: a plurality of channel structures on a substrate; a gate structure on the substrate and the plurality of channel structures, the plurality of channel structures including a dielectric material and extending through the gate structure to divide the gate structure into isolated portions; and an isolation structure extending along the gate structure and passing through at least one of the plurality of channel structures. The plurality of channel structures and the plurality of dielectric frame structures are arranged in an alternating configuration. The isolation structure contacts at least one of the plurality of dielectric frame structures.

[0098] In some embodiments, a method includes: forming a channel structure extending along a first direction on a substrate; forming a gate structure extending along a second direction different from the first direction on the channel structure; forming an opening in the gate structure; filling the opening with a dielectric material to form a dielectric frame structure parallel to the channel structure; and forming an isolation structure adjacent to the gate structure and extending through the channel structure into the substrate. The dielectric frame structure divides the gate structure into two parts. An end of the isolation structure contacts the dielectric frame structure.

[0099] It should be understood that the detailed description section (rather than the abstract section of the present disclosure) is intended to be used to interpret the claims. The abstract section of the present disclosure may set forth one or more embodiments, rather than all possible embodiments of the present disclosure contemplated by the inventor(s), and is therefore not intended to limit the appended claims in any way.

[0100] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a channel structure on the substrate and extending along a first direction; a gate structure on the channel structure and extending along a second direction different from the first direction; a dielectric frame structure on the substrate and parallel to the channel structure, wherein the dielectric frame structure includes a dielectric material extending through the gate structure to divide the gate structure into two portions; and An isolation structure is adjacent to the gate structure and extends through the channel structure into the substrate, wherein an end of the isolation structure contacts the dielectric frame structure.

2. The semiconductor structure according to claim 1, wherein: The dielectric material has a Young's modulus greater than about 75 GPa.

3. The semiconductor structure according to claim 1, wherein: A dielectric frame structure is between the gate structure and the isolation structure.

4. The semiconductor structure according to claim 1, wherein: Top surfaces of the gate structure, the dielectric frame structure, and the isolation structure are substantially coplanar.

5. The semiconductor structure according to claim 1, wherein: A bottom surface of the dielectric frame structure is higher than a bottom surface of the isolation structure.

6. The semiconductor structure according to claim 1, further comprising: A shallow trench isolation (STI) region is on the substrate and surrounds the channel structure, wherein the dielectric frame structure extends through the gate structure into the STI region.

7. The semiconductor structure according to claim 6, wherein: The isolation structure extends through the STI region into the substrate.

8. The semiconductor structure according to claim 6, wherein: A portion of the STI region is surrounded by the isolation structure and the substrate.

9. A semiconductor device comprising: a plurality of channel structures on a substrate; a gate structure on the substrate and the plurality of channel structures; a plurality of dielectric frame structures comprising a dielectric material and extending through the gate structure to divide the gate structure into isolated portions, wherein the plurality of channel structures and the plurality of dielectric frame structures are arranged in an alternating configuration; and An isolation structure extends along the gate structure and passes through at least one of the plurality of channel structures, wherein the isolation structure contacts at least one of the plurality of dielectric frame structures.

10. A method comprising: forming a channel structure extending along a first direction on a substrate; forming a gate structure extending along a second direction different from the first direction on the channel structure; forming an opening in the gate structure; filling the opening with a dielectric material to form a dielectric frame structure parallel to the channel structure, wherein the dielectric frame structure divides the gate structure into two parts; and An isolation structure is formed adjacent to the gate structure and extending through the channel structure into the substrate, wherein an end of the isolation structure contacts the dielectric frame structure.

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