Chip structure and preparation method thereof

Abstract

The embodiment of the invention provides a chip structure and a preparation method thereof, and the preparation method comprises the following steps: providing a substrate which comprises a first substrate, an indication layer and a second substrate; forming a plurality of conductive columns in the substrate, wherein each conductive column penetrates through the first substrate and the indication layer; a conductor rail layer is formed on the first substrate, the conductor rail layer comprises a plurality of conductor rails, and each conductor rail is connected with at least two conductive columns; a connecting layer and a device layer are formed on the conductor rail layer, the connecting layer comprises a medium part arranged on the conductor rail layer and provided with a plurality of connecting ports and conductive parts arranged in the connecting ports and connected with the conductor rail, the device layer is arranged on the connecting layer and comprises a plurality of thin film transistors, and the forming temperature of the thin film transistors is not larger than the preset temperature; forming a first interconnection layer on the device layer; and forming a second interconnection layer in the second substrate, wherein the thin film transistors are connected with the second interconnection layer through the conductive columns, the conductive rails, the conductive parts and the first interconnection layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip structure and a method for preparing the same. Background Art

[0002] Currently, the signal lines and power supply lines are interconnected on the front side of the chip. As the size of devices continues to shrink, the front side interconnection technology faces many challenges:

[0003] The reduction in the cross-sectional area of ​​interconnects leads to an increase in resistance, which further increases energy consumption and affects chip performance;

[0004] The reduction in space has led to a shortage of interconnect resources, and the miniaturization of process nodes is facing bottlenecks.

[0005] Therefore, a new chip structure is urgently needed. Summary of the invention

[0006] In view of the problems existing in the background technology, the embodiments of the present application provide a chip structure and a preparation method thereof, which avoids processes such as wafer bonding, whole wafer thinning, front and back side alignment, and nano-silicon vias, and greatly increases the types of metals that can be used as embedded metal conductive structures.

[0007] An embodiment of the first aspect of the present application provides a chip structure, which includes: a substrate, including a first substrate, an indication layer and a second substrate that are stacked; a plurality of conductive pillars, which are arranged in the substrate, and each conductive pillar penetrates the first substrate and the indication layer; a conductive track layer, which is arranged on the first substrate, and the conductive track layer includes a plurality of conductive tracks, and each conductive track is connected to at least two conductive pillars; a connecting layer, which includes a dielectric part arranged on the conductive track layer and having a plurality of connecting ports, and a conductive part arranged in the connecting ports and connected to the conductive tracks; a device layer, which is arranged on the connecting layer, and the device layer includes a plurality of thin film transistors, and a molding temperature of the thin film transistors is not greater than a preset temperature; a first interconnection layer, which is arranged on the device layer; and a second interconnection layer, which is arranged in the second substrate; wherein each thin film transistor is connected to the second interconnection layer via the conductive pillar, the conductive track, the conductive part and the first interconnection layer.

[0008] According to an embodiment of the first aspect of the present application, the first substrate, the indicator layer and the second substrate are an integrated structure.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the conductive pillars tend to become thicker along the direction from the second substrate to the first substrate.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the indicator layer is a silicon dioxide layer or a silicon germanium layer; and the first substrate and the second substrate are both silicon layers.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the thin film transistor is connected to the conductive part on the side facing the substrate; or, the first interconnect layer has an electrical connection part connecting the thin film transistor and the conductive part.

[0012] An embodiment of the second aspect of the present application provides a method for preparing a chip structure, the preparation method comprising the following steps: providing a substrate, the substrate comprising a first substrate, an indication layer and a second substrate which are stacked; forming a plurality of conductive pillars in the substrate, each conductive pillar penetrating the first substrate and the indication layer; forming a conductive track layer on the first substrate, the conductive track layer comprising a plurality of conductive tracks, each conductive track being connected to at least two conductive pillars; forming a connection layer and a device layer on the conductive track layer, the connection layer comprising a dielectric portion which is arranged on the conductive track layer and has a plurality of connection ports, and a conductive portion which is arranged in the connection ports and connected to the conductive tracks, the device layer being arranged on the connection layer, the device layer comprising a plurality of thin film transistors, the molding temperature of the thin film transistors being no greater than a preset temperature; forming a first interconnection layer on the device layer; forming a second interconnection layer in the second substrate, each thin film transistor being connected to the second interconnection layer via the conductive pillars, the conductive tracks, the conductive portions and the first interconnection layer.

[0013] According to an embodiment of the second aspect of the present application, the first substrate, the indicator layer and the second substrate are an integrated structure.

[0014] According to any of the aforementioned embodiments of the second aspect of the present application, the step of forming a plurality of conductive pillars in the substrate includes: using a first etchant to etch the first substrate to form a plurality of first through holes, each first through hole exposes the indicator layer to form a portion to be etched; using a second etchant to etch the portion to be etched to form a second through hole; depositing a plurality of conductive pillars and a conductive layer on the first substrate, the conductive pillars filling the first through holes and the second through holes, and the conductive layer is formed on the first substrate; and removing the conductive layer.

[0015] According to any of the aforementioned embodiments of the second aspect of the present application, in the first substrate and the indicator layer, the first etchant selectively etches the first substrate; in the indicator layer and the second substrate, the second etchant selectively etches the indicator layer.

[0016] According to any of the aforementioned embodiments of the second aspect of the present application, the steps of forming a connection layer and a device layer on the conductive track layer include: forming a dielectric material layer on the conductive track layer; patterning the dielectric material layer to form a dielectric portion having a plurality of connection ports; forming a conductive portion in the connection port; forming a device layer on the connection layer, and connecting the thin film transistor to the conductive portion on the side facing the substrate.

[0017] According to any of the aforementioned embodiments of the second aspect of the present application, the first interconnect layer has an electrical connection portion connecting the thin film transistor and the conductive portion, and the steps of forming a connection layer and a device layer on the conductive track layer include: forming a dielectric material layer on the conductive track layer; forming a device layer on the dielectric material layer; patterning the dielectric material layer to form a dielectric portion having multiple connection ports; and forming a conductive portion in the connection port.

[0018] In any of the aforementioned embodiments of the second aspect of the application, the step of forming the second interconnect layer in the second substrate includes: forming a window on the second substrate, the window exposing each conductive column; and forming the second interconnect layer in the window.

[0019] In the embodiments of the present application, a metal conductive structure is first formed in a substrate, and then a thin film transistor having a preparation temperature lower than a preset temperature is integrated on the metal conductive structure. Since the temperature for manufacturing the thin film transistor is relatively low, the selectable range of metals used for the metal conductive structure is greatly increased. For example, the most common metals such as copper can be used instead of high melting point metals such as tungsten. Processes such as wafer bonding and whole wafer thinning are avoided, as well as alignment problems encountered when forming a metal conductive structure on the back side and challenges of wafer-level processes are avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the embodiment of the present application, the following is a brief introduction to the drawings required for use in the embodiment of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are not drawn according to the true scale.

[0021] Figure 1 A schematic diagram of a chip structure provided for an embodiment of the first aspect of the present application;

[0022] Figure 2 A schematic structural diagram of another chip structure provided for an embodiment of the first aspect of the present application;

[0023] Figure 3 A flow chart of a method for preparing a chip structure provided for an embodiment of the second aspect of the present application;

[0024] Figure 4 A flow chart of forming a plurality of conductive pillars in a substrate provided for an embodiment of the second aspect of the present application;

[0025] Figure 5 A flow chart of forming a connection layer and a device layer on a conductive track layer provided for an embodiment of the second aspect of the present application;

[0026] Figure 6 A flow chart of forming a connection layer and a device layer on a conductive track layer provided for another embodiment of the second aspect of the present application;

[0027] Figure 7 A flow chart of forming a second interconnect layer in a second substrate provided for an embodiment of the second aspect of the present application;

[0028] Figures 8 to 26It is a schematic structural diagram of a product during the preparation process of the chip structure preparation method provided in the second aspect of the embodiment of the present application;

[0029] Figures 27 to 35 A schematic structural diagram of some products in a preparation process of a chip structure preparation method provided in another embodiment of the second aspect of the present application. Specific embodiments

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0031] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish an entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "include..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, in this article, the meaning of "multiple" is more than two, and "above" and "below" include the number.

[0032] Currently, the signal lines and power supply lines are interconnected on the front side of the chip. As the size of devices continues to shrink, the front side interconnection technology faces many challenges:

[0033] The reduction in the cross-sectional area of ​​interconnects leads to an increase in resistance, which further increases energy consumption and affects chip performance;

[0034] The reduction in space has led to a shortage of interconnect resources, and the miniaturization of process nodes is facing bottlenecks.

[0035] The back power supply technology in the related art requires that the device layer be connected to the back power supply network through conductive rails and conductive columns, while the back power supply technology based on traditional silicon-based devices adopts the following three solutions:

[0036] 1. Prepare the device layer and the front interconnection layer from the front side first, and then prepare the conductive tracks and conductive columns from the back side. However, this solution requires extreme thinning of the substrate and requires nanometer-level control, which is very difficult and can easily cause the silicon wafer to distort and deform, and there are difficulties in aligning the front and back sides;

[0037] 2. First, prepare the conductive track layer, device layer and front interconnect layer from the front side, and then prepare the conductive pillar from the back side. However, due to the high annealing temperature for preparing silicon-based devices, the types of metals used for the conductive track layer are very limited, and it is also difficult to align the conductive track and the conductive pillar;

[0038] 3. First prepare the conductive pillars and conductive track layer from the front side, and then prepare the device layer and the front interconnection layer. However, due to the high annealing temperature for preparing silicon-based devices, the types of metals used for conductive pillars and conductive track layers are very limited.

[0039] In order to solve the above technical problems, the embodiments of the present application provide a chip structure and a preparation method thereof, which avoids processes such as wafer bonding and whole wafer thinning, avoids the alignment problems faced when forming a metal conductive structure on the back, avoids the challenges of wafer-level processes, and greatly increases the types of metals that can be used as embedded metal conductive structures.

[0040] Optionally, the shape of the chip structure may be square, rectangular, circular, irregular, etc., which is not limited in the present application.

[0041] To better understand this application, Figures 1 to 35 The chip structure and preparation method thereof in the embodiments of the present application are described in detail.

[0042] Please refer to Figure 1 , Figure 1 A schematic structural diagram of a chip structure provided for an embodiment of the first aspect of the present application.

[0043] like Figure 1As shown, the chip structure includes a substrate 1, a plurality of conductive pillars 2, a conductive track layer 3, a connection layer 4, a device layer 5, a first interconnection layer 6 and a second interconnection layer 7. The substrate 1 includes a first substrate 11, an indication layer 13 and a second substrate 15 which are stacked. A plurality of conductive pillars 2 are arranged in the substrate 1, and each conductive pillar 2 passes through the first substrate 11 and the indication layer 13. The conductive track layer 3 is arranged on the first substrate 11. The conductive track layer 3 includes a plurality of conductive tracks 31, and each conductive track 31 is connected to at least two conductive pillars 2. The connection layer 4 includes a first conductive track 31 arranged on the first substrate 11. A dielectric portion 43 having a plurality of connection ports 41 on the conductive track layer 3 and a conductive portion 45 disposed in the connection port 43 and connected to the conductive track 31, a device layer 5 disposed on the connection layer 4, the device layer 5 including a plurality of thin film transistors 51, a molding temperature of the thin film transistors 51 being no greater than a preset temperature, a first interconnection layer 6 disposed on the device layer 5, and a second interconnection layer 7 disposed in the second substrate 15, wherein each thin film transistor 51 is connected to the second interconnection layer 7 via the conductive column 2, the conductive track 31, the conductive portion 45 and the first interconnection layer 6.

[0044] Among them, multiple conductive pillars 2 and multiple conductive rails 31 are metal conductive structures arranged adjacent to the chip structure and the thin film transistor 51. The metal conductive structure can not only be used for power supply, but also for signal transmission, that is, the electricity conducted by the metal conductive structure includes power supply electricity and signal electricity; the first interconnection layer 6 serves as the front interconnection layer, and the second interconnection layer 7 serves as the back interconnection layer.

[0045] The conductive rails 31 are connected to a certain number of conductive pillars 2 according to processing accuracy and design requirements.

[0046] Optionally, one conductive rail 31 may be connected to two, three, four, five, six, etc. conductive pillars 2 .

[0047] Optionally, the orthographic projection of the conductive track 31 on the second substrate 15 covers the orthographic projection of the conductive pillar 2 on the second substrate 15 .

[0048] Exemplarily, the width of the orthographic projection of the conductive track 31 on the second substrate 15 is greater than the width of the orthographic projection of the conductive pillar 2 on the second substrate 15 .

[0049] Optionally, the conductive pillar 2 may have a cylindrical structure or a sheet structure.

[0050] Optionally, the thickness of the second substrate 15 is greater than the thickness of the first substrate 11 .

[0051] Optionally, the thickness direction is a direction from the second substrate 15 to the first substrate 11 .

[0052] Optionally, the thin film transistor 51 refers to a transistor whose active layer is not in the substrate 1 but is deposited outside the substrate 1. The channel thickness of this type of transistor is generally very small (can reach nanometer level), so it is called a thin film transistor. Since the channel of the thin film transistor 51 is not in the substrate 1, it does not need to perform high temperature annealing and other technologies used in the manufacture of silicon-based transistors, so the manufacturing temperature is generally low.

[0053] Optionally, during the formation of the thin film transistor 51 , the temperature required for the process of forming the active layer of the thin film transistor 51 on the connection layer 4 is the highest. Therefore, the formation temperature of the thin film transistor 51 generally refers to the formation temperature of the active layer of the thin film transistor 51 .

[0054] Optionally, the thin film transistor 51 has a source, a drain and a gate, and the sources and drains of the multiple thin film transistors 51 are connected to the second interconnection layer 7 via multiple conductive parts 45, multiple conductive tracks 31 and multiple conductive pillars 2, and the gates of the multiple thin film transistors 51 are connected to the second interconnection layer 7 via multiple conductive parts 45, the first interconnection layer 6, multiple conductive tracks 31 and multiple conductive pillars 2, and the second interconnection layer 7 is also used to connect to the power supply and signal source of the external circuit, so as to realize the connection between the multiple thin film transistors 51 and the external circuit. That is, the signal lines and power lines of the multiple thin film transistors 51 are led out from the back of the chip structure via multiple conductive pillars 2, multiple conductive tracks 31, the first interconnection layer 6 and the second interconnection layer 7.

[0055] Optionally, the thin film transistor 51 may be directly connected to the conductive portion 45 or may be indirectly connected to the conductive portion 45 .

[0056] like Figure 1 As shown, in some optional embodiments, the first interconnection layer 6 has an electrical connection portion 61 connecting the thin film transistor 51 and the conductive portion 45. The electrical connection portion 61 is used to connect the conductive portion 45 to the thin film transistor 51 from the side of the thin film transistor 51 away from the substrate 1 or the side of the thin film transistor 51, that is, the thin film transistor 51 is indirectly connected to the conductive portion 45 through the electrical connection portion 61. The side of the thin film transistor 51 connects the side of the thin film transistor 51 facing the substrate 1 and the side of the thin film transistor 51 away from the substrate 1.

[0057] like Figure 2 As shown, in some optional embodiments, the side of the thin film transistor 51 facing the substrate 1 is connected to the conductive portion 45 so that the conductive track 31 can be connected to the thin film transistor 51 from the side of the thin film transistor 51 facing the substrate 1, that is, the thin film transistor 51 is directly connected to the conductive portion 45.

[0058] Optionally, in the first interconnection layer 6 and the second interconnection layer 7, at least the first interconnection layer 6 has signal line interconnection, and the gates of multiple thin film transistors 51 are interconnected through the signal lines to form a signal network; the second interconnection layer 7 has power line interconnection, and the source and drain electrodes of the multiple thin film transistors 51 are connected to the power line interconnection through multiple conductive parts 45, multiple conductive columns 2 and multiple conductive rails 31, so that the power line interconnection interconnects the source and drain electrodes of the multiple thin film transistors 51 to form a power supply network.

[0059] In some optional embodiments, only when the first interconnection layer 6 has signal line interconnection, the chip structure is a chip structure dominated by power supply requirements, and only the signal IO port is led out from the back; when the first interconnection layer 6 and the second interconnection layer 7 both have signal line interconnection, the second interconnection layer 7 forms a power supply network and performs high-density wiring of back functional signals, a certain proportion of the conductive track 31 is used to conduct signals, and another part is used to conduct power, and this proportion is determined by processing accuracy and design requirements, each thin film transistor 51 is connected to the conductive track 31 for power supply, and some thin film transistors 51 are connected to the conductive track 31 for signal conduction according to design requirements, that is, the chip structure is a chip structure dominated by both signal and power supply requirements.

[0060] Optionally, the second interconnect layer 7 also has multiple pads, including a first pad 7A, a second pad 7B and a third pad 7C. The first pad 7A and the second pad 7B respectively lead out the negative power line and the positive power line to connect to the power supply of the external circuit, and the third pad 7C leads out the signal line to connect to the signal source of the external circuit.

[0061] Optionally, the size of the pad is larger than the size required to contact two adjacent conductive pillars 2 .

[0062] Optionally, the first pad 7A is connected to at least one conductive pillar 2 , and the second pad 7B is connected to at least one conductive pillar 2 .

[0063] Optionally, the first interconnection layer 6 and the second interconnection layer 7 are both interconnection layers formed by a Damascus process.

[0064] In some embodiments, the preset temperature is the maximum temperature that the conductive pillar 2 and the conductive track 31 can withstand. If the molding temperature of the device layer 5 is higher than the preset temperature, at least one of the conductive pillar 2 and the conductive track 31 will be affected by melting or / and a significant decrease in electron mobility. That is, the molding temperature of the thin film transistor 51 is not greater than the maximum temperature that the conductive pillar 2 and the conductive track 31 can withstand. Since the molding temperature of the device layer 5 mainly depends on the molding temperature of the device, the thin film transistor 51 with a lower molding temperature is used as the device of the device layer 5, so the range of choices for the conductive metal material used in the metal conductive structure is greatly increased, such as the most common metals such as copper can be used, instead of high melting point metals such as tungsten.

[0065] Optionally, the conductive column 2 and the conductive track 31 are made of the same conductive metal material. That is, the preset temperature is not greater than the melting temperature of the conductive metal material used to prepare the conductive column 2 and the conductive track 31 or / and the temperature threshold at which the electron mobility of the conductive metal material of the conductive column 2 and the conductive track 31 is significantly reduced. Among them, when the preset temperature is the temperature threshold at which the electron mobility of the conductive metal material of the conductive column 2 and the conductive track 31 is significantly reduced, if the molding temperature of the thin film transistor 51 is higher than the preset temperature, it will cause the electron mobility of at least one of the conductive column 2 and the conductive track 31 to be significantly reduced. If the molding temperature of the thin film transistor 51 is lower than the preset temperature, the electron mobility of any one of the conductive column 2 and the conductive track 31 will be less affected by temperature changes.

[0066] Optionally, the conductive pillar 2 and the conductive rail 31 are made of common conductive metals such as copper.

[0067] In some optional embodiments, the preset temperature is no greater than 400°C.

[0068] Exemplarily, the preset temperature may be 400° C., 390° C., 380° C., 370° C., 360° C., 350° C., 340° C., 330° C., 320° C., 310° C. or 300° C., etc. Of course, the preset temperature may also be any combination range of the above values.

[0069] In some embodiments, the preset temperature may also be the maximum temperature that the conductive pillar 2, the conductive track 31 and the conductive part 45 can withstand. The molding temperature of the device layer 5 being higher than the preset temperature may cause at least one of the conductive pillar 2, the conductive track 31 and the conductive part 45 to be affected by melting or / and a significant decrease in electron mobility. That is, the molding temperature of the thin film transistor 51 is not greater than the maximum temperature that the conductive pillar 2, the conductive track 31 and the conductive part 45 can withstand. Since the molding temperature of the device layer 5 mainly depends on the molding temperature of the device, a thin film transistor 51 with a lower molding temperature is used as the device of the device layer 5, so that the range of choices for the conductive metal material used for the metal conductive structure and the conductive part 45 is greatly increased, such as the most common metals such as copper can be used, instead of high melting point metals such as tungsten.

[0070] Optionally, the conductive pillar 2 , the conductive rail 31 and the conductive portion 45 may be made of the same conductive metal material.

[0071] In some optional embodiments, the thin film transistor includes but is not limited to an indium gallium zinc oxide thin film transistor or a carbon nanotube thin film transistor.

[0072] In these embodiments, the indium gallium zinc oxide thin film transistor refers to a transistor using indium gallium zinc oxide as a semiconductor material, that is, the active layer includes indium gallium zinc oxide material; the carbon nanotube thin film transistor refers to a transistor using carbon nanotubes as a semiconductor material, that is, the active layer includes carbon nanotubes.

[0073] Optionally, a plurality of conductive rails 31 are arranged at intervals.

[0074] Optionally, the conductive track layer 3 further includes a plurality of electrical isolation portions 33 , and two adjacent conductive tracks 31 are spaced apart by the electrical isolation portions 33 .

[0075] Optionally, the electrical isolation portion 33 is formed by a photolithography process.

[0076] Optionally, a protection layer 8 is further provided on the first interconnect layer 6 .

[0077] Optionally, the protective layer 8 is an insulating material layer.

[0078] In some embodiments, the first substrate 11 , the indicator layer 13 and the second substrate 15 are an integral structure.

[0079] The first substrate 11, the indicator layer 13 and the second substrate 15 are an integrated structure, which means that the first substrate 11, the indicator layer 13 and the second substrate 15 form a whole with good structural integrity, and there is no splicing transition area between the first substrate 11 and the indicator layer 13, and between the indicator layer 13 and the second substrate 15. In addition, the first substrate 11, the indicator layer 13 and the second substrate 15 are an integrated structure, which is different from the first substrate 11 and the indicator layer 13, and between the indicator layer 13 and the second substrate 15, which are connected by bonding or the like. Therefore, the chip structure does not require a bonding process during the molding process.

[0080] In some embodiments, the conductive pillars 2 tend to be thicker along the direction from the second substrate 15 to the first substrate 11. That is, a through hole is formed in the substrate 1, which penetrates the first substrate 11 and the indicator layer 13 and is filled with the conductive pillars 2, and the aperture of the through hole tends to increase along the direction from the second substrate 15 to the first substrate 11.

[0081] Optionally, the conductive pillars 2 gradually become thicker along the direction from the second substrate 15 to the first substrate 11 .

[0082] Optionally, the conductive pillar 2 gradually thickens in a linear thickening trend.

[0083] Optionally, among the first substrate 11 and the indicator layer 13 , the first substrate 11 may be selectively etched, that is, a certain etchant only etches the first substrate 11 but does not etch the indicator layer 13 .

[0084] Optionally, in the second substrate 15 and the indicator layer 13, both the second substrate 15 and the indicator layer 13 can be selectively etched. That is, in the second substrate 15 and the indicator layer 13, when the second substrate 15 is selectively etched, a certain etchant only etches the second substrate 15 but does not etch the indicator layer 13; and when the indicator layer 13 is selectively etched, a certain etchant only etches the indicator layer 13 but does not etch the second substrate 15.

[0085] Optionally, the materials of the first substrate 11, the indicator layer 13 and the second substrate 15 are known materials. Accordingly, the etchant for selectively etching the first substrate 11, the indicator layer 13 and the second substrate 15 and the method for etching the materials of the first substrate 11, the indicator layer 13 and the second substrate 15 are also known etchants and etching methods, and the embodiments of the present application do not make specific limitations on this.

[0086] Optionally, the first substrate 11 and the second substrate 15 may be made of the same material.

[0087] In these embodiments, the indicator layer 13 is a silicon dioxide layer or a silicon germanium layer.

[0088] It can be understood that in other embodiments, the indicator layer 13 may also be other insulating materials.

[0089] In these embodiments, the first substrate 11 and the second substrate 15 are both silicon layers.

[0090] Please refer to 3 to Fig.35 , Figure 3 A flow chart of a method for preparing a chip structure provided for an embodiment of the second aspect of the present application; Figure 4 A flow chart of forming a plurality of conductive pillars in a substrate provided for an embodiment of the second aspect of the present application; Figure 5 A flow chart of forming a connection layer and a device layer on a conductive track layer provided for an embodiment of the second aspect of the present application; Figure 6 A flow chart of forming a connection layer and a device layer on a conductive track layer provided for another embodiment of the second aspect of the present application; Figure 7 A flow chart of forming a second interconnect layer in a second substrate provided for an embodiment of the second aspect of the present application; Figures 8 to 26 It is a schematic structural diagram of a product during the preparation process of the chip structure preparation method provided in the second aspect of the embodiment of the present application; Figures 27 to 35 A schematic diagram of the structure of some products in the process of preparing a chip structure provided by another embodiment of the second aspect of the present application. Fig.14 for Fig.15 Cross-sectional view along AA direction, Fig.17 for Fig.16 Cross-sectional view along AA direction, Fig. 22 for Fig.21 Top view after removing the device layer. Fig.29 for Fig.30 Cross-sectional view along the AA direction.

[0091] like Figure 3 As shown, an embodiment of the second aspect of the present application provides a method for preparing a chip structure, the preparation method comprising the following steps:

[0092] Step S1: Figure 8 As shown, a substrate 1 is provided, and the substrate 1 includes a first substrate 11, an indicator layer 13 and a second substrate 15 which are stacked.

[0093] Optionally, the thickness of the second substrate 15 is greater than the thickness of the first substrate 11 .

[0094] Optionally, the thickness direction is a direction from the second substrate 15 to the first substrate 11 .

[0095] Step S2: Fig.12 As shown, a plurality of conductive pillars 2 are formed in the substrate 1 , and each conductive pillar 2 penetrates the first substrate 11 and the indicator layer 13 .

[0096] Step S3: Fig.16 As shown, a conductive track layer 3 is formed on the first substrate 11 , and the conductive track layer 3 includes a plurality of conductive tracks 31 , each of which is connected to at least two conductive pillars 2 .

[0097] The conductive rails 31 are connected to a certain number of conductive pillars 2 according to processing accuracy and design requirements.

[0098] Optionally, one conductive rail 31 may be connected to two, three, four, five, six, etc. conductive pillars 2 .

[0099] Optionally, the orthographic projection of the conductive track 31 on the second substrate 15 covers the orthographic projection of the conductive pillar 2 on the second substrate 15 .

[0100] Exemplarily, the width of the orthographic projection of the conductive track 31 on the second substrate 15 is greater than the width of the orthographic projection of the conductive pillar 2 on the second substrate 15 .

[0101] Step S4: Fig. 20 As shown in the figure, a connection layer 4 and a device layer 5 are formed on the conductive track layer 3. The connection layer 4 includes a dielectric portion 43 provided on the conductive track layer 3 and having a plurality of connection ports 41 and a conductive portion 45 provided in the connection ports 41 and connected to the conductive track 31. The device layer 5 is provided on the connection layer 4. The device layer 5 includes a plurality of thin film transistors 51. The molding temperature of the thin film transistors 51 is not greater than a preset temperature.

[0102] Optionally, the thin film transistor 51 refers to a transistor whose active layer is not in the substrate 1 but is deposited outside the substrate 1. The channel thickness of this type of transistor is generally very small (can reach nanometer level), so it is called a thin film transistor. Since the channel of the thin film transistor 51 is not in the substrate 1, it does not need to perform high temperature annealing and other technologies used in the manufacture of silicon-based transistors, so the manufacturing temperature is generally low.

[0103] Step S5: Fig.23 and Fig.32 As shown, a first interconnection layer 6 is formed on the device layer 5 .

[0104] Step S6: Fig.25 , 26 As shown in FIGS. 34 and 35 , a second interconnection layer 7 is formed in the second substrate 15 , and each thin film transistor 51 is connected to the second interconnection layer 7 via the conductive pillar 2 , the conductive track 31 , the conductive portion 45 and the first interconnection layer 6 .

[0105] Optionally, the first interconnect layer 6 is formed by a Damascus process.

[0106] Optionally, the second interconnect layer 7 is formed by a Damascus process.

[0107] Optionally, the thin film transistor 51 has a source, a drain and a gate, and the sources and drains of the multiple thin film transistors 51 are connected to the second interconnection layer 7 via multiple conductive parts 45, multiple conductive tracks 31 and multiple conductive pillars 2, and the gates of the multiple thin film transistors 51 are connected to the second interconnection layer 7 via multiple conductive parts 45, the first interconnection layer 6, multiple conductive tracks 31 and multiple conductive pillars 2, and the second interconnection layer 7 is also used to connect to the power supply and signal source of the external circuit, so as to realize the connection between the multiple thin film transistors 51 and the external circuit. That is, the signal lines and power lines of the multiple thin film transistors 51 are led out from the back of the chip structure via multiple conductive pillars 2, multiple conductive tracks 31, the first interconnection layer 6 and the second interconnection layer 7.

[0108] Optionally, in the first interconnection layer 6 and the second interconnection layer 7, at least the first interconnection layer 6 has signal line interconnection, and the gates of multiple thin film transistors 51 are interconnected through the signal lines to form a signal network; the second interconnection layer 7 has power line interconnection, and the source and drain electrodes of the multiple thin film transistors 51 are connected to the power line interconnection through multiple conductive parts 45, multiple conductive columns 2 and multiple conductive rails 31, so that the power line interconnection interconnects the source and drain electrodes of the multiple thin film transistors 51 to form a power supply network.

[0109] In some embodiments, the first substrate 11 , the indicator layer 13 and the second substrate 15 are an integral structure.

[0110] The first substrate 11, the indicator layer 13 and the second substrate 15 are an integrated structure, which means that the first substrate 11, the indicator layer 13 and the second substrate 15 form a whole with good structural integrity, and there is no splicing transition area between the first substrate 11 and the indicator layer 13, and between the indicator layer 13 and the second substrate 15. In addition, the first substrate 11, the indicator layer 13 and the second substrate 15 are an integrated structure, which is different from the first substrate 11 and the indicator layer 13, and the indicator layer 13 and the second substrate 15 are connected by bonding or the like. Therefore, the chip structure does not require a bonding process during the molding process.

[0111] Optionally, the first substrate 11 and the second substrate 15 are formed on the indicator layer 13 through a growth process so that the first substrate 11, the indicator layer 13 and the second substrate 15 are an integrated structure.

[0112] In some embodiments, the preset temperature is no greater than 400°C.

[0113] In some embodiments, the thin film transistor 51 is an indium gallium zinc oxide thin film transistor or a carbon nanotube thin film transistor. The forming temperature of the indium gallium zinc oxide thin film transistor or the carbon nanotube thin film transistor is not greater than 400°C.

[0114] like Figure 4 As shown, in some embodiments, step S2 includes:

[0115] Step S21: Fig. 9 As shown, the first substrate 11 is etched using a first etchant to form a plurality of first through holes 111 , and each of the first through holes 111 exposes the indicator layer 13 to form a to-be-etched portion 131 .

[0116] The diameter of the first through hole 111 gradually decreases from the first substrate 11 to the indicator layer 13 .

[0117] Step S22: Fig. 9 and Fig.10 As shown, the to-be-etched portion 131 is etched using a second etchant to form a second through hole 133 .

[0118] The diameter of the second through hole 133 gradually decreases from the first substrate 11 to the indicator layer 13 .

[0119] Step S23: Fig.10 and Fig.11 As shown, a plurality of conductive pillars 2 and a conductive layer 2A are deposited on the first substrate 11 , the conductive pillars 2 fill the first through holes 111 and the second through holes 133 , and the conductive layer 2A is formed on the first substrate 11 .

[0120] Optionally, the plurality of conductive pillars 2 and the conductive layer 2A are formed at one time from a metal material through a deposition process.

[0121] Optionally, the metal material includes copper.

[0122] Optionally, the conductive pillar 2 may adopt a cylindrical structure or a sheet structure.

[0123] Step S24: Fig.11 and Fig.12 As shown, the conductive layer 2A is removed.

[0124] In some embodiments, in the first substrate 11 and the indicator layer 13 , the first etchant selectively etches the first substrate 11 ; in the indicator layer 13 and the second substrate 15 , the second etchant selectively etches the indicator layer 13 .

[0125] In these embodiments, the indicator layer 13 is a silicon dioxide layer or a silicon germanium layer.

[0126] It can be understood that in other embodiments, the indicator layer 13 may also be other insulating materials.

[0127] In these embodiments, the first substrate 11 and the second substrate 15 are both silicon layers. Among them, in the first substrate 11 and the indicator layer 13, the first etchant for selectively etching the first substrate 11 can be a known etchant, and in the indicator layer 13 and the second substrate 15, the second etchant for selectively etching the indicator layer 13 can also be a known etchant. The present application does not specifically limit the components and content of the first etchant and the components and content of the second etchant.

[0128] In these embodiments, the first substrate 11 and the second substrate 15 are the same material layer and the first substrate 11 and the second substrate 15 can be etched using the same etchant.

[0129] In these embodiments, the conductive layer 2A may be removed by a grinding process.

[0130] like Figure 5 As shown, in some embodiments, step S3 includes:

[0131] Step S31: Fig.13 As shown, an electrical isolation layer 30 is deposited on the first substrate 11 .

[0132] Step S32: Fig.14 and Fig.15 As shown, the electrical isolation layer 30 is patterned to form a plurality of filling holes 32 and a plurality of electrical isolation portions 33 . Two adjacent electrical isolation portions 33 are separated by the filling holes 32 . Each filling hole 32 exposes at least two conductive pillars 2 .

[0133] Optionally, the electrical isolation layer 30 is patterned by a photolithography process.

[0134] Optionally, the material of the electrical isolation layer 30 is a known material that can be patterned by a photolithography process, which is not specifically limited in the embodiment of the present application.

[0135] Step S33: Fig.16 and Fig.17 As shown, a conductive track 31 is formed in each filling hole 32, and each conductive track 31 is connected to at least two conductive pillars 2. That is, two adjacent conductive tracks 31 are arranged at intervals through an electrical isolation portion 33 so that the two adjacent conductive tracks 31 are electrically isolated through the electrical isolation portion 33.

[0136] Optionally, the material of the conductive track 31 is the same as that of the conductive column 2 .

[0137] like Figure 6 and Fig.26 As shown, in some embodiments, the first interconnect layer 6 has an electrical connection portion 61 connecting the thin film transistor 51 and the conductive portion 45; step S4 includes:

[0138] Step S41: Fig.18 As shown, a dielectric material layer 4A is formed on the conductive track layer 3.

[0139] Step S42: Fig.19 As shown, a device layer 5 is formed on the dielectric material layer 4A.

[0140] Step S43: Fig. 20 As shown, the dielectric material layer 4A is patterned to form a dielectric portion 43 having a plurality of connection openings 41. The connection openings 41 expose the conductive tracks 31.

[0141] Step S44: Fig.21 and Fig. 22 As shown, a conductive portion 45 is formed in the connection port 41 .

[0142] In some optional embodiments, since the device layer 5 is formed first and then the conductive part 45 is formed, the preset temperature is the maximum temperature that the conductive pillar 2 and the conductive track 31 can withstand. The molding temperature of the device layer 5 is higher than the preset temperature, which will cause at least one of the conductive pillar 2 and the conductive track 31 to melt or / and the electron mobility to drop significantly. That is, the molding temperature of the thin film transistor 51 is not greater than the maximum temperature that the conductive pillar 2 and the conductive track 31 can withstand. Since the molding temperature of the device layer 5 mainly depends on the molding temperature of the device, the thin film transistor 51 with a lower molding temperature is used as the device of the device layer 5, so the range of choices for the conductive metal material used in the metal conductive structure is greatly increased, such as the most common metals such as copper can be used, instead of high melting point metals such as tungsten.

[0143] like Figure 5 As shown, in some embodiments, step S4 includes:

[0144] Step S41: Fig. 27 As shown, a dielectric material layer 4A is formed on the conductive track layer 3.

[0145] Step S42: Fig.28 As shown, the dielectric material layer 4A is patterned to form a dielectric portion 43 having a plurality of connection ports 41 .

[0146] Step S43: Fig.29 and 30 As shown, a conductive portion 45 is formed in the connection port 41 .

[0147] Step S44: Fig.31 As shown, a device layer 5 is formed on the connection layer 4 , and a side of the thin film transistor 51 facing the substrate 1 is connected to the conductive portion 45 .

[0148] In some optional embodiments, since the device layer 5 is formed first and then the conductive part 45 is formed, the preset temperature is the maximum temperature that the conductive pillar 2, the conductive track 31 and the conductive part 45 can withstand. The molding temperature of the device layer 5 is higher than the preset temperature, which will cause at least one of the conductive pillar 2, the conductive track 31 and the conductive part 45 to melt or / and the electron mobility to drop significantly. That is, the molding temperature of the thin film transistor 51 is not greater than the maximum temperature that the conductive pillar 2, the conductive track 31 and the conductive part 45 can withstand. Since the molding temperature of the device layer 5 mainly depends on the molding temperature of the device, the thin film transistor 51 with a lower molding temperature is used as the device of the device layer 5, so the range of choices for the conductive metal material used for the metal conductive structure and the conductive part 45 is greatly increased. For example, the most common metals such as copper can be used, and high melting point metals such as tungsten are not necessarily used.

[0149] In some optional embodiments, the device layer 5 can be formed by using a known thin film transistor manufacturing process.

[0150] Exemplarily, taking the thin film transistor 51 as a carbon nanotube thin film transistor as an example, the step of forming the device layer 5 includes:

[0151] Self-assembled solution method for deposition of carbon nanotubes;

[0152] Selectively etching a portion of the carbon nanotubes;

[0153] Annealing treatment in vacuum environment at 400℃;

[0154] Preparation of carbon nanotube thin film transistors by wet stripping process.

[0155] The steps of preparing the carbon nanotube thin film transistor by wet stripping process include:

[0156] Graphic imaging;

[0157] Thin film deposition, including deposition of gate metal and gate dielectric;

[0158] Graphic transfer.

[0159] When depositing the gate dielectric, the hafnium oxide may be grown at a low temperature of 90° C. or at a high temperature of 250° C. or 300° C.

[0160] Among them, in the step of selectively etching part of the carbon nanotubes, the carbon nanotubes at the location of the power line leading out from the front are etched away, and the carbon nanotubes used to form the carbon nanotubes between the carbon nanotubes used to form the PMOS and the carbon nanotubes used to form the NMOS are used to play an isolation role, etc. The power line is used to connect to the carbon nanotubes.

[0161] like Figure 7 As shown, in some embodiments, step S6 includes:

[0162] Step S61: Fig.25 and Fig.34 As shown, a window 151 is formed on the second substrate 15 , and the window 151 exposes each conductive pillar 2 .

[0163] Optionally, the second substrate 15 is etched using a first etchant to form a window 151 .

[0164] Step S62: Fig.26 and Fig.35 As shown, a second interconnect layer 7 is formed in the window 151 .

[0165] Optionally, the second interconnect layer 7 has a multi-layer structure. During the preparation of the second interconnect layer 7, planarization treatment needs to be performed on each layer. For example, spin-on glass (SoG) is used as an insulating layer to locally planarize each layer of the second interconnect layer 7.

[0166] like Figure 3 As shown, in some embodiments, after step S5, the preparation method further includes:

[0167] Step S7: Fig.24 and Fig.33 As shown, a protection layer 8 is deposited on the first interconnect layer 6 .

[0168] Optionally, the protective layer 8 is an insulating material layer.

[0169] Optionally, step S6 may be any step after step S2. Specifically, step S6 may be performed after step S2 and before step S3, or after step S3 and before step S4, or after step S4 and before step S5, or after step S5 and before step S7, or after step S7.

[0170] Exemplarily, step S6 is performed after step S7. Because the back side of the wafer must be turned over to perform step S6, and the front side of the turned wafer is placed on the carrier, if the protective layer 8 is not formed on the front side, the finished structure may be damaged.

[0171] like Figure 3 As shown, exemplarily, step S6 may be performed after step S7.

[0172] In the embodiment of the present application, a metal conductive structure is first formed in the substrate 1, and then a thin film transistor 51 with a preparation temperature lower than a preset temperature is integrated on the metal conductive structure. Since the temperature for manufacturing the thin film transistor 51 is relatively low, the range of metals available for the metal conductive structure is greatly increased. For example, the most common metals such as copper can be used, and high melting point metals such as tungsten are not necessarily used. In addition, processes such as wafer bonding, whole wafer thinning, front and back alignment, and nano-silicon through-holes are avoided, thus avoiding the challenges of wafer-level processes. In addition, since each conductive track 31 is connected to at least a conductive column 2, it is beneficial to increase the arrangement density of the conductive columns 2 per unit area of ​​the substrate 1, and thus it is beneficial to provide a wiring density per unit area of ​​the chip structure. At the same time, since the conductive track 31 in the conductive track layer 3 occupies a large area (the metal is track-shaped), the yield of depositing the thin film transistor 51 on such a surface is not high. Therefore, compared with directly making the thin film transistor 51 on the conductive track layer 3, the embodiment of the present application provides a connecting layer 4 on the conductive track layer 3. Regardless of whether the thin film transistor 51 is made directly on the dielectric material layer 4A or directly on the connecting layer 4 (the conductive portion 45 in the connecting layer 4 is columnar or sheet-shaped and occupies a very small area), the surface properties of the thin film transistor deposition are more uniform, which is conducive to the deposition of the thin film transistor 51.

[0173] by Figure 3 The flowchart shown is taken as an example, and refer to Figures 8 to 26 A method for preparing a chip packaging substrate provided in an embodiment of the present application is illustrated by way of example. Figures 8 to 26 It is a structural schematic diagram of an intermediate product in the preparation process of the chip structure preparation method provided in the second aspect of the embodiment of the present application.

[0174] Step 1: Figure 8As shown, a substrate 1 is provided, and the substrate 1 includes a first substrate 11, an indicator layer 13 and a second substrate 15 which are stacked.

[0175] Step 2: Fig. 9 As shown, the first substrate 11 is etched using a first etchant to form a plurality of first through holes 111 , and each of the first through holes 111 exposes the indicator layer 13 to form a to-be-etched portion 131 .

[0176] Step 3: Fig. 9 and Fig.10 As shown, the to-be-etched portion 131 is etched using a second etchant to form a second through hole 133 .

[0177] Step 4: Fig.10 and Fig.11 As shown, a plurality of conductive pillars 2 and a conductive layer 2A are deposited on the first substrate 11 , the conductive pillars 2 fill the first through holes 111 and the second through holes 133 , and the conductive layer 2A is formed on the first substrate 11 .

[0178] Step 5: Fig.11 and Fig.12 As shown, the conductive layer 2A is removed.

[0179] Step 6: Fig.13 As shown, an electrical isolation layer 30 is deposited on the first substrate 11 .

[0180] Step 7: Fig.14 and Fig.15 As shown, the electrical isolation layer 30 is patterned to form a plurality of filling holes 32 and a plurality of electrical isolation portions 33 . Two adjacent electrical isolation portions 33 are separated by the filling holes 32 . Each filling hole 32 exposes at least two conductive pillars 2 .

[0181] Step 8: Fig.16 and Fig.17 As shown, a conductive track 31 is formed in each filling hole 32, and each conductive track 31 is connected to at least two conductive pillars 2. That is, two adjacent conductive tracks 31 are arranged at intervals through an electrical isolation portion 33 so that the two adjacent conductive tracks 31 are electrically isolated through the electrical isolation portion 33.

[0182] Step 9: Fig.18 As shown, a dielectric material layer 4A is formed on the conductive track layer 3.

[0183] Step 10: Fig.19 As shown, a device layer 5 is formed on the dielectric material layer 4A.

[0184] Step 11: Fig. 20 As shown, the dielectric material layer 4A is patterned to form a dielectric portion 43 having a plurality of connection openings 41. The connection openings 41 expose the conductive tracks 31.

[0185] Step 12: Fig.21 and Fig. 22 As shown, a conductive portion 45 is formed in the connection port 41 .

[0186] Step 13: Fig.23 As shown, a first interconnection layer 6 is formed on the device layer 5 .

[0187] Step 14: Fig.24 As shown, a protection layer 8 is deposited on the first interconnect layer 6 .

[0188] Step 15: Fig.25 As shown, a window 151 is formed on the second substrate 15 , and the window 151 exposes each conductive pillar 2 .

[0189] Step 16: Fig.26 As shown, a second interconnect layer 7 is formed in the window 151 .

[0190] The above is only a specific embodiment of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system described above can refer to the corresponding connection structure in the aforementioned system embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A chip structure, characterized in that: include: A substrate, comprising a first substrate, an indication layer and a second substrate which are stacked; A plurality of conductive pillars are disposed in the substrate, and each of the conductive pillars penetrates the first substrate and the indicator layer; A conductive track layer, disposed on the first substrate, the conductive track layer comprising a plurality of conductive tracks, each of the conductive tracks being connected to at least two of the conductive posts; A connection layer, comprising a dielectric portion disposed on the conductive track layer and having a plurality of connection ports, and a conductive portion disposed in the connection ports and connected to the conductive track; A device layer, disposed on the connection layer, the device layer comprising a plurality of thin film transistors, the molding temperature of the thin film transistors being no greater than a preset temperature; A first interconnect layer, disposed on the device layer; A second interconnect layer, disposed in the second substrate; Wherein, each of the thin film transistors is connected to the second interconnection layer via the conductive pillar, the conductive track, the conductive portion and the first interconnection layer.

2. The chip structure according to claim 1, characterized in that: The first substrate, the indicator layer and the second substrate are an integrated structure.

3. The chip structure according to claim 1, characterized in that: Along the direction from the second substrate to the first substrate, the conductive pillars tend to become thicker.

4. The chip structure according to claim 1, characterized in that: The indicator layer is a silicon dioxide layer or a silicon germanium layer; the first substrate and the second substrate are both silicon layers.

5. The chip structure according to claim 1, characterized in that: The thin film transistor is connected to the conductive part at a side facing the substrate; or the first interconnect layer has an electrical connection part connecting the thin film transistor and the conductive part.

6. A method for preparing a chip structure, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a first substrate, an indication layer and a second substrate which are stacked; forming a plurality of conductive pillars in the substrate, each of the conductive pillars passing through the first substrate and the indicator layer; forming a conductive track layer on the first substrate, wherein the conductive track layer comprises a plurality of conductive tracks, each of which is connected to at least two of the conductive posts; A connection layer and a device layer are formed on the conductive track layer, wherein the connection layer comprises a dielectric portion provided on the conductive track layer and having a plurality of connection ports, and a conductive portion provided in the connection ports and connected to the conductive track, and the device layer is provided on the connection layer, and the device layer comprises a plurality of thin film transistors, wherein the molding temperature of the thin film transistors is not greater than a preset temperature; forming a first interconnect layer on the device layer; A second interconnection layer is formed in the second substrate, and each of the thin film transistors is connected to the second interconnection layer via the conductive pillars, the conductive rails, the conductive portions and the first interconnection layer.

7. The preparation method according to claim 6, characterized in that: The first substrate, the indicator layer and the second substrate are an integrated structure.

8. The preparation method according to claim 6, characterized in that: The step of forming a plurality of conductive pillars in the substrate comprises: Using a first etchant to etch the first substrate to form a plurality of first through holes, each of the first through holes exposing the indicator layer to form a portion to be etched; Etching the to-be-etched portion using a second etchant to form a second through hole; Depositing a plurality of conductive pillars and a conductive layer on the first substrate, wherein the conductive pillars fill the first through holes and the second through holes, and the conductive layer is formed on the first substrate; The conductive layer is removed.

9. The preparation method according to claim 8, characterized in that: In the first substrate and the indicator layer, the first etchant selectively etches the first substrate; Among the indicator layer and the second substrate, the second etchant selectively etches the indicator layer.

10. The preparation method according to claim 6, characterized in that: The steps of forming a connection layer and a device layer on the conductive track layer include: forming a dielectric material layer on the conductive track layer; The dielectric material layer is patterned to form the dielectric portion having a plurality of the connection ports; forming the conductive portion in the connecting port; The device layer is formed on the connection layer, and the side of the thin film transistor facing the substrate is connected to the conductive part.

11. The preparation method according to claim 6, characterized in that: The first interconnect layer has an electrical connection portion connecting the thin film transistor and the conductive portion, and the step of forming a connection layer and a device layer on the conductive track layer comprises: forming a dielectric material layer on the conductive track layer; forming the device layer on the dielectric material layer; The dielectric material layer is patterned to form the dielectric portion having a plurality of the connection ports; The conductive portion is formed in the connection port.

12. The preparation method according to claim 6, characterized in that: The step of forming a second interconnect layer in the second substrate comprises: forming a window on the second substrate, wherein the window exposes each of the conductive pillars; The second interconnect layer is formed in the window.

Images