Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, at least two gate structures, a first gap wall structure and a second gap wall structure. The at least two gate structures are arranged on the substrate, each gate structure comprises a short side edge extending in the first direction and a long side edge extending in the second direction, and the short side edges are oppositely arranged. The first gap wall structure covers the long side edges of the two gate structures. The second gap wall structure covers the short side edges of the two gate structures at the same time, and the extension length of the second gap wall structure is larger than that of the short side edges of the two gate structures. Therefore, the first gap wall structure and the second gap wall structure achieve different insulation effects, thereby optimizing the operation performance of the semiconductor device.

Description

Technical Field

[0001] The present application relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device with a gate structure and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the invention

[0003] One of the purposes of the present application is to provide a semiconductor device, by providing spacer structures with different materials and / or film structures on different sides of the gate structure, so that the gate structure can achieve different insulation effects in different extension directions. As a result, the semiconductor device of the present application has a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device.

[0004] One of the purposes of the present application is to provide a method for manufacturing a semiconductor device, which forms spacer structures with different materials and / or film structures on different sides of a gate structure, thereby achieving different insulation effects in different extension directions. As a result, the semiconductor device manufactured by the manufacturing method of the present application can obtain an optimized component structure and performance, thereby improving its operating performance.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application provides a semiconductor device, including a substrate, at least two gate structures, a first spacer structure and a second spacer structure. The at least two gate structures are arranged on the substrate. The two gate structures respectively include short sides extending in a first direction and long sides extending in a second direction. The short sides of the two gate structures are arranged relative to each other. The first direction is perpendicular to the second direction. The first spacer structure covers the long sides of the two gate structures. The second spacer structure simultaneously covers the short sides of the two gate structures. The extension length of the second spacer structure in the first direction is greater than the extension length of the short sides of the two gate structures in the first direction.

[0006] To achieve the above-mentioned purpose, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising the following steps. A substrate is provided, and at least two gate structures are formed on the substrate. The two gate structures respectively include short sides extending in a first direction and long sides extending in a second direction, the short sides of the two gate structures are arranged relatively to each other, and the first direction is perpendicular to the second direction. A first spacer structure is formed on the long sides of the two gate structures. A second spacer structure is formed on the short sides of the two gate structures. Wherein, the extension length of the second spacer structure in the first direction is greater than the extension length of the short sides of the two gate structures in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of the embodiments of the present application and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figure 1 is a schematic top view of a semiconductor device according to the first embodiment of the present application;

[0009] Figure 2 for Figure 1 Schematic cross-sectional view taken along section lines A-A' and BB';

[0010] Figure 3 for Figure 1 A partial schematic diagram of the middle spacer structure and the gate structure;

[0011] Figure 4 for Figure 1 Another cross-sectional schematic diagram taken along section lines AA' and BB';

[0012] Figure 5for Figure 1 Another cross-sectional schematic diagram taken along section lines AA' and BB';

[0013] Figure 6 A schematic top view of a semiconductor device after forming a stacked layer structure according to a preferred embodiment of the present application;

[0014] Figure 7 is a schematic top view of a semiconductor device after a patterning process is performed;

[0015] Figure 8 is a schematic top view of a semiconductor device after a spacer structure is formed;

[0016] Fig. 9 is a schematic top view of a semiconductor device according to a second embodiment of the present application;

[0017] Fig.10 for Fig. 9 A partial schematic diagram of the middle spacer structure and the gate structure;

[0018] Fig.11 is a schematic top view of a semiconductor device according to a third embodiment of the present application;

[0019] Fig.12 for Fig.11 Partial schematic diagram of the middle gap wall structure and gate structure.

[0020] Description of reference numerals:

[0021] 10, 30, 40 Semiconductor devices

[0022] 100 Substrate

[0023] 101 Surrounding Area

[0024] 102 Shallow Trench Isolation

[0025] Unit 103

[0026] 104 Active Area

[0027] 110 Dielectric layer

[0028] 112 Silicon oxide layer

[0029] 114 Silicon nitride layer

[0030] 116 Silicon oxide layer

[0031] 120 Gate structure

[0032] 120t Top

[0033] 122 Semiconductor layer

[0034] 124 Barrier Layer

[0035] 126 Metal Layer

[0036] 128 Covering layer

[0037] 130, 330, 430 first spacer structure

[0038] 130e, 330e, 430e end

[0039] 140, 340, 440 Second spacer structure

[0040] 140t, 340t, 440t top surface

[0041] 142 first gate spacer

[0042] 144 second gate spacer

[0043] 146 The third gate spacer

[0044] 150 bit line structure

[0045] 150C Bit Line Plug

[0046] 152 Semiconductor layer

[0047] 154 Barrier

[0048] 156 Metal Layer

[0049] 158 Covering layer

[0050] 160 First line gap wall structure

[0051] 170 Second bit line spacer structure

[0052] 172 First Line Spacer

[0053] 174 Second bit line spacer

[0054] 176 Third bit line spacer

[0055] 178 Fourth bit line spacer

[0056] 180 Insulation layer

[0057] 182, 184 Insulation layer

[0058] 202, 204 openings

[0059] 220 Gate stack structure

[0060] 230 first gate spacer stacking structure

[0061] 250 bit line stacking layer structure

[0062] 260 First line spacer stacking structure

[0063] 280 Insulation material layer

[0064] BS1 First side wall

[0065] BS2 Second side wall

[0066] D1 First direction

[0067] D2 Second direction

[0068] D3 vertical direction

[0069] GS1 Short Side

[0070] GS2 Long Side

[0071] L1, L2, L3, L4 extension length

[0072] TS1 First top surface

[0073] TS2 Second top surface

[0074] TS3 Third top surface

[0075] W1 Width DETAILED DESCRIPTION

[0076] In order to enable those skilled in the art to further understand the present application, the following lists the preferred embodiments of the present application, and with the accompanying drawings, describes in detail the composition and intended effects of the present application. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present application.

[0077] Please refer to Figures 1 to 5 As shown, what is depicted is a schematic diagram of a semiconductor device 10 according to a first embodiment of the present application, wherein: Figure 1 is a schematic top view of a semiconductor device 10, Figure 2 , Figure 4 and Figure 5 are schematic cross-sectional views of the semiconductor device 10, respectively. Figure 3 A partial three-dimensional schematic diagram and a partial cross-sectional schematic diagram of the semiconductor device 10 are simultaneously presented.

[0078] First, if Figure 1 and Figure 2As shown, the semiconductor device 10 includes a substrate 100 , at least two gate structures 120 disposed on the substrate 100 , and a first spacer structure 130 and a second spacer structure 140 disposed on the at least two gate structures 120 .

[0079] The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and a cell region 103 with a relatively high device integration and a peripheral region 101 with a relatively low device integration are defined on the substrate 100. In one embodiment, the cell region 103 and the peripheral region 101 are, for example, Figure 1 and Figure 2 As shown, the substrate 100 is arranged adjacent to each other, but is not limited thereto. Figure 2 At least one shallow trench isolation 102 is shown, and a plurality of active regions 104 are defined in the peripheral region 101 and the cell region 103 of the substrate 100 .

[0080] Each gate structure 120 is disposed in the peripheral region 101 and specifically includes a short side GS1 extending in the first direction D1 and two long sides GS2 extending in a second direction D2 perpendicular to the first direction D1. The short sides GS1 of the two gate structures 120 are, for example, disposed opposite to each other in the second direction D2 and adjacent to each other. Figure 1 shown.

[0081] It should be particularly noted that the first spacer structure 130 completely covers the long side GS2 of the two gate structures 120, while the second spacer structure 140 is disposed between the two gate structures 120 and covers the short side GS1 of the two gate structures 120 adjacent to each other, and the extension length L1 of the second spacer structure 140 in the first direction D1 is greater than the extension length L2 of the short side GS1 of the gate structure 120 in the first direction D1. In one embodiment, the second spacer structure 140, for example, simultaneously spans the first spacer structure 130 disposed on the long side GS2 on both sides of the gate structure 120, so that its extension length L1 is preferably greater than the sum of the extension length L2 of the short side GS1 plus the twice width W1 of the first spacer structure 130 disposed on each long side GS2 of the gate structure 120 in the first direction D1 (L2+2×W1), such as Figure 1 As shown, but not limited to this. In this way, the first spacer structure 130 and the second spacer structure 140 can effectively isolate the contact between different sides of each gate structure 120 and adjacent components in different directions, so that the gate structure 120 can achieve different insulation effects in different extension directions. Under this arrangement, the semiconductor device 10 can have a more optimized component structure and performance, thereby improving its operating performance.

[0082] In one embodiment, the first spacer structures 130 respectively disposed on the long sides GS2 of the two gate structures 120 are, for example, spaced apart from each other in the second direction D2. That is, the first spacer structures 130 covering each long side GS2 of the gate structure 120 have ends 130e in the first direction D1, and the second spacer structures 140 simultaneously cover each end 130e of the first spacer structures 130, so that the first spacer structures 130 disposed on the long sides GS2 of the two gate structures 120 do not directly contact each other.

[0083] In another embodiment, if Figure 3 As shown, the first spacer structure 130 covering the long side GS2 of each gate structure 120 is also partially disposed below the second spacer structure 140, so that the first spacer structures 130 covering the long side GS2 of each gate structure 120 are in contact with each other, as shown in FIG. Figure 3 As shown. Moreover, due to the difference in etching selectivity, the first spacer structure 130 may have a first top surface TS1 and a second top surface TS2 with different heights in a vertical direction D3 perpendicular to the substrate 100. The second top surface TS2 of the first spacer structure 130 is disposed between the two gate structures 120 and below the second spacer structure 140, and may be entirely covered by the second spacer structure 140, while the first top surface TS1 of the first spacer structure 130 is located at a position not covered by the second spacer structure 140. The first top surface TS1 is higher than the second top surface TS2, and is slightly lower than the top surface 140t of the second spacer structure 140 or the top surface 120t of the gate structure 120, as shown in FIG. Figure 3 shown.

[0084] For example Figure 1 and Figure 2As shown, the semiconductor device 10 further includes a plurality of bit line structures 150, a first bit line spacer structure 160, and a second bit line spacer structure 170 disposed on the substrate 100. The bit line structures 150 are, for example, mutually spaced and extend in the first direction D1, and each bit line structure 150 includes two first side walls BS1 extending in the second direction D2 and two second side walls BS2 extending in the first direction D1. The two first side walls BS1 of each bit line structure 150 are, for example, disposed opposite to each other in the first direction D1, and the two second side walls BS2 of each bit line structure 150 are, for example, disposed opposite to each other in the second direction D2. The first bit line spacer structure 160 completely covers the first side wall BS1 of each bit line structure 150, and the second bit line spacer structure 170 completely covers the second side wall BS2 of each bit line structure 150. Thus, the first bit line spacer structure 160 and the second bit line spacer structure 170 can also effectively isolate the contact between different sidewalls of each bit line structure 150 and adjacent components, so that each bit line structure 150 can achieve different insulation effects in different extension directions.

[0085] In detail, each bit line structure 150 is, for example, disposed on the dielectric layer 110, and further includes a semiconductor layer 152 (for example, including semiconductor materials such as doped polysilicon and doped amorphous silicon), a barrier layer 154 (for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal layer 156 (for example, including low-resistance metal materials such as tungsten, aluminum or copper), and a cap layer 158 (for example, including insulating materials such as silicon nitride, silicon carbonitride or silicon oxynitride). Each bit line structure 150 is electrically connected to the active region 104 in the cell region 103 by extending into the substrate 100 through a bit line contact (BLC) formed thereunder correspondingly. In one embodiment, the dielectric layer 110 includes, for example, a silicon oxide layer 112, a silicon nitride layer 114 and a silicon oxide layer 116 stacked in sequence to have an oxide-nitride-oxide (ONO) structure. It should be noted that the manufacturing process of the gate structure 120 disposed in the peripheral region 101 is, for example, integrated with the manufacturing process of the bit line structure 150 disposed in the cell region 103, so that each gate structure 120 includes components and materials similar to each bit line structure 150. That is, each gate structure 120 in the peripheral region 101 is, for example, disposed on the silicon oxide layer 112, and also includes a semiconductor layer 122 (for example, including semiconductor materials such as doped polysilicon and doped amorphous silicon), a barrier layer 124 (for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal layer 126 (for example, including low-resistance metal materials such as tungsten, aluminum or copper) and a cap layer 128 (for example, including insulating materials such as silicon nitride, silicon carbonitride or silicon oxynitride), which are stacked in sequence, but the present invention is not limited thereto. In another embodiment, the manufacturing process of the gate structure may also be selected not to be integrated with the manufacturing process of the bit line structure 150, and include a metal gate structure or other suitable gate structure.

[0086] On the other hand, the manufacturing process of the first spacer structure 130 disposed on the long side GS2 of each gate structure 120 can also be selected to be integrated with the manufacturing process of the first bit line spacer structure 160 disposed on the first side wall BS1 of each bit line structure 150, so that the first spacer structure 130 includes components and materials similar to those of the first bit line spacer structure 160. For example, the first bit line spacer structure 160 and the first spacer structure 130 both include the following: Figure 1The single-layer structure shown, for example, all includes insulating materials such as silicon oxide, silicon oxynitride, silicon nitride or silicon carbonitride, but is not limited thereto. In another embodiment, the first bit line spacer structure and the first spacer structure can also be selected to include a composite layer structure with similar components and materials. The manufacturing process of the second spacer structure 140 arranged on the short side GS1 of each gate structure 120 can also be selected to be integrated with the manufacturing process of the second bit line spacer structure 170 arranged on the second side wall BS2 of each bit line structure 150, so that the second spacer structure 140 includes components and materials similar to the second bit line spacer structure 170, but is not limited thereto.

[0087] In one embodiment, the second bit line spacer structure 170, for example, includes a first bit line spacer 172 (for example, including silicon nitride, silicon carbonitride) arranged on the side wall of each bit line plug 150C, and a second bit line spacer 174 (for example, including silicon nitride, silicon carbonitride), a third bit line spacer 176 (for example, including silicon oxide, silicon oxynitride) and a fourth bit line spacer 178 (for example, including silicon nitride, silicon carbonitride) stacked in sequence on the second side wall BS2 of each bit line structure 150, and the second spacer structure 140 includes a first gate spacer 142 (for example, including silicon nitride, silicon carbonitride), a second gate spacer 144 (for example, including silicon oxide, silicon oxynitride) and a third gate spacer 146 (for example, including silicon nitride, silicon carbonitride) stacked in sequence on the short side GS1 adjacent to each other of the two gate structures 120, but is not limited to this. The material of the first gate spacer 142 is equal to the material of the second bit line spacer 174, the material of the second gate spacer 144 is equal to the material of the third bit line spacer 176, and the material of the third gate spacer 146 is equal to the material of the fourth bit line spacer 178. That is, the material of the second spacer structure 140 disposed in the peripheral region 101 can be completely equal to the material of the second bit line spacer structure 170 disposed in the cell region 103. Figure 2 In addition, the second spacer structure 140 is completely disposed on the shallow trench isolation 102. However, in other embodiments, the second spacer structure 240 may also be different due to differences in actual manufacturing process conditions. Figure 4 The structure shown includes a first gate spacer 142 (eg, including silicon nitride, silicon carbonitride) and a second gate spacer 144 (eg, including silicon oxide, silicon oxynitride) sequentially disposed on the short side edges GS1 of the two gate structures 120 adjacent to each other, or as shown in FIG. Figure 5The first gate spacer 142 (e.g., silicon nitride or silicon carbonitride) is only provided on the short side GS1 of the two gate structures 120, but the present invention is not limited thereto. Thus, the material of the second spacer structure 240 provided in the peripheral region 101 is partially equivalent to the material of the second bit line spacer structure 170 provided in the cell region 103.

[0088] In addition, the semiconductor device 10 further includes an insulating layer 180 and insulating layers 182 and 184 that are entirely covered on the substrate 100, and include insulating materials such as silicon oxide and silicon oxynitride. The insulating layer 180 is disposed around the gate structure 120, the first spacer structure 130, the bit line structure 150, and the first gate spacer structure 160, the insulating layer 182 is disposed between the second sidewalls BS2 of the adjacent bit line structures 150, and the insulating layer 184 is disposed on the insulating layer 180 and is also disposed around the gate structure 120 and the first spacer structure 130. In one embodiment, the insulating layer 180, the insulating layer 182, and the insulating layer 184 preferably include the same insulating material, so that the insulating layer 184 can be formed in an integral manner with the insulating layer 180 disposed therebelow, but the present invention is not limited thereto. Although other components are not specifically depicted in the drawings of this embodiment, those skilled in the art should be able to easily understand that the semiconductor device 10 of this embodiment may also include a plurality of word line structures (not shown) and a plurality of storage node plugs (not shown) disposed in the cell region 103. The word line structures are separated from each other and extend in a second direction D2 perpendicular to the bit line structures 150, and the storage node plugs are disposed between the bit line structures 150 to be electrically connected to the active region 104, receive and transmit voltage signals from the substrate 100 (such as the source or drain of a transistor component in the substrate 100). Thus, the semiconductor device 10 and the capacitor structure (not shown) disposed thereon can together constitute a dynamic random access memory (DRAM) device, and the transistor components and capacitors in the substrate 100 together constitute the smallest memory cell in the dynamic random access memory array to receive voltage information from the bit line structure 150 and the word line structure.

[0089] According to the semiconductor device 10 of the first embodiment of the present application, a first spacer structure 130 and a second spacer structure 140 with different materials and / or film structures are respectively arranged on the short side GS1 and the long side GS2 of the gate structure 120, so that the gate structure 120 can achieve different insulation effects in different extension directions through the arrangement of the first spacer structure 130 and the second spacer structure 140. In addition, the second spacer structure 140 is arranged between the two gate structures 120 and covers the short side GS1 of the two gate structures 120 adjacent to each other at the same time, and has an extension length L1 greater than the short side GS1. In this way, the second spacer structure 140 can effectively isolate the contact between the short side GS1 of each gate structure 120 and the adjacent components. Under this arrangement, the semiconductor device 10 can have a more optimized component structure and performance, thereby improving its operating performance.

[0090] In order to enable a person skilled in the art to which the present application belongs to easily understand the semiconductor device 10 of the present application, the manufacturing method of the semiconductor device 10 of the present application will be further described below.

[0091] See also Figures 6 to 8 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device in a preferred embodiment of the present application. First, Figure 6 As shown, a substrate 100 is provided, and shallow trench isolation 102 is formed in the peripheral region 101 and the cell region 103 of the substrate 100, and a plurality of active regions 104 are defined in the peripheral region 101 and the cell region 103 of the substrate 100. In one embodiment, the shallow trench isolation 102 is formed by, for example, first forming at least one trench (not shown) in the substrate 100 by etching, and then filling the at least one trench with an insulating material (such as silicon oxide or silicon oxynitride, etc.), but the present invention is not limited thereto. Next, a gate stack layer structure 220 and a bit line stack layer structure 250 are simultaneously formed on the peripheral region 101 and the cell region 103 of the substrate 100 by similar processes.

[0092] Specifically, before forming the gate stack layer structure 220 and the bit line stack layer structure 250, a silicon oxide layer 112 is first formed in the peripheral region 101 of the substrate 100, and a dielectric layer 110 (including the silicon oxide layer 112, the silicon nitride layer 114 and the silicon oxide layer 116 formed in sequence) is formed in the cell region 103. In one embodiment, the method for manufacturing the silicon oxide layer 112 in the peripheral region 101 and the dielectric layer 110 in the cell region 103 includes but is not limited to the following steps, for example, firstly forming a first oxide material layer (not shown), a nitride material layer (not shown) and a second oxide material layer (not shown) on the substrate 100 in sequence to cover the peripheral region 101 and the cell region 103 as a whole, and then removing the second oxide material layer and the nitride material layer covering the peripheral region 101. Alternatively, in another embodiment, the second oxide material layer, the nitride material layer and the first oxide material layer covering the peripheral region 101 may be completely removed, and then the oxide material layer (not shown) may be re-formed.

[0093] Then, a patterning process is performed with the aid of a mask layer (not shown) to partially remove the second oxide material layer, the nitride material layer, and the first oxide material layer in the cell region 103, thereby forming a plurality of openings (not shown) that can partially expose the substrate 100, so as to define the following: Figure 2 The formation position of the bit line plug 150C is shown, and then the mask layer is completely removed.

[0094] Next, semiconductor material layers (not shown, for example, including semiconductor materials such as doped polysilicon and doped amorphous silicon), barrier material layers (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), metal material layers (not shown, for example, including low-resistance metal materials such as tungsten, aluminum or copper) and capping material layers (not shown, for example, including insulating materials such as silicon nitride, silicon carbonitride or silicon oxynitride) are stacked in sequence from bottom to top on the peripheral area 101 and the unit area 103.

[0095] Then, another patterning process is performed with the aid of another mask layer (not shown) to partially remove the capping material layer, the metal material layer, the semiconductor material layer, the barrier material layer, and the first oxide material layer sequentially stacked in the peripheral region 101 to form a gate stack structure 220 and the like. Figure 2 The silicon oxide layer 112 is shown, and then another mask layer is completely removed, and the capping material layer, the metal material layer, the semiconductor material layer, the barrier material layer, the second oxide material layer, the nitride material layer and the first oxide material layer stacked in sequence in the cell area 103 are also partially removed to form a bit line stack layer structure 250 and Figure 2 The dielectric layer 110 shown (including a silicon oxide layer 112, a silicon nitride layer 114 and a silicon oxide layer 116 stacked in sequence) is not limited to the aforementioned steps.

[0096] For example Figure 6 As shown, a deposition process and an etch-back process are simultaneously performed on the peripheral region 101 and the cell region 103, and a first gate spacer stacking structure 230 and a first bit line spacer stacking structure 260 are formed on the sidewalls of the gate stacking layer structure 220 and the bit line stacking layer structure 250, respectively. The first gate spacer stacking structure 230 and the first bit line spacer stacking structure 260 are respectively arranged around the gate stacking layer structure 220 and the bit line stacking layer structure 250. Then, an insulating material layer 280 is formed on the peripheral region 101 and the cell region 103 of the substrate 100 to cover the entirety, wherein the insulating material layer 280 is formed around the first gate spacer stacking structure 230 and the first bit line spacer stacking structure 260, and substantially has a top surface (not shown) flush with the gate stacking layer structure 220 and the bit line stacking layer structure 250. In one embodiment, the first gate spacer stacking structure 230 and the first bit line spacer stacking structure 260, for example, both include a single-layer or multi-layer structure and the same insulating material, which includes, for example, silicon oxide, silicon oxynitride, silicon nitride or silicon carbonitride, etc., and the insulating material layer 280, for example, includes an insulating material different from the first gate spacer stacking structure 230 and the first bit line spacer stacking structure 260, preferably includes silicon oxide or silicon oxynitride, but is not limited thereto. In another embodiment, the first gate spacer stacking structure and the first bit line spacer stacking structure may also be selected to include a composite layer structure with similar components and materials.

[0097] like Figure 7 As shown, a patterning process is performed by covering with a mask layer (not shown), and an opening 204 and a plurality of openings 202 are simultaneously formed in the peripheral region 101 and the cell region 103, and then the mask layer is completely removed. The opening 204 formed in the peripheral region 101 simultaneously cuts off the gate stack layer structure 220 and the first gate spacer stack structure 230, and forms Figure 1 and Figure 2 The two gate structures 120 shown in FIG. 1 are each formed in the cell region 103. Each opening 202 cuts off the bit line stack layer structure 250 and the first bit line spacer stack structure 260 at the same time, thereby forming a Figure 1 and Figure 2 The plurality of bit line structures 150 shown. It should be noted that each gate structure 120 includes a short side GS1 in the first direction D1 and two long side GS2 in the second direction D2, and each bit line structure 150 includes a first side wall BS1 in the second direction D2 and a second side wall BS2 in the first direction D1. In addition, the first gate spacer stacking structure 230 covers the long side GS2 of the two gate structures 120, and the first bit line spacer stacking structure 260 covers the first side wall BS1 of each bit line structure 150, as shown in FIG. Figure 7 shown.

[0098] like Figure 8 As shown, deposition and etching processes are performed on the peripheral region 101 and the cell region 103 for multiple times, and the second spacer structure 140 and the second bit line spacer structure 170 are formed in the openings 204 and 202, respectively. The second spacer structure 140 fills the opening 204, and the second bit line spacer structure 170 is formed on the sidewalls of each opening 202, and can be seen in a top view (such as Figure 8 ) presents a rectangular frame-shaped structure, but is not limited thereto. In this way, the second spacer structure 140 simultaneously covers the short side edges GS1 of the two gate structures 120 adjacent to each other, and the second bit line spacer structure 170 completely covers the second side walls BS2 of each bit line structure 150. In one embodiment, the second bit line spacer structure 170, for example, includes a first bit line spacer 172 (for example, including silicon nitride, silicon carbonitride) formed on the side walls of each bit line plug 150C, and a second bit line spacer 174 (for example, including silicon nitride, silicon carbonitride), a third bit line spacer 176 (for example, including silicon oxide, silicon oxynitride) and a fourth bit line spacer 178 (for example, including silicon nitride, silicon carbonitride) sequentially formed on the second side wall BS2, and can present the following: Figure 2 The cross-sectional structure shown in FIG. 1 is a schematic diagram of a structure of a second spacer 140 formed simultaneously. Here, the second spacer structure 140 formed simultaneously can selectively include the following by controlling the operating conditions of the aforementioned deposition process and the back etching process: Figure 2 The first gate spacer 142 (for example, including silicon nitride, silicon carbonitride), the second gate spacer 144 (for example, including silicon oxide, silicon oxynitride) and the third gate spacer 146 (for example, including silicon nitride, silicon carbonitride) are sequentially formed on the short side GS1, or include Figure 4 The first gate spacer 142 (eg, including silicon nitride, silicon carbonitride) and the second gate spacer 144 (eg, including silicon oxide, silicon oxynitride) are sequentially formed on the short side GS1, or as shown in FIG. Figure 5 The illustration only includes the first gate spacer 142 (eg, including silicon nitride or silicon carbonitride) formed on the short side GS1 , but the invention is not limited thereto.

[0099] It should be noted that, when the aforementioned back etching process is performed, due to the difference in etching selection, the first gate spacer stack structure 230 originally covering the long side GS2, the first bit line spacer stack structure 260 originally covering the first side wall BS1, and the insulating material layer 280 originally formed around them will also be partially etched, thereby forming the following in the peripheral area 101: Figure 1 and Figure 2The first spacer structure 130 and the insulating layer 180 are shown. The first spacer structure 130 completely covers the long side edges GS2 of the two gate structures 120 and has a first top surface TS1 (eg, Figure 2 As shown), the insulating layer 180 surrounds the gate structure 120 and the first spacer structure 130 and also has a top surface that is lower than the top surface 140t of the second spacer structure 140 but flush with the first top surface TS1 (as shown). Figure 2 shown).

[0100] Subsequently, a deposition process and a planarization process may be continued on the unit region 103 to form a Figure 1 and Figure 2 The first bit line spacer structure 160, and the insulating layer 182 and the insulating layer 184 are shown. The first bit line spacer structure 160 completely covers the first side wall BS1 of each bit line structure 150. The insulating layer 182 is formed between the second side walls BS2 of adjacent bit line structures 150, and the insulating layer 184 is simultaneously formed on the insulating layer 180, and also surrounds the gate structure 120 and the first spacer structure 130. In one embodiment, the insulating layer 182 and the insulating layer 184, for example, both include insulating materials such as silicon oxide and silicon oxynitride, and preferably include the same insulating material, but not limited thereto. In one embodiment, the insulating layer 180, the insulating layer 182, and the insulating layer 184, for example, all include the same insulating material, so that the insulating layer 184 can be formed in an integral manner with the insulating layer 180 formed thereunder, but not limited thereto. In addition, those skilled in the art can easily understand that the method for manufacturing the semiconductor device 10 of the present embodiment may further include forming a plurality of word line structures (not shown) and a plurality of storage node plugs (not shown) in the cell region 103. The word line structures are separated from each other and extend in the second direction D2 perpendicular to the bit line structure 150, and the storage node plugs are respectively arranged between the bit line structures 150 to be electrically connected to the active region 104, receive and transmit the voltage signal of the substrate 100 (such as the source or drain of a transistor element in the substrate 100). Thus, the semiconductor device 10 and the capacitor structure (not shown) subsequently formed thereon can form a dynamic random access memory device together, and the transistor element and the capacitor in the substrate 100 together form the smallest memory cell in the dynamic random access memory array to receive the voltage information from the bit line structure 150 and the word line structure.

[0101] According to the manufacturing method of the semiconductor device 10 of the preferred embodiment of the present application, after the gate stack layer structure 220 and the bit line stack layer structure 250 are simultaneously formed, and the first gate spacer stack structure 230 and the first bit line spacer stack structure 260 are simultaneously formed, an opening 204 that can simultaneously cut off the gate stack layer structure 220 and the first gate spacer stack structure 230 is formed in the peripheral area 101, and an opening 202 that can simultaneously cut off the bit line stack layer structure 250 and the first bit line spacer stack structure 260 is formed in the cell area 103, and then a second spacer structure 140 and a second bit line spacer structure 170 are simultaneously formed in the openings 204 and 202. In this operation, without performing additional steps, the first spacer structure 130 and the second spacer structure 140 with different materials and / or film structures are formed on the short side GS1 and the long side GS2 of the gate structure 120 formed in the peripheral area 101, and the first bit line spacer structure 160 and the second bit line spacer structure 170 with different materials and / or film structures are formed on the first side wall BS1 and the second side wall BS2 of the bit line structure 150 formed in the cell area 103. Thus, by forming the first spacer structure 130 and the second spacer structure 140 on different sides, the gate structure 120 can achieve different insulation effects in different extension directions, and by forming the first bit line spacer structure 160 and the second spacer structure 140 on different side walls, the bit line structure 150 formed together can also achieve different insulation effects in different extension directions. The semiconductor device 10 formed by the manufacturing method of this embodiment can have a more optimized component structure and performance, thereby improving its operating performance.

[0102] A person skilled in the art of the present application should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present application may also have other aspects and is not limited to the above. Other embodiments or variations of the semiconductor device of the present application will be further described below. In order to simplify the description, the following description mainly details the differences between the embodiments, and no longer repeats the same aspects. In addition, the same components in the embodiments of the present application are marked with the same reference numerals to facilitate comparison between the embodiments.

[0103] Please refer to Figures 9 and 10 FIG. 1 is a schematic diagram of a semiconductor device 30 according to a second embodiment of the present application, wherein: Fig. 9 is a schematic top view of a semiconductor device 30, Fig.10The partial three-dimensional schematic diagram and the partial cross-sectional schematic diagram of the semiconductor device 30 are simultaneously presented. The semiconductor device 30 of the present embodiment is substantially the same as the semiconductor device 10 in the aforementioned embodiment, with the main difference being that the second spacer structure 340 only partially passes through the first spacer structure 330 respectively disposed on the long sides GS2 on both sides of the gate structure 120, so that its extension length L3 in the first direction D1 is greater than the extension length L2 of the short side GS1 of the gate structure 120 in the first direction D1, but less than the extension length L2 of the short side GS1 plus the sum of twice the width W1 of the first spacer structure 130 disposed on each long side GS2 of the gate structure 120 in the first direction D1 (L2+2×W1).

[0104] In the present embodiment, the first spacer structure 330 also completely covers the long side edges GS2 of the two gate structures 120, and the second spacer structure 340 is also disposed between the two gate structures 120 and simultaneously covers the short side edges GS1 of the two gate structures 120 adjacent to each other. It should be noted that the first spacer structure 330 covering each long side edge GS2 of the gate structure 120 has an end portion 330e in the first direction D1, and the second spacer structure 340 simultaneously partially covers each end portion 330e of the first spacer structure 330, as shown in FIG. Fig. 9 and Fig.10 That is, the first spacer structures 330 disposed on the long sides GS2 of the two gate structures 120 are in contact with each other, and may be partially disposed below the second spacer structure 340, as shown in FIG. Fig.10 As shown. Moreover, due to the difference in etching selectivity, the first spacer structure 330 may have a first top surface TS1, a second top surface TS2, and a third top surface TS3 with different heights in the vertical direction D3 perpendicular to the substrate 100. The first top surface TS1 is higher than the second top surface TS2 and the third top surface TS3, and is slightly lower than the top surface 340t of the second spacer structure 340 or the top surface 120t of the gate structure 120, while the third top surface TS3 is higher than the second top surface TS2 and lower than the first top surface TS1. Among them, the second top surface TS2 and the third top surface TS3 of the first spacer structure 330 are both arranged between the two gate structures 120, the second top surface TS2 is adjacent to the third top surface TS3, and is located directly below the second spacer structure 340. In this way, the second top surface TS2 can be entirely covered by the second spacer structure 340, the third top surface TS3 is only partially covered by the second spacer structure 340, and the first top surface TS1 is not covered by the second spacer structure 340, as shown in FIG. Fig.10 shown.

[0105] According to the semiconductor device 30 of the second embodiment of the present application, the first spacer structure 330 and the second spacer structure 340 are also provided to effectively isolate the contact between different sides of each gate structure 120 and adjacent components in different directions, so that the gate structure 120 can achieve different insulation effects in different extension directions. Under this arrangement, the semiconductor device 30 can have a more optimized component structure and performance, thereby improving its operating performance.

[0106] Please refer to Figure 11 to Figure 12 FIG. 4 is a schematic diagram of a semiconductor device 40 according to a third embodiment of the present application, wherein: Fig.11 is a schematic top view of a semiconductor device 40, Fig.12 The partial three-dimensional schematic diagram and the partial cross-sectional schematic diagram of the semiconductor device 10 are simultaneously presented. The semiconductor device 40 of the present embodiment is substantially the same as the semiconductor device 10 in the aforementioned embodiment, with the main difference being that the semiconductor device 40 includes a plurality of gate structures 120 arranged in two rows in a first direction D1, so that the gate structures 120 arranged in one row are aligned with the gate structures 120 arranged in another row in a second direction D2, and the short side edges GS1 of the gate structures 120 arranged in one row are arranged opposite to and adjacent to the short side edges GS1 of the gate structures 120 arranged in another row in the second direction D2, as shown in FIG. Fig.11 shown.

[0107] In the present embodiment, the first spacer structure 430 also completely covers the long side GS2 of each gate structure 120, and the second spacer structure 440 is disposed between two rows of gate structures 120 and simultaneously covers the short side GS1 of each gate structure 120. It should be noted that the first spacer structure 430 covering each long side GS2 of the gate structure 120 has an end 430e in the first direction D1, and the second spacer structure 440 of the present embodiment completely covers a portion of the end 430e and partially covers another portion of the end 430e, as shown in FIG. Fig.11 and Fig.12 That is, the second spacer structure 440 only partially passes through the first spacer structure 430 disposed on the long side GS2 on one side of a gate structure 120, crosses the first spacer structure 430 disposed on the long side GS2 on the other side of the same gate structure 120, and extends to the first spacer structure 430 on the long side GS2 on one side of another gate structure 120, so that its extension length L4 in the first direction D1 is at least greater than twice the extension length L2 (2×L2) of the short side GS1 of the gate structure 120 in the first direction D1, as shown in FIG. Fig.11 As shown, but not limited to.

[0108] It should be noted that the first spacer structures 430 on the long sides GS2 of the gate structures 120 aligned with each other in the second direction D2 are also in contact with each other, so that part of the first spacer structure 430 can be disposed below the second spacer structure 440. Fig.12 As shown. Moreover, due to the difference in etching selectivity, the first spacer structure 430 may have a first top surface TS1, a second top surface TS2 and a third top surface TS3 with different heights in the vertical direction D3 perpendicular to the substrate 100. Among them, the heights of the first top surface TS1, the second top surface TS2 and the third top surface TS3 are all lower than the top surface 140t of the second spacer structure 440, the first top surface TS1 is higher than the second top surface TS2 and the third top surface TS3, and the third top surface TS3 is higher than the second top surface TS2 and lower than the first top surface TS1. In detail, the third top surface TS3 and the second top surface TS2 are adjacent to each other and are both located between the two gate structures 120 that are aligned with each other in the second direction D2. The second spacer structure 440 covers the second top surface TS2 as a whole, and partially covers the third top surface TS3, but does not cover the first top surface TS1, as shown in FIG. Fig.12 shown.

[0109] According to the semiconductor device 40 of the second embodiment of the present application, the first spacer structure 430 and the second spacer structure 440 are also provided to effectively isolate the contact between different sides of each gate structure 120 and adjacent components in different directions, so that the gate structure 120 can achieve different insulation effects in different extension directions. Under this arrangement, the semiconductor device 40 can have a more optimized component structure and performance, thereby improving its operating performance.

[0110] In general, the present application integrates the manufacturing processes of components arranged on different regions, and while avoiding the need to add additional operation steps, when forming the bit line spacer structure, simultaneously forms a gate spacer structure with different materials and / or film layer structures on different sides of the gate structure, so that the gate structure can achieve different insulation effects in different extension directions. As a result, the semiconductor device formed by the manufacturing process of the present application can have a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device.

[0111] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; At least two gate structures are arranged on the substrate, the two gate structures respectively include short sides extending in a first direction and long sides extending in a second direction, the short sides of the two gate structures are arranged opposite to each other, and the first direction is perpendicular to the second direction; A first spacer structure covering the long sides of the two gate structures; as well as The second spacer structure covers the short sides of the two gate structures at the same time, wherein an extension length of the second spacer structure in the first direction is greater than an extension length of the short sides of the two gate structures in the first direction.

2. The semiconductor device according to claim 1, wherein: Also includes: A plurality of bit line structures are spaced apart from each other and extend in the first direction and are disposed on the substrate, each of the bit line structures comprising a first sidewall in the second direction and a second sidewall in the first direction; A first bit line spacer structure covering the first sidewall of each bit line structure; as well as The second bit line spacer structure covers the second sidewalls of each bit line structure, wherein the second bit line spacer structure comprises a first bit line spacer, a second bit line spacer and a third bit line spacer which are arranged in sequence.

3. The semiconductor device according to claim 2, characterized in that The material of the second spacer structure is at least equal to a part of the material of the second bit line spacer structure.

4. The semiconductor device according to claim 2, characterized in that The material of the first spacer structure is the same as the material of the first bit line spacer structure.

5. The semiconductor device according to claim 1, wherein: The first spacer structures covering the long sides of the two gate structures are spaced apart from each other and respectively have ends in the first direction, and the second spacer structures cover the ends of the first spacer structures.

6. The semiconductor device according to claim 1, wherein: The first spacer structure covering the long sides of the two gate structures has a first top surface and a second top surface with different heights, and the second spacer structure covers the second top surface.

7. The semiconductor device according to claim 1, wherein: The first spacer structure covering the long sides of the two gate structures has a first top surface and a second top surface with different heights; The first top surface is higher than the second top surface and lower than a top surface of the second spacer structure.

8. The semiconductor device according to claim 1, wherein: The extension length of the second spacer structure is greater than the sum of the extension lengths of the short sides of the two gate structures and twice the width of the first spacer structure in the first direction.

9. The semiconductor device according to claim 7, characterized in that The first spacer structure covering the long sides of the two gate structures further has a third top surface having a height different from that of the first top surface and the second top surface.

10. The semiconductor device according to claim 9, characterized in that The third top surface is higher than the second top surface and lower than the first top surface.

11. The semiconductor device according to claim 9, characterized in that The first spacer structure partially covers an end portion of the second spacer structure in the second direction.

12. The semiconductor device according to claim 1, wherein: It also includes a plurality of the gate structures arranged in two rows, and the short sides of two opposite gate structures are arranged opposite to each other, and the second spacer structure covers the short sides of each gate structure at the same time.

13. The semiconductor device according to claim 12, characterized in that The first spacer structures covering the long sides of at least two of the gate structures are spaced apart from each other and respectively have ends in the first direction, the second spacer structure covers the ends of the first spacer structure, and the first spacer structure covering the long sides of the other two gate structures has a first top surface and a second top surface with different heights, the first top surface is lower than the top surface of the second spacer structure, and the second spacer structure covers the second top surface.

14. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; At least two gate structures are formed on the substrate, the two gate structures respectively comprising short sides extending in a first direction and long sides extending in a second direction, the short sides of the two gate structures are arranged opposite to each other, and the first direction is perpendicular to the second direction; forming a first spacer structure on the long sides of the two gate structures; as well as A second spacer structure is formed on the short sides of the two gate structures, wherein an extension length of the second spacer structure in the first direction is greater than an extension length of the short sides of the two gate structures in the first direction.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that: Forming the gate structure further includes: forming a gate stack structure on the substrate; forming a first gate spacer stack structure surrounding the gate stack structure; forming an insulating material layer surrounding the first gate spacer stack structure and the gate stack layer structure; A patterning process is performed to cut off the gate stack structure to form the two gate structures.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: When performing the patterning process, the first gate spacer stack structure is cut off to form the first spacer structure.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that: When performing the patterning process, the first gate spacer stack structure is partially cut off to form the first spacer structure.

18. The method for manufacturing a semiconductor device according to claim 15, characterized in that: Also includes: forming a bit line stacking layer structure on the substrate; When forming the first gate spacer stack structure, a first bit line spacer stack structure is simultaneously formed to surround the bit line stack layer structure; as well as When the patterning process is performed, the bit line stack layer structure is patterned simultaneously to form a bit line structure, and the bit line structures are spaced apart from each other and extend in the first direction.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that: After performing the patterning process, the method further comprises: When forming the second spacer structure, a second bit line spacer structure is synchronously formed between the bit line structures and is located on the second sidewall of each bit line structure in the first direction.

20. The method for manufacturing a semiconductor device according to claim 18, wherein: Also includes: A plurality of the gate structures are formed, the short sides of any two of the gate structures are arranged opposite to each other, and the second spacer structure covers the short sides of each of the gate structures at the same time.

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