Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate which comprises a pixel region and a logic region surrounding the pixel region; forming a sacrificial layer on the substrate by adopting a chemical vapor deposition process; forming a first photoresist layer on the sacrificial layer; exposing and developing the first photoresist layer until the surface of the sacrificial layer is exposed, and forming the first photoresist layer with a pixel region pattern; and taking the first photoresist layer with the pixel region pattern as a mask, and performing ion implantation on the substrate to form a photosensitive region. The chemical vapor deposition process is adopted, the sacrificial layer is formed on the substrate, the flatness of the surface of the substrate is guaranteed, gathering of static charges on the surface of the substrate and damage to the surface of a silicon wafer can be reduced as much as possible, a high-temperature environment is not needed in the preparation process, the preparation cost is reduced, and the performance of a semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] CMOS Image Sensor (CIS) is a semiconductor device used to capture images, usually composed of pixel area and logic area. The design and process of pixel area are key to the performance of CIS products. The complete pixel area needs multiple injections to form photodiodes, isolation areas, well areas, source and drain electrodes, etc. CMOS image sensors have the advantages of high integration, low power consumption and low production cost. These features enable CMOS sensors to integrate the entire image system on a single chip, thereby reducing volume and power consumption.

[0003] However, the substrate surface of current CMOS image sensors is easily damaged. Summary of the invention

[0004] The technical problem solved by the present invention is how to improve the substrate damage problem in a CMOS image sensor.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a pixel area and a logic area surrounding the pixel area; using a chemical vapor deposition process to form a sacrificial layer on the substrate; forming a first photoresist layer on the sacrificial layer; exposing and developing the first photoresist layer to expose the surface of the sacrificial layer to form a first photoresist layer having a pixel area pattern; using the first photoresist layer having the pixel area pattern as a mask, performing ion implantation on the substrate to form a photosensitive area.

[0006] Optionally, the chemical vapor deposition process includes low pressure chemical vapor deposition, subatmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and atomic layer deposition.

[0007] Optionally, the process parameters of the low pressure chemical vapor deposition method include: a reaction pressure range of 13.3 Pa to 133 Pa, a reaction temperature range of 600° C. to 1000° C., and a reaction gas including SiH 4 and N 2 O, the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0008] Optionally, the process parameters of the subatmospheric pressure chemical vapor deposition method include: a reaction pressure range of 0.9 atm to 1 atm, a reaction temperature range of 400° C. to 450° C., and a reaction gas including SiH 4 and N2 O, the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0009] Optionally, the process parameters of the plasma enhanced chemical vapor deposition include: a reaction temperature range of 200° C. to 400° C., a reaction gas including SiH 4 and N 2 O, the gas pressure range is 1 Torr to 10 Torr; the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0010] Optionally, the process parameters of the atomic layer deposition include: a reaction temperature range of 200° C. to 400° C., a reaction gas including N 2 or Ar, the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0011] Optionally, the thickness of the substrate ranges from 500 microns to 1000 microns, and the thickness of the sacrificial layer ranges from 20 angstroms to 2000 angstroms.

[0012] Optionally, the process parameters for ion implantation into the substrate include: an implantation concentration range of 1E12 ions / cm 2 To 1E16 ions / cm 2 The implanted ions are arsenic ions or phosphorus ions.

[0013] Optionally, after the step of forming the photosensitive area, the method further includes: removing the first photoresist layer having the pixel area pattern and the sacrificial layer until the substrate surface and the photosensitive area surface are exposed.

[0014] Optionally, after removing the first photoresist layer having the pixel area pattern and the sacrificial layer to expose the substrate surface and the photosensitive area surface, the method further includes: forming an oxide layer on the substrate surface and the photosensitive area surface using a thermal oxidation process; and forming a nitride layer on the oxide layer.

[0015] Optionally, the process parameters of the thermal oxidation treatment process are an oxidation temperature range of 500° C. to 2000° C., an oxidation time range of 10 seconds to 24 hours, an oxidation atmosphere of O 2 , H 2 O or HCl.

[0016] Optionally, the thickness of the oxide layer ranges from 20 angstroms to 2000 angstroms, and the thickness of the nitride layer ranges from 50 angstroms to 3000 angstroms.

[0017] Optionally, after the step of forming the nitride layer, it also includes: forming a second photoresist layer on the nitride layer; exposing and developing the second photoresist layer until the surface of the substrate is exposed to form a second photoresist layer having an isolation area pattern; using the second photoresist layer having the isolation area pattern as a mask, etching the substrate to form an isolation trench; filling the isolation trench with isolation material to form an isolation area.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The technical solution of the present invention forms a sacrificial layer on the substrate through a chemical vapor deposition process, thereby ensuring the flatness of the substrate surface and reducing the influence of electrostatic breakdown caused by the accumulation of static charge at the edge of the first photoresist layer during the exposure and development of the first photoresist layer, thereby minimizing the accumulation of static charge on the substrate surface and damage to the silicon wafer surface, and no high-temperature environment is required during the preparation process, thereby reducing the preparation cost and improving the performance of the semiconductor device; in addition, the present invention forms a sacrificial layer on the substrate through a chemical vapor deposition process, and realizes direct deposition on the substrate surface to form the sacrificial layer. Compared with the solution of oxidizing the substrate surface through a thermal oxidation treatment process in the prior art to form the sacrificial layer, the present invention does not need to consume the substrate surface material, thereby ensuring the integrity of the substrate, reducing the preparation cost and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0021] Figure 2 It is a schematic diagram of defect scanning of a semiconductor structure;

[0022] Figures 3 to 9 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0024] At present, the CMOS image sensor advances the step of partially high-energy ion implantation to form the photodiode photosensitive area before the AA loop (etching process of shallow trench isolation structure). For details, please refer to Figure 1 , Figure 1The present invention is a schematic diagram of a semiconductor structure formation process, comprising: providing a substrate 100, wherein the substrate 100 comprises a pixel region II and a logic region I surrounding the pixel region II; forming a sacrificial layer 101 on the substrate 100 by a thermal oxidation process; exposing and developing a first photoresist layer (not shown in the figure) to expose the surface of the sacrificial layer 101 to form a first photoresist layer having a pixel region II pattern; and performing ion implantation on the substrate 100 to form a photosensitive region using the first photoresist layer having the pixel region II pattern as a mask.

[0025] In this embodiment, the thickness of the first photoresist layer is greater than 1 micron, and the clear ratio of exposure and development is greater than 50%.

[0026] Please refer to Figure 2 , Figure 2 yes Figure 1 Scanning defect map, Figure 2 The middle (a) figure is the scan defect map of the entire wafer. Figure 2 The red dots in (a) represent defects. Figure 2 Figure (b) is a scanned defect image of a chip in the wafer. It can be seen from the figure that after photolithography development, the first photoresist layer needs a higher rotation speed or a longer time to be flushed and cleaned. The higher the rotation speed or the longer the time, the more electrostatic charge accumulates at the edge of the first photoresist layer, which in turn causes more electrostatic charge to accumulate on the surface of the substrate, thereby causing damage to the surface of the substrate.

[0027] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, which adopts a chemical vapor deposition process to deposit a sacrificial layer on the substrate, so as to avoid damage to the substrate surface and reduce the accumulation of static charge on the substrate, thereby minimizing the damage to the surface of the silicon wafer, and no high-temperature environment is required during the preparation process, thereby reducing the preparation cost and improving the performance of the semiconductor device; in addition, the present invention adopts a chemical vapor deposition process to deposit the sacrificial layer on the substrate, and can directly deposit the sacrificial layer on the surface of the substrate. Compared with the solution of oxidizing the substrate surface to form a sacrificial layer through a thermal oxidation treatment process in the prior art, the present invention does not need to consume the substrate surface material, thereby ensuring the integrity of the substrate, reducing the preparation cost and improving the performance of the semiconductor device.

[0028] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Please refer to Figure 3 , providing a substrate 200, wherein the substrate 200 includes a pixel region II and a logic region I surrounding the pixel region II.

[0030] In some embodiments of the present invention, the substrate 200 is made of silicon.

[0031] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0032] In some embodiments of the present invention, the thickness of the substrate 200 is in a range of 500 micrometers to 1000 micrometers.

[0033] In this embodiment, since the subsequent method of forming the sacrificial layer 201 on the substrate 200 is a chemical vapor deposition process, the thickness of the substrate 200 will not be consumed, thereby ensuring the integrity of the substrate 200.

[0034] In some embodiments of the present invention, the pixel region II is used to form a photodiode to convert optical signals into electrical signals. Specifically, when light enters the pixel region II through the microlens and the color filter, the photodiode converts photons into electrons, and the electrons accumulate in the photodiode.

[0035] In some embodiments of the present invention, the logic area I is used to form a signal processing circuit to realize functions such as signal processing, control and data transmission. Specifically, it is used to process analog signals from the pixel array and convert them into digital signals for subsequent processing and transmission.

[0036] Please refer to Figure 4 , a sacrificial layer 201 is formed on the substrate 200 by using a chemical vapor deposition process.

[0037] In some embodiments of the present invention, the chemical vapor deposition process includes low pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and atomic layer deposition.

[0038] In some embodiments of the present invention, the process parameters of the low pressure chemical vapor deposition method include: a reaction pressure range of 13.3 Pa to 133 Pa, a reaction temperature range of 600° C. to 1000° C., and a reaction gas including SiH 4 and N 2 O, the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0039] In the above scheme, the low-pressure chemical vapor deposition method is a chemical vapor deposition technology performed in a low-pressure environment. The mean free path of gas molecules is long, so that the reaction gas can cover the substrate surface more evenly, forming a dense and uniform film, and can achieve uniform deposition on a large-area substrate. In addition, the process parameters of the low-pressure chemical vapor deposition method are easy to control and repeat, the deposition process is stable, and the film has good repeatability, which is suitable for large-scale production.

[0040] In some embodiments of the present invention, the process parameters of the subatmospheric pressure chemical vapor deposition method include: a reaction pressure range of 0.9 atm to 1 atm, a reaction temperature range of 400° C. to 450° C., and a reaction gas including SiH 4 and N 2 O, the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0041] In the above scheme, due to the fast deposition rate of subatmospheric pressure chemical vapor deposition, thicker films can be deposited in a shorter time, which improves production efficiency and is suitable for applications with high requirements for deposition rate, such as large-area coating and rapid mass production.

[0042] In some embodiments of the present invention, the process parameters of the plasma enhanced chemical vapor deposition include: a reaction temperature range of 200° C. to 400° C., a reaction gas including SiH 4 and N 2 O, the gas pressure range is 1 Torr to 10 Torr; the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0043] In the above scheme, plasma enhanced chemical vapor deposition can deposit thin films at lower temperatures. Low temperature deposition can avoid damage to substrate materials or devices caused by high temperatures, and high-energy particles in plasma enhanced chemical vapor deposition can promote chemical reactions to form a denser thin film structure.

[0044] In some embodiments of the present invention, the process parameters of the atomic layer deposition include: a reaction temperature range of 200° C. to 400° C., a reaction gas including N 2 or Ar, the deposition rate is 2000 angstroms per minute to 3000 angstroms per minute, and the deposition time is 0.5 seconds to 1 minute.

[0045] In the above schemes, atomic layer deposition is based on a self-limiting reaction mechanism. Each deposition cycle usually deposits one atomic layer. By controlling the number of deposition cycles, the thickness of the film can be precisely controlled, and the accuracy can reach the sub-nanometer level. The film formed by atomic layer deposition usually has high density and low porosity, and the film has high mechanical strength and chemical stability.

[0046] In a specific embodiment, the thickness of the sacrificial layer 201 ranges from 20 angstroms to 2000 angstroms.

[0047] In some embodiments of the present invention, the material of the sacrificial layer 201 includes: one or more of silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0048] In some embodiments of the present invention, the sacrificial layer 201 is used to protect the surface of the substrate 200 from being contaminated by impurities in the environment, to prevent impurities from entering the surface of the substrate 200 and causing device performance degradation or failure, thereby improving device performance; and in the subsequent ion implantation process, high-energy ions bombarding the surface of the substrate 200 may cause physical damage, such as surface roughening or lattice damage. The sacrificial layer 201 can serve as a buffer layer to absorb part of the ion energy and reduce direct damage to the surface of the substrate 200.

[0049] In other embodiments of the present invention, the sacrificial layer 201 is also used to control the distribution of dopants after ion implantation. Specifically, the range and concentration distribution of dopants can be adjusted by controlling the thickness and properties of the sacrificial layer 201. For example, increasing the thickness of the sacrificial layer 201 can increase the scattering of ions and reduce the range of ions in the silicon wafer, thereby changing the depth distribution of dopants.

[0050] In the above scheme, a chemical vapor deposition process is used to form a sacrificial layer 201 on the substrate 200, thereby ensuring the flatness of the surface of the substrate 200 and reducing the influence of electrostatic breakdown caused by the accumulation of static charge at the edge of the first photoresist layer 202 during the exposure and development of the first photoresist layer 202, thereby minimizing the accumulation of static charge on the surface of the substrate 200 and the damage to the surface of the silicon wafer. In addition, no high-temperature environment is required during the preparation process, thereby reducing the preparation cost and improving the performance of the semiconductor device. In addition, the present invention forms a sacrificial layer 201 on the substrate 200 through a chemical vapor deposition process, and realizes direct deposition on the surface of the substrate 200 to form the sacrificial layer 201. Compared with the scheme in the prior art of oxidizing the surface of the substrate 200 through a thermal oxidation treatment process to form the sacrificial layer 201, the present invention does not need to consume the surface material of the substrate 200, thereby ensuring the integrity of the substrate 200, reducing the preparation cost and improving the performance of the semiconductor device.

[0051] Please refer to Figure 5 , forming a first photoresist layer 202 on the sacrificial layer 201; exposing and developing the first photoresist layer 202 until the surface of the sacrificial layer 201 is exposed, thereby forming the first photoresist layer 202 having a pixel region II pattern.

[0052] In some embodiments of the present invention, the first photoresist layer 202 having the pixel region II pattern exposes a portion of the surface of the pixel region II.

[0053] In other embodiments, the first photoresist layer is exposed and developed to achieve exposure of the surface of different positions of the pixel region II, and subsequently a plurality of photosensitive regions may be implanted in the pixel region II.

[0054] In some embodiments of the present invention, the thickness of the first photoresist layer 202 is greater than 1 micrometer.

[0055] Please refer to Figure 6 , using the first photoresist layer 202 having the pixel region II pattern as a mask, ion implantation is performed on the substrate 200 to form a photosensitive region 203 .

[0056] In some embodiments of the present invention, the process parameters for ion implantation into the substrate 200 include: an implantation concentration range of 1E12 ions / cm 2 To 1E16 ions / cm 2 The implanted ions are arsenic ions or phosphorus ions.

[0057] In some embodiments of the present invention, after the step of forming the photosensitive area 203 , the step further includes: removing the first photoresist layer 202 having the pixel area II pattern and the sacrificial layer 201 to expose the surface of the substrate 200 and the surface of the photosensitive area 203 .

[0058] In other embodiments, after the step of forming the photosensitive area, the method further includes: annealing the substrate.

[0059] Since lattice damage may occur on the surface of the substrate 200 during the ion implantation process, the substrate 200 may be repaired by an annealing process. During the annealing process, the dopant may be activated to form a stable bonding structure with the silicon atoms in the substrate 200 .

[0060] In some embodiments of the present invention, the steps of forming the sacrificial layer 201 and ion implantation are performed before the AA loop (etching process of the isolation region 208 ).

[0061] In other embodiments, the steps of forming the sacrificial layer and ion implantation are performed after the AA loop (etching process of the isolation region).

[0062] Please refer to Figure 7 , a thermal oxidation process is used to form an oxide layer 204 on the surface of the substrate 200 and the surface of the photosensitive area 203; and a nitride layer 205 is formed on the oxide layer 204.

[0063] In some embodiments of the present invention, the process parameters of the thermal oxidation process are an oxidation temperature range of 500° C. to 2000° C., an oxidation time range of 10 seconds to 24 hours, an oxidation atmosphere of O 2 , H 2 O or HCl.

[0064] In some embodiments of the present invention, the thickness of the oxide layer 204 ranges from 20 angstroms to 2000 angstroms, and the thickness of the nitride layer 205 ranges from 50 angstroms to 3000 angstroms.

[0065] In some embodiments of the present invention, the material of the oxide layer 204 includes: one or more of silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide; the material of the nitride layer 205 includes: boron nitride or aluminum nitride.

[0066] In the above solution, the oxide layer 204 can be used as a stress buffer layer to reduce the stress of the substrate 200 caused by thermal mismatch or lattice mismatch, thereby preventing device failure.

[0067] Please refer to Figure 8 , forming a second photoresist layer 206 on the nitride layer 205; exposing and developing the second photoresist layer 206 until the surface of the substrate 200 is exposed, forming a second photoresist layer 206 having an isolation region 208 pattern; using the second photoresist layer 206 having the isolation region 208 pattern as a mask, etching the substrate 200 to form an isolation groove 207.

[0068] In some embodiments of the present invention, a dry etching process is used to etch the substrate 200 to form an isolation groove 207, and the process parameters of the dry etching process are: the chamber pressure is 5 mT to 15 mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

[0069] The isolation trench is used to accommodate an isolation region to be formed subsequently.

[0070] Please refer to Fig. 9 , filling the isolation trench 207 with isolation material to form an isolation region 208 .

[0071] In some embodiments of the present invention, the isolation trench 207 is filled by a chemical vapor deposition process.

[0072] In some embodiments of the present invention, the material of the isolation region 208 is silicon oxide.

[0073] In other embodiments, the material of the isolation region is silicon nitride.

[0074] In some embodiments of the present invention, the isolation region 208 is used to avoid electrical crosstalk between adjacent devices.

[0075] In some embodiments of the present invention, the method further includes: removing the isolation region 208 higher than the surface of the substrate 200 through a planarization process.

[0076] In some embodiments of the present invention, the planarization process adopts a chemical mechanical polishing process.

[0077] In some embodiments of the present invention, by adjusting the process parameters of chemical mechanical polishing, it is possible to ensure that the isolation region 208 above the surface of the substrate 200 is removed during the polishing process and stops at a surface flush with the substrate 200 .

[0078] In other embodiments, the thickness of the isolation region above the surface of the substrate is 0 angstroms to 80 angstroms.

[0079] In some embodiments of the present invention, the method further includes: removing the second photoresist layer 206 .

[0080] In some embodiments of the present invention, the present invention is used to form a CMOS image sensor device.

[0081] Of course, the present invention is not limited to this, and other devices are within the protection scope of the present invention.

[0082] In summary, the technical solution of the present invention forms a sacrificial layer on the substrate through a chemical vapor deposition process, thereby ensuring the flatness of the substrate surface and reducing the influence of electrostatic breakdown caused by the accumulation of static charge at the edge of the first photoresist layer during the exposure and development of the first photoresist layer, thereby minimizing the accumulation of static charge on the substrate surface and damage to the silicon wafer surface, and no high-temperature environment is required during the preparation process, thereby reducing the preparation cost and improving the performance of the semiconductor device; in addition, the present invention forms a sacrificial layer on the substrate through a chemical vapor deposition process, and realizes direct deposition on the substrate surface to form the sacrificial layer. Compared with the solution in the prior art of oxidizing the substrate surface to form a sacrificial layer through a thermal oxidation treatment process, the present invention does not need to consume the substrate surface material, thereby ensuring the integrity of the substrate, reducing the preparation cost and improving the performance of the semiconductor device.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a pixel region and a logic region surrounding the pixel region; forming a sacrificial layer on the substrate by using a chemical vapor deposition process; forming a first photoresist layer on the sacrificial layer; Expose and develop the first photoresist layer until the surface of the sacrificial layer is exposed, so as to form a first photoresist layer having a pixel area pattern; Using the first photoresist layer with the pixel area pattern as a mask, ion implantation is performed on the substrate to form a photosensitive area.

2. The method for forming a semiconductor structure according to claim 1, wherein: The chemical vapor deposition process includes low pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and atomic layer deposition.

3. The method for forming a semiconductor structure according to claim 2, wherein: The process parameters of the low pressure chemical vapor deposition method include: a reaction pressure range of 13.3 Pa to 133 Pa, a reaction temperature range of 600°C to 1000°C, reaction gases including SiH4 and N2O, a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute, and a deposition time of 0.5 seconds to 1 minute.

4. The method for forming a semiconductor structure according to claim 2, wherein: The process parameters of the subatmospheric pressure chemical vapor deposition method include: a reaction pressure range of 0.9 atm to 1 atm, a reaction temperature range of 400°C to 450°C, reaction gases including SiH4 and N2O, a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute, and a deposition time of 0.5 seconds to 1 minute.

5. The method for forming a semiconductor structure according to claim 2, wherein: The process parameters of the plasma enhanced chemical vapor deposition include: a reaction temperature range of 200°C to 400°C, reaction gases include SiH4 and N2O, and a gas pressure range of 1Torr to 10Torr; a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute, and a deposition time of 0.5 seconds to 1 minute.

6. The method for forming a semiconductor structure according to claim 2, wherein: The process parameters of the atomic layer deposition include: a reaction temperature range of 200°C to 400°C, a reaction gas including N2 or Ar, a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute, and a deposition time of 0.5 seconds to 1 minute.

7. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the substrate ranges from 500 micrometers to 1000 micrometers, and the thickness of the sacrificial layer ranges from 20 angstroms to 2000 angstroms.

8. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters for ion implantation into the substrate include: an implantation concentration range of 1E12 ions / cm 2 To 1E16 ions / cm 2 The implanted ions are arsenic ions or phosphorus ions.

9. The method for forming a semiconductor structure according to claim 1, wherein: After the step of forming the photosensitive area, the method further comprises: The first photoresist layer having the pixel area pattern and the sacrificial layer are removed until the substrate surface and the photosensitive area surface are exposed.

10. The method for forming a semiconductor structure according to claim 9, wherein: After removing the first photoresist layer having the pixel area pattern and the sacrificial layer until the substrate surface and the photosensitive area surface are exposed, the method further includes: Using a thermal oxidation process to form an oxide layer on the surface of the substrate and the surface of the photosensitive area; A nitride layer is formed on the oxide layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process parameters of the thermal oxidation treatment process are: an oxidation temperature ranging from 500° C. to 2000° C., an oxidation time ranging from 10 seconds to 24 hours, and an oxidation atmosphere of O2, H2O or HCl.

12. The method for forming a semiconductor structure according to claim 10, wherein: The thickness of the oxide layer ranges from 20 angstroms to 2000 angstroms, and the thickness of the nitride layer ranges from 50 angstroms to 3000 angstroms.

13. The method for forming a semiconductor structure according to claim 10, wherein: After the step of forming the nitride layer, the method further comprises: forming a second photoresist layer on the nitride layer; Expose and develop the second photoresist layer until the surface of the substrate is exposed to form a second photoresist layer having an isolation area pattern; Using the second photoresist layer having the isolation region pattern as a mask, etching the substrate to form an isolation trench; An isolation material is filled into the isolation trench to form an isolation region.

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