Packaging structure of avalanche photodiode

Abstract

The invention discloses a packaging structure of an avalanche photodiode, which comprises an APD chip, an intermediary plate unit, a TIA chip and a packaging substrate, and is characterized in that the intermediary plate unit and the TIA chip are electrically connected with the packaging substrate and are located in the same plane; and two electrodes of the APD chip are electrically connected with the intermediate plate unit and the TIA chip respectively. The advantages are that the interposer provides physical support and optional optical coupling function for the APD chip on one hand, provides external power supply for the APD chip on the other hand, and can integrate elements such as a capacitor and a resistor on the other hand. Compared with a traditional gold wire bonding scheme, the scheme has the advantages that the internal electric interconnection length of the optical receiver is remarkably reduced, and the optical detection sensitivity can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the fields of high-speed optical communication, optical chip technology, and in particular to the fields of photoelectric detector technology and advanced packaging technology, and specifically to a packaging structure of an avalanche photodiode. Background Art

[0002] The current optical network has an increasing demand for optical modules. The industry's 200Gbps / lane optical modules have been realized and gradually deployed on a large scale. In the future, optical modules are expected to exceed 400Gbps / lane. The increase in single-channel rate has put forward more stringent requirements for the packaging of optical modules, and the impact of signal integrity on the transmission performance of optoelectronic signals has become increasingly important.

[0003] In order to reduce the RF loss in the module packaging, industry manufacturers are working hard to reduce the length of the optoelectronic interconnection inside the optical module. At the optical signal receiving end, in the traditional low-speed (10G, 25G) optical module packaging, the interconnection between the photodiode PD and the transimpedance amplifier TIA is completed by gold wire bonding, which is low-cost and easy to implement; when the single-channel rate exceeds 200Gbps / lane, the interconnection between the photodiode PD and the transimpedance amplifier TIA is required to be completed by flip-chip, in order to reduce the length of the electrical interconnection, improve the signal transmission quality, and obtain higher optical receiving sensitivity.

[0004] Currently, commercial photodiodes are divided into PIN-PD (PIN photodiode) and APD (avalanche photodiode). Since the driving voltage required by PIN-PD is usually less than 3V, the interconnection between PIN-PD and TIA can be directly realized through Flip-chip, and TIA provides the driving voltage of PIN-PD. Compared with PIN-PD, APD can provide 5-10dB of optical gain, which effectively improves the sensitivity of receiving signals; however, APD requires a higher driving voltage, usually between 20-30V; the cost of directly driving APD through TIA is very high, so the current method commonly used in the industry is to set up an additional electrical pin in the package interface to power APD. This packaging solution increases the length of gold wire bonding, reduces signal integrity during high-speed transmission, and leads to reduced receiving sensitivity. Summary of the invention

[0005] The technical problem to be solved by the present invention is that the external power supply of the APD chip affects the signal transmission quality.

[0006] In order to solve the above technical problems, the present invention proposes a packaging structure of an avalanche photodiode, which includes an intermediate board. The APD chip is flip-chipped to the TIA and the intermediate board at the same time. The intermediate board, on the one hand, realizes the physical support of the APD chip, and on the other hand, provides electrical signal transmission for the APD chip and can integrate components such as capacitors and resistors, thereby reducing the overall electrical interconnection length and effectively improving signal integrity.

[0007] The specific technical solutions adopted are as follows: A packaging structure of an avalanche photodiode includes an APD chip intermediate board unit, a TIA chip and a packaging substrate. The intermediate board unit and the TIA chip are both electrically connected to the packaging substrate, and the intermediate board unit and the TIA chip are in the same plane; two electrodes of the APD chip are electrically connected to the intermediate board unit and the TIA chip respectively.

[0008] In a further preferred embodiment of the technical solution of the present invention, the intermediate board unit includes an intermediate board and a thin film circuit integrated on the intermediate board, and the electrodes in the APD chip are electrically connected to the thin film circuit to provide a bias voltage for the APD chip.

[0009] In a further embodiment of the technical solution of the present invention, the thin film circuit includes an electrical connection component and a capacitance component, wherein the electrical connection component connects the N electrode in the APD chip, the capacitance component and the external packaging pin; the capacitance component provides a filtering function for the electrical signal of the external power supply to reduce the noise source.

[0010] In a further preferred embodiment of the technical solution of the present invention, the intermediate board unit further includes an optical coupling unit, which is integrated on the intermediate board. The optical coupling unit is used to connect an external optical fiber, improve the optical fiber coupling efficiency of the APD chip, and reduce the difficulty of optical fiber assembly. When the APD chip is a surface-incident type, such as Figure 2 (a) and (b), there is no need for an optical coupling unit; when the APD chip is a side-illuminated type, such as Figure 2 (c) and (d), an optical coupling unit is required.

[0011] In a further preferred embodiment of the technical solution of the present invention, the interposer is made of silicon, glass or other optoelectronic packaging materials. The advantage of various materials is that they are convenient for use in higher density optoelectronic packaging, such as CPO (co-packaged optics).

[0012] In a further preferred embodiment of the technical solution of the present invention, a V-groove is formed on the intermediate board. The intermediate board can selectively provide an optical auxiliary coupling function for the waveguide APD chip, for example, a V-groove is formed on the intermediate board to provide physical support and high-precision alignment for optical coupling between the single-mode optical fiber and the APD chip.

[0013] In a further preferred embodiment of the technical solution of the present invention, the packaging substrate is made of PCB, silicon, glass or other optoelectronic packaging materials.

[0014] In a further preferred embodiment of the technical solution of the present invention, the APD chip is an APD chip with a surface illumination structure, and the APD chip with a surface illumination structure comprises a P electrode, an N electrode and a photosensitive area, and the P electrode and the N electrode are electrically connected to the thin film circuit (201) and the TIA chip respectively.

[0015] In a further embodiment of the technical solution of the present invention, the APD chip is an APD chip with a side-illuminated structure, and the APD chip with a side-illuminated structure includes a P electrode, an N electrode, a photosensitive area, an optical waveguide and an edge coupler, and the P electrode and the N electrode are electrically connected to the thin-film circuit and the TIA chip respectively.

[0016] In a further preferred embodiment of the technical solution of the present invention, the electrodes of the APD chip are coplanar electrodes or skew electrodes. The coplanar electrodes are bumped through TSV, and any one of the skew electrodes is bumped through TSV.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. The packaging structure of the avalanche photodiode of the present invention, the interposer provides physical support and optional optical coupling function for the APD chip on the one hand, and provides external power supply for the APD chip and can integrate components such as capacitors and resistors on the other hand. Compared with the traditional gold wire bonding solution, this solution significantly reduces the internal electrical interconnection length of the optical receiver and can effectively increase the light detection sensitivity.

[0018] 2. The packaging structure of the avalanche photodiode of the present invention can flip-chip the APD chip to the TIA chip and the interposer at the same time. This solution is compatible with the existing photodiode technology and various electrode layout methods in the industry, and can significantly reduce the electrical interconnection length between the APD chip and the TIA chip.

[0019] 3. The packaging structure of the avalanche photodiode of the present invention allows the intermediate board to freely arrange a variety of electrical connection branches, and can provide additional planar electrical connection paths for electrical chips such as TIA chips, replacing the traditional gold wire bonding method and reducing the overall electrical interconnection length of the optical receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of the packaging structure of the avalanche photodiode of this embodiment; Figure 2 Schematic diagram of the cross section of the avalanche photodiode APD chip, (a) single-channel surface-incident APD chip, (b) four-channel surface-incident APD chip, (c) single-channel waveguide APD chip, (d) four-channel waveguide APD chip; Figure 3Schematic diagram of electrode distribution of avalanche photodiode APD chip; (a) Coplanar electrodes, P electrode and N electrode are in the same plane; (b) Non-planar electrodes, P electrode and N electrode are in different planes; (c) Coplanar electrodes, and both P electrode and N electrode are bumped through TSV; (d) Non-planar electrodes, and either P electrode or N electrode is bumped through TSV; Figure 4 Schematic diagram of the packaging structure of the avalanche photodiode APD optical chip including the interposer in this embodiment; (a) the P electrode and the N electrode of the APD chip are interconnected with the TIA unit 30 and the interposer unit 20 through bumps, (b) the P electrode and the N electrode of the APD chip are interconnected with the TIA unit 30 and the interposer unit 20 through a gold-tin alloy method; Figure 5 It is a schematic diagram of the surface-incident APD chip package with an interposer; Figure 6 It is a schematic diagram of the waveguide APD chip package with an interposer; Figure 7 Schematic diagram of the TO-can package of the avalanche photodiode; (a) traditional package structure, (b) package structure with an interposer; Among them, 10-APD chip, 20-intermediate board unit, 201-thin film circuit, 2011-electrical connection component, 2012-capacitive resistance component, 202-optical coupling unit, 203-intermediate board, 30-TIA chip, 40-packaging substrate. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the following Figure 1-Figure 7 The present invention is further described in detail with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in each embodiment of the present invention described below can be combined with each other as long as they do not conflict with each other. Example 1

[0022] like Figure 1 As shown, this embodiment is a packaging structure of an avalanche photodiode, which mainly includes: an APD chip 10, an intermediate board unit 20, a TIA chip 30 and a packaging substrate 40; wherein the intermediate board unit 20 includes an intermediate board 203, a thin film circuit 201 and an optical coupling unit 202, and the thin film circuit 201 includes an electrical connection component 2011 and a capacitive resistance component 2012.

[0023] In this embodiment, two electrodes of the APD chip 10 are electrically connected to the thin film circuit 201 in the interposer unit 20 and the TIA chip 30. The interposer unit 20 and the TIA chip 30 are in the same plane and are electrically connected to the package substrate 40 by gold wire bonding or bump welding.

[0024] The thin film circuit 201 in the interposer unit 20 is integrated on an interposer 203 made of silicon, glass or other optoelectronic packaging materials. The function of the thin film circuit 201 is to provide a bias voltage for the APD chip 10 .

[0025] The function of the electrical connection component 2011 is to connect the N electrode of the APD chip 10, the capacitance component 2012 and the external packaging pin. The electrical connection component 2011 is implemented by metallization wiring on the surface or inside of the intermediate board 203, and the metal type is not limited.

[0026] The function of the capacitive resistor component 2012 is to provide filtering function for the electrical signal of the external power supply and reduce the noise source.

[0027] The optical coupling unit 202 in the intermediate board unit 20 is integrated on the intermediate board 203 . The optical coupling unit 202 is used to connect to an external optical fiber, thereby improving the optical fiber coupling efficiency of the APD chip 10 and reducing the difficulty of optical fiber assembly.

[0028] The packaging substrate 40 may be made of PCB, silicon, glass or other optoelectronic packaging materials.

[0029] In particular, the package structure is compatible with two types of APD chips currently used in the industry, such as Figure 2 The first type of APD chip is a surface illumination structure, that is, the external light irradiates the APD chip vertically; the APD chip with surface illumination structure, such as Figure 2 As shown in a, it includes a P electrode, an N electrode and a photosensitive area, wherein the P electrode and the N electrode are electrically connected to the thin film circuit 201 and the TIA chip 30 respectively. In addition, a surface-illuminated APD array chip with four or more channels, such as Figure 2 As shown in b, this packaging structure is also compatible.

[0030] The second type of APD chip is a side-illuminated structure, namely a waveguide-coupled APD chip; a waveguide-coupled APD chip, such as Figure 2 c, including P-electrode, N-electrode, photosensitive area, optical waveguide and edge coupler, wherein the P-electrode and the N-electrode are electrically connected to the thin film circuit 201 and the TIA chip 30 respectively; in addition, a waveguide-coupled APD chip with four or more channels, such as Figure 2 As shown in d, this packaging structure is also compatible.

[0031] In particular, the packaging structure is compatible with different types of electrode connection methods of APD chips, such as Figure 3 The electrode modes of APD chip include: coplanar electrodes, P electrodes and N electrodes on the same plane, such as Figure 3 As shown in a; skew electrodes, the P electrode and the N electrode are in different planes, such as Figure 3 As shown in b; coplanar electrodes, bumped by TSV, such as Figure 3 c; electrodes on different surfaces, one electrode is selected to form a bump through TSV, such as Figure 3 As shown in d.

[0032] In particular, when the electrode bonding point of the APD chip is not in the same plane as the photosensitive area, the APD chip is directly mounted to the interposer unit 20 and the TIA chip 30, such as Figure 4 a; Specifically, the P electrode and N electrode of the APD chip are interconnected with the TIA chip 30 and the interposer unit 20 through bumps. When the APD electrode welding point and the photosensitive area are in the same plane, the APD chip is mounted to the interposer unit 20 and the TIA chip 30 through a flip-chip, as shown in FIG. Figure 4 b; specifically: the P electrode and the N electrode of the APD chip are interconnected with the TIA chip 30 and the intermediate board unit 20 by means of a gold-tin alloy. Specific embodiment 1

[0033] like Figure 5 As shown, a packaging structure of a four-channel surface-illuminated APD array chip is demonstrated.

[0034] The P electrode of the array chip is electrically connected to the electrode of the TIA chip; the N electrode of the array chip is connected to the electrode of the intermediate board unit 20. The intermediate board 203 is a silicon-based material, which is formed by a planar process. Figure 5 The thin film circuit 201 is shown.

[0035] On the metal routing path of the thin film circuit 201, a mounting area for components such as capacitors and resistors is reserved. According to packaging requirements, capacitor components and resistor components with different capacitance and resistance values ​​are mounted to form a capacitor and resistor component 2012.

[0036] Optionally, the capacitors and resistors in the capacitance and resistance component 2012 can also be directly fabricated on the interposer by semiconductor planar processes, for example, by adding TiN material through two parallel electrodes to form an on-chip capacitor, and by selective ion implantation to achieve an on-chip resistor of any resistance value.

[0037] like Figure 5 As shown, the PIN pins ( Figure 5 PIN1-4 in the APD chip are connected to external pins by gold wire bonding to realize external power supply to the APD chip. Specific embodiment 2

[0038] like Figure 6 As shown, a packaging structure of a four-channel waveguide-coupled APD array chip is demonstrated.

[0039] and Figure 5 The packaging structure shown is different in that the interposer unit 20 includes an optical coupling unit 202. Since the waveguide-coupled APD array chip has extremely high requirements for the optical coupling efficiency of the single-mode optical fiber and the edge coupler, the spatial coupling mechanical stability of the general single-mode optical fiber and the APD chip is poor, and a long coupling alignment process is required.

[0040] In this embodiment, a V-groove is directly made on the Si-based interposer as an optical coupling unit for placing a single-mode optical fiber. The direction of the V-groove is aligned with the direction of the APD chip side coupler, facilitating direct connection between the optical fiber and the APD chip. Specific embodiment 3

[0041] like Figure 7 As shown, an avalanche photodiode TO-can package structure including an intermediate board is shown.

[0042] like Figure 7 As shown in a, a schematic diagram of a traditional APD chip TO packaging structure is shown. The N electrode of the APD chip is electrically connected to the capacitor element, the resistor element and the external pin (PIN2) by gold wire bonding to provide an external bias voltage for the APD chip; the placement of the resistor and capacitor elements is not fixed; the P electrode of the APD chip is connected to the TIA chip to realize the conversion of photoelectric signals. In addition, the TIA also needs to be connected to the pins PIN1 and PIN3 by gold wire bonding to provide an external bias voltage for the TIA chip. The connection method of the above components is gold wire bonding, and the electrical interconnection length is very long, so the rate of this packaging solution cannot exceed 200Gbps / lane.

[0043] like Figure 7 As shown in FIG. 2 , a schematic diagram of the TO-can package structure of an avalanche photodiode including an intermediate board is shown. In this solution, the electrical connections between the four APD chips 10, the TIA chip 30 and the external pins PIN1-3 are all completed through the intermediate board unit 20. The APD chip 10 is mounted between the intermediate board unit 20 and the TIA chip 30 by flip-chip method. The intermediate board unit 20 includes three electrical connection branches. Among them, the two ends of the first branch are respectively connected to the N electrode of the APD chip 10 and the TO pin PIN2; wherein, the two ends of the second and third branches are respectively connected to the electrode of the TIA chip 30 and the PIN1 and PIN3 of the TO pin.

[0044] Compared with traditional packaging solutions, the avalanche photodiode packaging structure with an intermediate board greatly reduces the electrical signal transmission path, can significantly improve the signal transmission quality, and is expected to break through the optical reception rate of 200Gbps / lane.

[0045] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A packaging structure of an avalanche photodiode, characterized in that: The invention comprises an APD chip (10), an intermediate board unit (20), a TIA chip (30) and a packaging substrate (40); the intermediate board unit (20) and the TIA chip (30) are both electrically connected to the packaging substrate (40), and the intermediate board unit (20) and the TIA chip (30) are located in the same plane; and two electrodes of the APD chip (10) are electrically connected to the intermediate board unit (20) and the TIA chip (30) respectively.

2. The packaging structure of the avalanche photodiode according to claim 1, characterized in that: The intermediate board unit (20) comprises an intermediate board (203) and a thin film circuit (201) integrated on the intermediate board (203); electrodes in the APD chip (10) are electrically connected to the thin film circuit (201) to provide a bias voltage for the APD chip (10).

3. The packaging structure of the avalanche photodiode according to claim 2, characterized in that: The thin film circuit (201) comprises an electrical connection component (2011) and a capacitance component (2012); the electrical connection component (2011) connects the N electrode in the APD chip (10), the capacitance component (2012) and an external packaging pin; the capacitance component (2012) provides a filtering function for the electrical signal of the external power supply, thereby reducing the noise source.

4. The packaging structure of the avalanche photodiode according to claim 2, characterized in that: The intermediate board unit (20) further comprises an optical coupling unit (202), and the optical coupling unit (202) is integrated on the intermediate board (203).

5. The packaging structure of the avalanche photodiode according to claim 2, characterized in that: The intermediate board (20) is made of silicon, glass or other optoelectronic packaging materials.

6. The packaging structure of the avalanche photodiode according to claim 5, characterized in that: A V-shaped groove is formed on the intermediate plate.

7. The packaging structure of the avalanche photodiode according to claim 1, characterized in that: The packaging substrate (40) is made of PCB, silicon, glass or other optoelectronic packaging materials.

8. The packaging structure of the avalanche photodiode according to claim 1, characterized in that: The APD chip (10) is an APD chip with a surface illumination structure. The APD chip with a surface illumination structure comprises a P electrode, an N electrode and a photosensitive area. The P electrode and the N electrode are electrically connected to the thin film circuit (201) and the TIA chip (30) respectively.

9. The packaging structure of the avalanche photodiode according to claim 1, characterized in that: The APD chip (10) is an APD chip with a side-illuminated structure, comprising a P electrode, an N electrode, a photosensitive region, an optical waveguide and an edge coupler, wherein the P electrode and the N electrode are electrically connected to the thin film circuit (201) and the TIA chip (30) respectively.

10. The packaging structure of the avalanche photodiode according to claim 1, characterized in that: The electrodes of the APD chip (10) are coplanar electrodes or skew electrodes. The coplanar electrodes are bumped in the form of TSVs, and any one of the skew electrodes is bumped in the form of TSVs.

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