Light emitting diode chip and preparation method thereof

Abstract

The invention provides a light-emitting diode chip and a preparation method thereof, and the light-emitting diode chip comprises a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a second insulation protection layer, a P-type conductive metal layer, a reflection layer, an ohmic contact layer, an epitaxial layer, and a third insulation protection layer which are stacked from bottom to top. A plurality of segmentation grooves penetrating through the epitaxial layer are formed in the epitaxial layer, a first insulation protection layer and a stress release metal layer are sequentially arranged in the segmentation grooves in a stacked mode, the thermal expansion coefficient of the stress release metal layer is smaller than that of the epitaxial layer, and the multiple segmentation grooves are prepared in the epitaxial layer to ensure that the stress release metal layer is not damaged in the separation process of the epitaxial layer and the substrate. The generated stress can be conducted and dispersed through the multiple segmentation grooves, the phenomenon that the epitaxial layer is broken or falls off is avoided, the stress release metal layers are arranged in the segmentation grooves, and the phenomenon that the epitaxial layer is broken or falls off due to internal stress of the epitaxial layer and high-temperature warping in the thermocompression bonding process is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a light emitting diode chip and a preparation method thereof. Background Art

[0002] Light-emitting diode chips are energy-efficient and highly efficient, and are widely used in the fields of lighting and display, many of which involve applications with extremely high power, such as outdoor lighting and automotive lighting.

[0003] The preparation of vertical light-emitting diode chips requires a laser lift-off process to separate the epitaxial layer from the substrate. During the laser lift-off process, due to the stress problem in the epitaxial layer, the epitaxial layer is prone to cracking or falling off after the laser lift-off is completed. Summary of the invention

[0004] In view of the above situation, it is necessary to provide a light emitting diode chip and a method for preparing the same in order to solve the problem in the prior art that the epitaxial layer is easily broken or detached after laser lift-off.

[0005] A light-emitting diode chip comprises a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a second insulating protective layer, a P-type conductive metal layer, a reflective layer, an ohmic contact layer, an epitaxial layer, and a third insulating protective layer stacked from bottom to top; The epitaxial layer is provided with a plurality of segmentation grooves penetrating the epitaxial layer, a first insulating protection layer and a stress release metal layer are sequentially stacked in the segmentation grooves, the thermal expansion coefficient of the stress release metal layer is smaller than the thermal expansion coefficient of the epitaxial layer, and the material of the stress release metal layer is metal Cu, metal Ni or metal Ti; A P-type pad layer is disposed on the P-type conductive metal layer.

[0006] Beneficial effects of the present invention: By preparing multiple dividing grooves on the epitaxial layer, it can be ensured that the stress generated during the separation of the epitaxial layer from the substrate can be conducted and dispersed through the multiple dividing grooves, preventing excessive local stress accumulation and thus avoiding the epitaxial layer from cracking or falling off. At the same time, by arranging a stress release metal layer in the dividing grooves, the thermal expansion coefficient of the stress release metal layer is smaller than the thermal expansion coefficient of the epitaxial layer. This characteristic can reduce the generation of thermal stress. After laser peeling, the epitaxial layer can be prevented from cracking or falling off due to the internal stress of the epitaxial layer and high-temperature warping during hot pressing bonding.

[0007] Furthermore, the width of the dividing groove is 3um-5um.

[0008] Furthermore, the first insulating protective layer covers the dividing groove, and the edge of the first insulating protective layer extends 1um-2um in a direction away from the edge of the dividing groove, and the thickness of the first insulating protective layer is 1000Å-1500Å. Furthermore, the thickness of the stress release metal layer is greater than the depth of the dividing groove by 1um-2um.

[0009] On the other hand, the present invention further provides a method for preparing a light emitting diode chip, which is used to prepare the light emitting diode chip as described above, comprising the following steps: Providing a substrate, depositing an epitaxial layer on the substrate, and dividing the epitaxial layer to form a plurality of dividing grooves; forming a first insulating protection layer in the dividing groove; Forming a stress release metal layer by evaporating on the first insulating protective layer; Depositing an ohmic contact layer and a reflective layer on a portion of the epitaxial layer; forming a P-type conductive metal layer on the reflective layer; Forming a second insulating protective layer by evaporating on the P-type conductive metal layer and a portion of the epitaxial layer; Forming an N-type conductive metal layer by evaporation on the second insulating protective layer; Forming a first metal bonding layer by evaporation on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporation on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer; Using laser to peel off the substrate and the epitaxial layer; A third insulating protection layer is deposited on the epitaxial layer, and a P-type pad layer is formed by evaporation on the P-type conductive metal layer.

[0010] Furthermore, the step of dividing the epitaxial layer to form a plurality of dividing grooves includes: A substrate is provided, and an epitaxial layer is prepared on the substrate by using an MOCVD process. The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer which are stacked in sequence from bottom to top. Then, a photoresist is coated on the surface of the P-type semiconductor layer. Part of the photoresist is removed by exposure and development to expose the P-type semiconductor layer under the part of the photoresist. Then, an inductively coupled plasma etching process is used to remove part of the P-type semiconductor layer and the active light-emitting layer and the N-type semiconductor layer under the P-type semiconductor layer until the substrate is exposed. Then, the photoresist is removed and the epitaxial layer is divided to form a plurality of dividing grooves.

[0011] Furthermore, the step of forming a first insulating protection layer in the dividing groove includes: Using the PECVD process, a SiO2 layer is deposited on the surface of the dividing groove and the P-type semiconductor layer, and then a photoresist is coated on the SiO2 layer. Then, part of the photoresist is removed by exposure and development to expose the SiO2 layer under the photoresist. Then, a BOE etching solution is used to remove the exposed SiO2 layer, and then the photoresist is removed. The remaining SiO2 layer forms a first insulating protective layer.

[0012] Further, the step of forming a stress release metal layer on the first insulating protection layer includes: A negative photoresist layer is coated on the surface of the first insulating protective layer and the P-type semiconductor layer not covered by the first insulating protective layer, and then a portion of the photoresist is removed by exposure and development to form a photoresist through hole, wherein the photoresist through hole corresponds to the position of the dividing groove, the photoresist through hole is trapezoidal, and the width of the bottom of the photoresist through hole is equal to the width of the dividing groove; A metal layer is evaporated on the surface of the photoresist layer and in the photoresist through hole by using an electron beam evaporation process, and then the metal on the photoresist layer is removed by a blue film stripping process, and then the photoresist layer is removed to form a stress release metal layer on the first insulating protective layer.

[0013] Further, the step of depositing an ohmic contact layer and a reflective layer on the epitaxial layer comprises: Continue to coat the epitaxial layer and the stress release metal layer with negative photoresist, then expose and develop to remove part of the photoresist to form a photoresist opening, then use a magnetron sputtering process to deposit an ITO layer on the photoresist and the photoresist opening as an ohmic contact layer, then use a magnetron sputtering process to deposit Ag metal on the surface of the ohmic contact layer as a reflective layer, then use a blue film stripping process to remove the ITO layer and Ag metal on the photoresist, and then remove the photoresist layer.

[0014] Furthermore, the step of forming a P-type conductive metal layer on the reflective layer includes: A negative photoresist is coated on the surface of the reflective layer and the ohmic contact layer not covered by the reflective layer, and then a portion of the photoresist is removed by exposure and development. Then, Ti metal, Pt metal, Au metal and Cr metal are sequentially evaporated by an electron beam evaporation process, and then the metal on the photoresist is removed by a Lift-Off process. Then, the photoresist is removed to form a P-type conductive metal layer, and the projection of the P-type conductive metal layer on the P-type semiconductor layer completely covers the projection of the reflective layer on the P-type semiconductor layer.

[0015] Further, etching a portion of the epitaxial layer to form an N-type semiconductor conductive step; A photoresist is coated on the surface of the P-type conductive metal layer and the surface of the P-type semiconductor layer not covered by the P-type conductive metal layer, and then a portion of the photoresist is removed by exposure and development to expose a portion of the P-type semiconductor layer. An inductively coupled plasma etching process is then used to remove the exposed portion of the P-type semiconductor layer and the active light-emitting layer thereunder until the N-type semiconductor layer is reached to form an N-type semiconductor conductive step, and then the photoresist is removed.

[0016] Further, a second insulating protective layer is formed by evaporating on the P-type conductive metal layer and a portion of the epitaxial layer; Continue to coat the P-type conductive metal layer, the P-type semiconductor layer not covered by the P-type conductive metal layer, and the surface of the N-type semiconductor conductive step with negative photoresist, and then remove part of the negative photoresist by exposure and development; then evaporate the SiO2 layer by electron beam evaporation process, and then remove the SiO2 layer on the negative photoresist by blue film stripping process, and then remove the photoresist to form a second insulating protective layer.

[0017] Furthermore, the step of evaporating and forming an N-type conductive metal layer on the second insulating protective layer includes: Cr metal, Al metal, Ti metal and Pt metal are sequentially deposited on the second insulating protection layer and the N-type semiconductor conductive step by electron beam evaporation process to form an N-type conductive metal layer.

[0018] Further, the steps of forming a first metal bonding layer by evaporating on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporating on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer include: A metal bonding layer is evaporated using an electron beam evaporation process, wherein the metal bonding layer includes a first metal bonding layer and a second metal bonding layer, and the first metal bonding layer is formed by evaporation on the N-type conductive metal layer. A conductive silicon wafer is provided, and the second metal bonding layer is formed by evaporation on the conductive silicon wafer. The first metal bonding layer and the second metal bonding layer both include a stack of Ti metal and 2-5 groups of Sn metal and Ni metal, and then the first metal bonding layer and the second metal bonding layer are bonded using a hot pressing bonding process.

[0019] Furthermore, the step of peeling the substrate and the epitaxial layer by using laser comprises: The substrate is irradiated with laser light to decompose GaN at a junction surface between a portion of the substrate and the N-type semiconductor layer to generate metal Ga and N2, thereby decomposing and removing the substrate.

[0020] Further, the step of etching part of the epitaxial layer to form a P-type conductive through hole includes: After stripping and removing the substrate, the surface of the epitaxial layer is coated with photoresist, and then a mask is used to expose part of the photoresist, and then developed to remove the exposed part of the photoresist; the epitaxial layer under the part of the photoresist is exposed; then, the inductively coupled plasma etching process is used to etch and remove the exposed part of the epitaxial layer to form a P-type conductive through hole.

[0021] Furthermore, the step of depositing a third insulating protection layer on the epitaxial layer and evaporating a P-type pad layer on the P-type conductive metal layer comprises: An Al2O3 layer is deposited on the surface of the P-type conductive through hole and the epitaxial layer as a third insulating protective layer by using an atomic layer deposition device, a negative photoresist is coated on the surface of the third insulating protective layer, and then a portion of the photoresist is removed by exposure and development to expose a portion of the third insulating protective layer, and then BOE is used to corrode the exposed third insulating protective layer and the epitaxial layer thereunder until the P-type conductive metal layer to form a third insulating protective layer through hole, and then Ti metal, Pt metal, Au metal, Ni metal and Au metal are sequentially evaporated by an electron beam evaporation process, and then the metal on the photoresist is removed by a Lift-Off process, and then the photoresist is removed to form a P-type pad layer on the P-type conductive metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 A schematic structural diagram of a light emitting diode chip according to a first embodiment of the present invention; Figure 2 is a flow chart of a method for preparing a light emitting diode chip according to a second embodiment of the present invention; Figure 3 for Figure 2 A schematic diagram of the semi-finished product structure after completing step S2; Figure 4 for Figure 2 Schematic diagram of the semi-finished product structure completing step S3.

[0024] In the figure: 10, substrate; 11, epitaxial layer; 111, N-type semiconductor layer; 112, active light-emitting layer; 113, P-type semiconductor layer; 114, dividing groove; 115, N-type semiconductor conductive step; 12, first insulating protection layer; 13, photoresist layer; 14, stress release metal layer; 15, ohmic contact layer; 16, reflective layer; 17, P-type conductive metal layer; 18, second insulating protection layer; 19, N-type conductive metal layer; 20, metal bonding layer; 21, conductive silicon wafer; 22, P-type conductive through hole; 23, third insulating protection layer; 24, P-type pad layer.

[0025] The embodiments of the present invention will be further described below with reference to the accompanying drawings. DETAILED DESCRIPTION

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0027] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0029] Embodiment 1 A light emitting diode chip, such as Figure 1 As shown, it includes a conductive silicon wafer 21, a metal bonding layer 20, an N-type conductive metal layer 19, a second insulating protection layer 18, a P-type conductive metal layer 17, a reflective layer 16, an ohmic contact layer 15, an epitaxial layer 11, and a third insulating protection layer 23 stacked from bottom to top; The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 which are stacked in sequence from bottom to top. A plurality of split grooves 114 are provided on the epitaxial layer 11. The split grooves 114 penetrate the N-type semiconductor layer 111, the active light-emitting layer 112 and the P-type semiconductor layer 113. The width of the split grooves 114 is 3 um. A first insulating protection layer 12 and a stress release metal layer 14 are stacked in sequence in the split grooves 114. The thickness of the stress release metal layer 14 is greater than the depth of the split grooves 114, which is 1.5 um. The thermal expansion coefficient of the stress release metal layer 14 is less than the thermal expansion coefficient of the epitaxial layer 11. The material of the stress release metal layer 14 is metal Cu. A P-type pad layer 24 is disposed on the P-type conductive metal layer 17 .

[0030] Specifically, the width of the dividing groove 114 is 3um. The first insulating protective layer 12 covers the dividing groove 114, and the edge of the first insulating protective layer 12 extends 1um in the direction away from the edge of the dividing groove 114, and the thickness of the first insulating protective layer 12 is 1000Å. Such a setting of the first insulating protective layer 12 can effectively electrically isolate the dividing groove 114 from other components or circuits, and this isolation can prevent leakage between different circuit areas. The setting of the edge distance of 1μm can optimize the stress distribution to a certain extent. When subjected to external temperature changes, mechanical stress, etc., the closer distance between the edge of the first insulating protective layer 12 and the edge of the dividing groove 114 helps to transfer the stress more evenly. If the edge distance is too large, a stress concentration point will be formed, resulting in cracks and other damage to the first insulating protective layer 12 or the structure below.

[0031] The present invention, by preparing a plurality of dividing grooves 114 on the epitaxial layer 11, can ensure that the stress generated during the separation process of the epitaxial layer 11 and the substrate 10 can be released through the plurality of dividing grooves 114, thereby preventing the occurrence of excessive local stress and further avoiding the phenomenon of the epitaxial layer 11 being broken or falling off. At the same time, by arranging a stress release metal layer 14 in the dividing grooves 114, the thermal expansion coefficient of the stress release metal layer 14 is smaller than the thermal expansion coefficient of the epitaxial layer 11. In the process involving temperature changes, such as laser stripping operation, due to the difference in thermal expansion coefficients between the two, this characteristic can reduce the generation of thermal stress. The reduction of such thermal stress is of vital importance to the stability of the epitaxial layer 11, because thermal stress may cause changes in the internal structure of the epitaxial layer 11. After laser stripping, the occurrence of the epitaxial layer 11 being broken or falling off caused by the internal stress of the epitaxial layer 11 and the high-temperature warping during the hot pressing bonding process can be avoided.

[0032] Embodiment 2 See also Figures 1 to 3As shown, this embodiment provides a method for preparing a light emitting diode chip, which is used to prepare the flip-chip light emitting diode chip described in the first embodiment. The preparation method comprises the following steps: S1, providing a substrate 10, depositing an epitaxial layer 11 on the substrate 10, and dividing the epitaxial layer 11 to form a plurality of dividing grooves 114; Furthermore, in this embodiment, the specific process for preparing the dividing groove 114 is as follows: A substrate 10 is provided, and an epitaxial layer 11 is prepared on the substrate 10 by using a MOCVD process. The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 which are stacked in sequence from bottom to top. Then, a photoresist is coated on the surface of the P-type semiconductor layer 113, and a portion of the photoresist is removed by exposure and development to expose the P-type semiconductor layer 113 under the portion of the photoresist. Then, an inductively coupled plasma etching process is used to remove a portion of the P-type semiconductor layer 113 and the active light-emitting layer 112 and the N-type semiconductor layer 111 under the P-type semiconductor layer 113 until the substrate 10 is exposed. Then, the photoresist is removed, and the epitaxial layer 11 is divided to form a plurality of dividing grooves 114.

[0033] The width of the dividing groove 114 is 3 um.

[0034] S2, forming a first insulating protection layer 12 in the dividing groove 114; Furthermore, in this embodiment, the specific process for preparing the first insulating protection layer 12 is as follows: By using the PECVD process, a SiO2 layer is deposited on the surface of the dividing groove 114 and the P-type semiconductor layer 113, and then a photoresist is coated on the SiO2 layer. Then, a portion of the photoresist is removed by exposure and development to expose the SiO2 layer under the photoresist. Then, a BOE etching solution is used to remove the exposed portion of the SiO2 layer. Then, the photoresist is removed, and the remaining SiO2 layer forms a first insulating protective layer 12 in the dividing groove 114.

[0035] The first insulating protection layer 12 covers the dividing groove 114 , and the edge of the first insulating protection layer 12 extends 1 um in a direction away from the edge of the dividing groove 114 , and the thickness of the first insulating protection layer 12 is 1000Å.

[0036] S3, forming a stress release metal layer 14 on the first insulating protection layer 12; Furthermore, in this embodiment, the specific process for preparing the stress release metal layer 14 is as follows: A negative photoresist layer 13 is coated on the surface of the first insulating protective layer 12 and the surface of the P-type semiconductor layer 113 not covered by the first insulating protective layer 12, and then a portion of the photoresist is removed by exposure and development to form a photoresist through hole, wherein the photoresist through hole corresponds to the position of the dividing groove 114, the photoresist through hole is trapezoidal, and the width of the bottom of the photoresist through hole is equal to the width of the dividing groove 114; A metal layer is deposited on the surface of the photoresist layer 13 and in the photoresist through hole by electron beam evaporation process, and then the metal on the photoresist layer 13 is removed by blue film stripping process to form a stress release metal layer 14 on the first insulating protection layer 12 .

[0037] The thickness of the stress release metal layer 14 is greater than the depth of the dividing groove 114 by 1.5 um.

[0038] S4, depositing an ohmic contact layer 15 and a reflective layer 16 on a portion of the epitaxial layer 11; Furthermore, in this embodiment, the specific process for preparing the ohmic contact layer 15 and the reflective layer 16 is as follows: On the epitaxial layer 11 and the stress release metal layer 14, negative photoresist is continuously coated, and then part of the photoresist is removed by exposure and development to form a photoresist opening, and then an ITO layer is deposited on the photoresist and the photoresist opening by a magnetron sputtering process as an ohmic contact layer 15, and then Ag metal is deposited on the surface of the ohmic contact layer 15 by a magnetron sputtering process as a reflective layer 16, and then a blue film stripping process is used to remove the ITO layer and Ag metal on the photoresist, and then the photoresist layer 13 is removed.

[0039] S5, forming a P-type conductive metal layer 17 on the reflective layer 16; Furthermore, in this embodiment, the specific process for preparing the P-type conductive metal layer 17 is as follows: A negative photoresist is coated on the surface of the reflective layer 16 and the ohmic contact layer 15 not covered by the reflective layer 16, and then a portion of the photoresist is removed by exposure and development. Then, Ti metal, Pt metal, Au metal and Cr metal are sequentially evaporated by an electron beam evaporation process, and then the metal on the photoresist is removed by a Lift-Off process. Then, the photoresist is removed to form a P-type conductive metal layer 17, and the projection of the P-type conductive metal layer 17 on the P-type semiconductor layer 113 completely covers the projection of the reflective layer 16 on the P-type semiconductor layer 113.

[0040] S6, etching a portion of the epitaxial layer 11 to form an N-type semiconductor conductive step 115; Furthermore, in this embodiment, the specific process for preparing the N-type semiconductor conductive step 115 is as follows: Photoresist is coated on the surface of the P-type conductive metal layer 17 and the surface of the P-type semiconductor layer 113 not covered by the P-type conductive metal layer 17, and then a portion of the photoresist is removed by exposure and development to expose a portion of the P-type semiconductor layer 113, and then an inductively coupled plasma etching process is used to remove the exposed portion of the P-type semiconductor layer 113 and the active light-emitting layer 112 thereunder until the N-type semiconductor layer 111 is reached to form an N-type semiconductor conductive step 115, and then the photoresist is removed.

[0041] S7, forming a second insulating protection layer 18 by evaporation on the P-type conductive metal layer 17 and a portion of the epitaxial layer 11; Furthermore, in this embodiment, the specific process for preparing the second insulating protection layer 18 is as follows: Continue to coat the P-type conductive metal layer 17, the P-type semiconductor layer 113 not covered by the P-type conductive metal layer 17, and the surface of the N-type semiconductor conductive step 115 with negative photoresist, and then remove part of the negative photoresist by exposure and development; then evaporate the SiO2 layer by electron beam evaporation process, and then remove the SiO2 layer on the negative photoresist by blue film stripping process, and then remove the photoresist to form a second insulating protective layer 18.

[0042] S8, forming an N-type conductive metal layer 19 by evaporation on the second insulating protection layer 18; Furthermore, in this embodiment, the specific process for preparing the N-type conductive metal layer 19 is as follows: Cr metal, Al metal, Ti metal and Pt metal are sequentially deposited on the second insulating protection layer 18 and the N-type semiconductor conductive step 115 by electron beam evaporation process to form an N-type conductive metal layer 19 .

[0043] S9, forming a first metal bonding layer by evaporation on the N-type conductive metal layer 19, providing a conductive silicon wafer 21, forming a second metal bonding layer by evaporation on the conductive silicon wafer 21, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer 20; Furthermore, in this embodiment, the specific process of bonding the first metal bonding layer and the second metal bonding layer to form the metal bonding layer 20 is: The first metal bonding layer is formed by evaporation on the N-type conductive metal layer 19 by electron beam evaporation process, a conductive silicon wafer 21 is provided, and the second metal bonding layer is formed by evaporation on the conductive silicon wafer 21, the first metal bonding layer and the second metal bonding layer both include Ti metal and 2-5 groups of Sn metal and Ni metal stacks, and then the first metal bonding layer and the second metal bonding layer are bonded to form a metal bonding layer 20 by a hot pressing bonding process.

[0044] S10, peeling off the substrate 10 and the epitaxial layer 11 by using a laser; Furthermore, in this embodiment, the specific process of peeling off the substrate 10 and the epitaxial layer 11 is as follows: The substrate 10 is irradiated with a laser to decompose GaN at the interface between the substrate 10 and the N-type semiconductor layer 111 to generate metal Ga and N2, thereby decomposing and removing the substrate 10. The laser is a 266nm ultraviolet laser, the spot radius of the laser is 13 um, the spot movement speed of the laser is 2800 mm / s, and the power of the laser is 5W.

[0045] S11, etching a portion of the epitaxial layer 11 to form a P-type conductive through hole 22; Furthermore, in this embodiment, the specific process for preparing the P-type conductive via 22 is as follows: After stripping and removing the substrate 10, the surface of the epitaxial layer 11 is coated with photoresist, and then a portion of the photoresist is exposed using a mask and then developed to remove the exposed portion of the photoresist; the epitaxial layer 11 under the portion of the photoresist is exposed, and then, the exposed portion of the epitaxial layer 11 is removed by etching using an inductively coupled plasma etching process to form a P-type conductive through hole 22.

[0046] S12, depositing a third insulating protection layer 23 on the epitaxial layer 11, and forming a P-type pad layer 24 by evaporation on the P-type conductive metal layer 17; Furthermore, in this embodiment, the specific process for preparing the P-type pad layer 24 is as follows: An Al2O3 layer is deposited on the surface of the P-type conductive through hole 22 and the remaining epitaxial layer 11 by using an atomic layer deposition device as a third insulating protective layer 23, a negative photoresist is coated on the surface of the third insulating protective layer 23, and then a portion of the photoresist is removed by exposure and development to expose a portion of the third insulating protective layer 23, and then BOE is used to etch the exposed third insulating protective layer 23 and the epitaxial layer 11 thereunder until the P-type semiconductor layer 113, so as to form a third insulating protective layer through hole; and then an electron beam evaporation process is used to sequentially evaporate Ti metal, Pt metal, Au metal, Ni metal and Au metal, and then a Lift-Off process is used to remove the metal on the photoresist, and then the photoresist is removed to form a P-type pad layer 24.

[0047] Embodiment 3 The difference from the second embodiment is that: The material of the stress release metal layer 14 is metal Ni, the width of the dividing groove 114 is 3.2 um, the edge of the first insulating protection layer 12 extends 1.5 um in a direction away from the edge of the dividing groove 114, and the thickness of the first insulating protection layer 12 is 1100Å.

[0048] Embodiment 4 The difference from the second embodiment is that: The material of the stress release metal layer 14 is metal Ti, the width of the dividing groove 114 is 3.8 um, the edge of the first insulating protection layer 12 extends 1.6 um in a direction away from the edge of the dividing groove 114, and the thickness of the first insulating protection layer 12 is 1300Å.

[0049] Embodiment 5 The difference from the second embodiment is that: The material of the stress release metal layer 14 is metal Ni, the width of the dividing groove 114 is 4.3 um, the edge of the first insulating protection layer 12 extends 1.8 um in a direction away from the edge of the dividing groove 114, and the thickness of the first insulating protection layer 12 is 1400Å.

[0050] Embodiment 6 The difference from the second embodiment is that: The material of the stress release metal layer 14 is metal Ni, the width of the dividing groove 114 is 5um, the edge of the first insulating protection layer 12 extends 2um away from the edge of the dividing groove 114, and the thickness of the first insulating protection layer 12 is 1500Å.

[0051] Comparative Example The light emitting diode chip of the comparative example is prepared by the existing process, and the light emitting diode chip is not provided with the dividing groove 114 and the stress release metal layer 14 .

[0052] The laser lift-off yield of the light-emitting diode chip prepared in the comparative example was compared with that of the light-emitting diode chips prepared in Examples 2 to 6, and the corresponding test results are shown in Table 1: Table 1

[0053] It should be noted that in order to ensure the reliability of the verification results, when comparing the laser lift-off yield of the light-emitting diode chips prepared in the above-mentioned comparative example of the present invention and the light-emitting diode chips prepared in Examples 2 to 6, other processes and parameters except the above-mentioned parameters should remain consistent.

[0054] It can be seen from the above table that the laser lift-off yield of the light emitting diode chips prepared in Examples 2 to 6 is significantly improved compared with the light emitting diode chips prepared in the comparative example.

[0055] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0056] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A light emitting diode chip, characterized in that: It includes a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a second insulating protective layer, a P-type conductive metal layer, a reflective layer, an ohmic contact layer, an epitaxial layer, and a third insulating protective layer stacked from bottom to top; The epitaxial layer is provided with a plurality of segmentation grooves penetrating the epitaxial layer, a first insulating protection layer and a stress release metal layer are sequentially stacked in the segmentation grooves, the thermal expansion coefficient of the stress release metal layer is smaller than the thermal expansion coefficient of the epitaxial layer, and the material of the stress release metal layer is metal Cu, metal Ni or metal Ti; A P-type pad layer is disposed on the P-type conductive metal layer.

2. The light emitting diode chip according to claim 1, characterized in that: The width of the dividing groove is 3um-5um.

3. The light emitting diode chip according to claim 1, characterized in that: The first insulating protective layer covers the dividing groove, and the edge of the first insulating protective layer extends 1um-2um away from the edge of the dividing groove. The thickness of the first insulating protective layer is 1000Å-1500Å.

4. The light emitting diode chip according to claim 1, characterized in that: The thickness of the stress release metal layer is greater than the depth of the dividing groove by 1um-2um.

5. A method for preparing a light emitting diode chip, for preparing the light emitting diode chip according to any one of claims 1 to 4, characterized in that: The following steps are involved: Providing a substrate, depositing an epitaxial layer on the substrate, and dividing the epitaxial layer to form a plurality of dividing grooves; forming a first insulating protection layer in the dividing groove; Forming a stress release metal layer by evaporating on the first insulating protective layer; Depositing an ohmic contact layer and a reflective layer on a portion of the epitaxial layer; forming a P-type conductive metal layer on the reflective layer; Forming a second insulating protective layer by evaporating on the P-type conductive metal layer and a portion of the epitaxial layer; Forming an N-type conductive metal layer by evaporation on the second insulating protective layer; Forming a first metal bonding layer by evaporation on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporation on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer; Using laser to peel off the substrate and the epitaxial layer; A third insulating protection layer is deposited on the epitaxial layer, and a P-type pad layer is formed by evaporation on the P-type conductive metal layer.

6. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The step of dividing the epitaxial layer to form a plurality of dividing grooves comprises: A substrate is provided, an epitaxial layer is prepared on the substrate by using an MOCVD process, a photoresist is coated on the surface of the epitaxial layer, a part of the photoresist is removed by exposure and development to expose the epitaxial layer under the part of the photoresist, and then a part of the epitaxial layer is removed by using an inductively coupled plasma etching process until the substrate is exposed, the epitaxial layer is divided to form a plurality of dividing grooves, and the photoresist is removed.

7. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The step of forming a first insulating protection layer in the dividing groove comprises: Using the PECVD process, a SiO2 layer is deposited on the surface of the dividing groove and the epitaxial layer, and then a photoresist is coated on the SiO2 layer. Then, part of the photoresist is removed by exposure and development to expose the SiO2 layer under the photoresist. Then, a BOE etching solution is used to remove the exposed SiO2 layer, and then the photoresist is removed. The remaining SiO2 layer forms a first insulating protective layer.

8. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The step of forming a stress release metal layer by evaporating on the first insulating protective layer comprises: A negative photoresist is coated on the first insulating protective layer and the surface of the epitaxial layer not covered by the first insulating protective layer, and then a portion of the photoresist is removed by exposure and development to form a photoresist through hole, wherein the photoresist through hole corresponds to the position of the segmentation groove, the photoresist through hole is trapezoidal, and the width of the bottom of the photoresist through hole is the same as the width of the segmentation groove; A metal layer is evaporated on the surface of the photoresist layer using an electron beam evaporation process, and then the metal on the photoresist layer is removed using a blue film stripping process. The photoresist layer is then removed to form a stress release metal layer on the first insulating protective layer.

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