LED chip and brightening method thereof

Abstract

The invention discloses an LED chip and a brightening method thereof, and the method comprises the following steps: S1, etching an MESA structure on an epitaxial layer, enabling an N-GaN layer to be exposed, and forming a positive electrode and a negative electrode; s2, etching the N-GaN at the edge of the LED chip until an isolation layer is formed on the surface of the sapphire substrate; s3, sputtering an ITO layer on the epitaxial layer, and keeping a first distance between the ITO layer and the MESA structure; s4, manufacturing a first insulating layer along the edge of the MESA structure, and enabling the first insulating layer to wrap the MESA structure; and S5, sequentially forming a DBR layer, a second insulating layer and a silver mirror reflecting layer on the first insulating layer. According to the invention, the brightness of the LED chips can be improved, so that the number of the LED chips used in the packaging body is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of LED chip production, and in particular to an LED chip and a brightening method thereof. Background Art

[0002] LED, or light-emitting diode, is a solid-state semiconductor device that converts electrical energy into light energy. As the application trend of LED in car lights becomes increasingly prominent, the LED chips used in flip-chip cars are usually packaged together by 6 to 10 chips on the same substrate. However, in order to reduce costs and increase efficiency, manufacturers are now deliberately reducing the number of chips placed in a single package, while also maintaining the brightness of the package, which increases the brightness requirements for each chip.

[0003] In order to solve the above problems, a Chinese patent document discloses a method for improving the brightness of LED chips (Announcement No. CN101740692A), which specifically discloses using a metal layer as a mask to etch the N-GaN layer on the side wall of the scribe path, so that the N-GaN layer has a "gradient inverted triangle" structure; removing the metal layer; making transparent electrodes, N / P electrodes, and SiO2 passivation layers on the etched chip unit; grinding and thinning the back of the LED wafer, and then using a chip splitter to split the LED chip. The present invention can change the propagation distance of light, increase the probability of photons escaping from the chip, and improve the light extraction efficiency of the LED chip.

[0004] Although the brightness enhancement method in the above patent document can improve the brightness of the LED chip, it has high requirements for the chip thickness, that is, the chip should have a certain thickness to facilitate the formation of the inverted triangle structure. Although it can reduce the use of chips, it will increase the overall volume of the package. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an LED chip and a brightening method thereof, which can reduce the number of chips while ensuring that the brightness of the package does not decrease.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for brightening an LED chip comprises the following steps: S1: Etching a MESA structure on the epitaxial layer to expose the N-GaN layer and form positive and negative electrodes; S2: Etching the N-GaN at the edge of the LED chip until an isolation layer is formed on the surface of the sapphire substrate; S3: sputtering an ITO layer on the epitaxial layer, and maintaining a first distance between the ITO layer and the MESA structure; S4: forming a first insulating layer along the edge of the MESA structure so that the first insulating layer covers the MESA structure; S5: forming a DBR layer, a second insulating layer and a silver mirror reflection layer in sequence on the first insulating layer.

[0007] In order to solve the above technical problems, another technical solution adopted by the present invention is: An LED chip is manufactured by the above-mentioned LED chip brightening method, comprising a sapphire substrate, an epitaxial layer, a first insulating layer, a DBR layer, a second insulating layer and a silver mirror reflection layer which are stacked in sequence from bottom to top.

[0008] The beneficial effect of the present invention is that after forming the MESA structure, a first insulating layer is made to provide insulating protection for the MESA structure to prevent the chip from leaking electricity, and then a DBR layer (i.e., a distributed Bragg reflection layer), a second insulating layer, and a silver mirror reflection layer are sequentially formed on the first insulating layer. Due to the superposition of the DBR layer and the silver mirror reflection layer and the formation of the MESA structure, the reflectivity is improved, that is, the brightness of the LED chip can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view of the LED chip in the present invention; Figure 2 Graph showing the reflectivity test results of Example 2 of the present invention and Comparative Example 1.

[0010] Description of labels: 1. MESA structure; 2. Sapphire substrate; 3. First insulating layer; 4. DBR layer; 41. Current through hole; 5. Second insulating layer; 51. Support part; 6. Silver mirror reflection layer; 7. P pole; 8. N pole; 9. Epitaxial layer; 10. Pattern. DETAILED DESCRIPTION

[0011] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0012] A method for brightening an LED chip comprises the following steps: S1: etching the MESA structure 1 on the epitaxial layer 9 to expose the N-GaN layer and form positive and negative electrodes; S2: Etching the N-GaN at the edge of the LED chip until an isolation layer is formed on the surface of the sapphire substrate 2; S3: sputtering an ITO layer on the epitaxial layer 9, and maintaining a first distance between the ITO layer and the MESA structure 1; S4: forming a first insulating layer 3 along the edge of the MESA structure 1 so that the first insulating layer 3 covers the MESA structure 1; S5 : forming a DBR layer 4 , a second insulating layer 5 and a silver mirror reflection layer 6 in sequence on the first insulating layer 3 .

[0013] It can be understood that after forming the MESA structure 1, the first insulating layer 3 is made to provide insulation protection for the MESA structure 1 to prevent the chip from leaking electricity, and then the DBR layer 4, the second insulating layer 5 and the silver mirror reflection layer 6 are sequentially formed on the first insulating layer 3. Due to the superposition of the DBR layer 4 and the silver mirror reflection layer 6, and the formation of the MESA structure 1, the reflectivity is improved, that is, the brightness of the LED chip can be improved. The above-mentioned isolation layer is located between two adjacent chips.

[0014] In some embodiments, step S1 is specifically to etch the MESA structure 1 on the epitaxial layer 9, that is, to remove the P-GaN layer and the quantum well and expose the N-GaN layer, and to form positive and negative electrodes.

[0015] In some embodiments, the first distance is about 14 μm, and may also be 12 μm, 13 μm, 14 μm, 15 μm, or 16 μm.

[0016] In some embodiments, step S5 includes the following steps: S51: evaporating a DBR layer 4 on the first insulating layer 3; S52: etching a current through hole 41 on the DBR layer 4; S53: depositing a second insulating layer 5 on the DBR layer 4; S54 : forming a silver mirror reflection layer 6 on the second insulating layer 5 .

[0017] The DBR layer 4 is formed by alternately evaporating SIO2 and Ti3O5 according to a preset thickness, with a total of 13 layers; due to the formation of the DBR layer 4, the reflectivity of the metal oxide is utilized to enhance the brightness of the LED chip. Preferably, the first insulating layer 3 and the second insulating layer 5 are both SIO2 insulating layers. Further, current through holes 41 should be etched on the DBR layer 4 of the P pole 7 and the N pole 8, respectively.

[0018] In some embodiments, in step S52, the current through hole 41 penetrates the DBR layer 4 and permeates into the first insulating layer 3. Specifically, the DBR layer 4 is etched with CF4 to form the current through hole 41, and since the actual depth of the current through hole 41 should be greater than the thickness of the DBR layer 4 to ensure that there is no residue on the DBR layer 4, the current through hole 41 extends to the first insulating layer 3 after penetrating the DBR layer 4, and the etching of the first insulating layer 3 is stopped after the etching depth of the first insulating layer 3 reaches half of the thickness of the first insulating layer 3.

[0019] In some embodiments, the specific steps of step S54 are to apply photoresist on the second insulating layer and expose and develop to form the corresponding pattern 10, etch a part of the second insulating layer 5 so that the second insulating layer 5 forms a support portion 51, and evaporate on the support portion 51 to form the silver mirror reflection layer 6. The second insulating layer 5 is provided, and the support portion 51 is formed in a part of the second insulating layer 5 by etching, so as to form a height difference between the silver mirror reflection layer 6 and most of the second insulating layer 5, so as to avoid the silver mirror reflection layer 6 from warping and ensure its reflection effect. In fact, the formation of the support portion 51 is used as the chamfer of the silver mirror reflection layer 6.

[0020] In some embodiments, the photoresist is a negative-tone photoresist.

[0021] In some embodiments, in step S54, the second insulating layer 5 is corroded by a BOE solution; the BOE solution includes ammonium fluoride and hydrogen fluoride, and the ratio of ammonium fluoride to hydrogen fluoride is (10-12): (0.5-2). Preferably, the ratio of ammonium fluoride to hydrogen fluoride is 12:1. Optionally, the ratio can be 10:0.5, 10:1, 10:2, 11:0.5, 11:1, 11:2, 12:0.5 or 12:2.

[0022] In some embodiments, the etching depth of the second insulating layer 5 is at most half of the thickness of the second insulating layer 5 , which can ensure the insulating effect of the second insulating layer 5 and form a sufficient height difference between the corroded portion of the second insulating layer 5 and the silver mirror reflection layer 6 .

[0023] Please refer to Figure 1 as well as Figure 2 An LED chip is made by the above-mentioned LED chip brightening method, including a sapphire substrate 2, an epitaxial layer 9, a first insulating layer 3, a DBR layer 4, a second insulating layer 5 and a silver mirror reflection layer 6 stacked in sequence from bottom to top.

[0024] Embodiment 1 of the present invention is: A method for brightening an LED chip comprises the following steps: S1: etching a MESA structure 1 on the epitaxial layer 9 to expose the N-GaN layer and form positive and negative electrodes; specifically, etching a MESA structure 1 on the epitaxial layer 9 to remove the P-GaN layer and the quantum well and expose the N-GaN layer to form positive and negative electrodes.

[0025] S2: Etching the N-GaN at the edge of the LED chip until an isolation layer is formed on the surface of the sapphire substrate 2; S3: sputtering an ITO layer on the epitaxial layer 9, and maintaining a distance of about 14 μm between the ITO layer and the MESA structure 1; S4: forming a first insulating layer 3 along the edge of the MESA structure 1 so that the first insulating layer 3 covers the MESA structure 1; S5 : forming a DBR layer 4 , a second insulating layer 5 and a silver mirror reflection layer 6 in sequence on the first insulating layer 3 .

[0026] Specifically, step S5 includes the following steps: S51: evaporating a DBR layer 4 on the first insulating layer 3; S52: etching a current through hole 41 on the DBR layer 4; specifically, the current through hole 41 penetrates the DBR layer 4 and permeates into the first insulating layer 3, and the etching is stopped after the etching depth of the first insulating layer 3 reaches half of the thickness of the first insulating layer 3; S53: depositing a second insulating layer 5 on the DBR layer 4; preferably, the first insulating layer 3 and the second insulating layer 5 are both SIO2 insulating layers; S54: a silver mirror reflective layer 6 is formed on the second insulating layer 5; specifically, a photoresist is coated on the second insulating layer 5 and exposed and developed to form a corresponding pattern 10, and a partial area on the second insulating layer 5 is etched, and the etching depth of the second insulating layer 5 is half of the thickness of the second insulating layer 5, so that the second insulating layer 5 forms a supporting portion 51, and vapor deposition is performed on the supporting portion 51 to form a silver mirror reflective layer 6; since BOE only corrodes the SIO2 insulating layer and does not corrode the photoresist, the second insulating layer 5 is corroded by a BOE solution after the photoresist is formed; the BOE solution includes ammonium fluoride and hydrogen fluoride, and the ratio of ammonium fluoride to hydrogen fluoride is 12:1.

[0027] The DBR layer 4 is formed by alternately evaporating SIO2 and TI3O5 according to a preset thickness, with a total of 13 layers; current through holes 41 should be etched on the DBR layer 4 of the P pole 7 and the N pole 8 respectively; and the photoresist is a negative photoresist.

[0028] Embodiment 2 of the present invention is: An LED chip is manufactured based on the first embodiment.

[0029] An LED chip is made by the above-mentioned LED chip brightening method, comprising a sapphire substrate 2, an epitaxial layer 9, a first insulating layer 3, a DBR layer 4, a second insulating layer 5, a photolithography layer and a silver mirror reflection layer 6 which are stacked in sequence from bottom to top; the second insulating layer 5 has a support portion 51, the silver mirror reflection layer 6 is formed on the support portion 51 and extends in a direction away from the support portion 51, the photolithography layer is located in a recessed portion of the second insulating layer 5 and is spaced apart from the silver mirror reflection layer 6.

[0030] Comparative Example 1: An LED chip comprises a sapphire substrate, an epitaxial layer, an insulating layer and a silver mirror reflecting layer which are sequentially stacked on top of each other.

[0031] In this comparative example, the silver mirror reflection layer is directly disposed on the insulating layer, and a negative resist is used to make a chamfer (ie, a supporting portion).

[0032] Among them, the conventional method adopted for the silver mirror reflective layer in Comparative Example 1 is to evaporate the silver mirror through a negative photoresist as a mask. The negative photoresist is used as a mask because the photoresist will be connected to the edge of the silver mirror. After the silver mirror is evaporated, when the photoresist is peeled off, the edge of the silver mirror will be lifted, resulting in the breakage of the blue film covering the silver mirror.

[0033] In the LED chip of the second embodiment, the DBR layer is first deposited on the first insulating layer, and then the second insulating layer is formed, and the support portion is formed on the second insulating layer by etching. In this way, the edge of the silver mirror will not be directly connected to the photoresist after evaporation, and thus the silver mirror will not be warped.

[0034] The reflectivity of the LED chips prepared in Example 2 and Comparative Example 1 was tested respectively. The reflectivity of the LED chip in Example 2 can reach 100%, while the reflectivity of the LED chip in Comparative Example 1 is only 95%. Figure 2 (Curve AG is the experimental data of comparative example 1, and curve DBR+AG is the experimental data of embodiment 2).

[0035] In summary, the present invention discloses an LED chip and a brightening method thereof. A MESA structure is first formed, and then wrapped by a first insulating layer. Then, a DBR layer, a second insulating layer and a silver mirror reflecting layer are sequentially formed on the first insulating layer, so that the DBR layer and the silver mirror reflecting layer work together to fully reflect the light from the sapphire substrate, thereby enhancing the reflectivity of the chip, thereby achieving the goal of reducing the number of chips while ensuring that the overall brightness of the package does not decrease. In addition, compared with the prior art, there is no need to reserve sufficient thickness to change the light propagation path to increase the brightness.

[0036] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for brightening an LED chip, characterized in that: The following steps are involved: S1: Etching a MESA structure on the epitaxial layer to expose the N-GaN layer and form positive and negative electrodes; S2: Etching the N-GaN at the edge of the LED chip until an isolation layer is formed on the surface of the sapphire substrate; S3: sputtering an ITO layer on the epitaxial layer, and maintaining a first distance between the ITO layer and the MESA structure; S4: forming a first insulating layer along the edge of the MESA structure so that the first insulating layer covers the MESA structure; S5: forming a DBR layer, a second insulating layer and a silver mirror reflection layer in sequence on the first insulating layer.

2. A method for brightening an LED chip according to claim 1, characterized in that: The step S5 comprises the following steps: S51: evaporating a DBR layer on the first insulating layer; S52: etching a current through hole on the DBR layer; S53: depositing a second insulating layer on the DBR layer.

3. A method for brightening an LED chip according to claim 2, characterized in that: The step S5 further comprises the following steps: S54: forming a silver mirror reflection layer on the second insulating layer.

4. A method for brightening an LED chip according to claim 3, characterized in that: The specific steps of step S54 are to coat photoresist on the second insulating layer and expose and develop to form a corresponding pattern, etch a part of the second insulating layer to form a supporting portion of the second insulating layer, and evaporate on the supporting portion to form a silver mirror reflective layer.

5. A method for brightening an LED chip according to claim 4, characterized in that: The photoresist is a negative photoresist.

6. A method for brightening an LED chip according to claim 4, characterized in that: In the step S54, the second insulating layer is corroded by a BOE solution; The BOE solution includes ammonium fluoride and hydrogen fluoride, and the ratio of ammonium fluoride to hydrogen fluoride is (10-12): (0.5-2).

7. The method for brightening an LED chip according to claim 4, characterized in that: The etching depth of the second insulating layer is at most one half of the thickness of the second insulating layer.

8. The method for brightening an LED chip according to claim 2, characterized in that: In the step S52 , the current via penetrates through the DBR layer and penetrates into the first insulating layer.

9. The method for brightening an LED chip according to claim 2, characterized in that: The DBR layer is formed by alternately evaporating SIO2 and Ti3O5 according to a preset thickness.

10. An LED chip, manufactured by the LED chip brightening method according to any one of claims 1 to 9, characterized in that: The invention comprises a sapphire substrate, an epitaxial layer, a first insulating layer, a DBR layer, a second insulating layer and a silver mirror reflecting layer which are sequentially stacked from bottom to top.

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