Light emitting diode and light emitting device

Abstract

The invention provides a light emitting diode, which comprises a semiconductor lamination layer, a first semiconductor layer, an active layer and a second semiconductor layer, the transparent conducting layer is formed on the second semiconductor layer; a first pad electrode formed on the first semiconductor layer and electrically connected to the first semiconductor layer; a second pad electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer; wherein the distance between the transparent conductive layer and the second semiconductor layer is 0.5-3 [mu] m, and the distances between the transparent conductive layer and the second semiconductor layer are equal everywhere.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a light emitting diode and a light emitting device. Background Art

[0002] Light-emitting diodes are used in a variety of products such as large backlight units (BLUs), general lighting, and electronic devices, as well as various small home appliances and interior decoration products. Furthermore, light-emitting diodes are not only used as light sources, but also can be used for various purposes such as conveying information and evoking beauty. Summary of the invention

[0003] The present application provides a light-emitting diode, comprising a semiconductor stack, including a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence; a transparent conductive layer formed on the second semiconductor layer; a first pad electrode formed on the first semiconductor layer and electrically connected to the first semiconductor layer; a second pad electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer; wherein the distance between the transparent conductive layer and the second semiconductor layer is between 0.5 and 3 μm, and the distance between the transparent conductive layer and the second semiconductor layer is equal everywhere.

[0004] The present application also provides a light-emitting diode, comprising: a semiconductor stack, comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence; a transparent conductive layer formed on the second semiconductor layer; a first pad electrode formed on the first semiconductor layer and electrically connected to the first semiconductor layer; a second pad electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer; wherein the surface of the second semiconductor layer comprises a first edge, a second edge, and a first corner connecting the first edge and the second edge, and the projection of the first pad electrode on the semiconductor stack covers the projection of the first corner on the semiconductor stack; the fillet radius of the first corner is ≥2.5 μm, the distance between the first corner and the transparent conductive layer is a first distance D1, the distance between the first edge or the second edge and the transparent conductive layer is a second distance D2, and D1 is between 75%D2 and 125%D2.

[0005] The present application also provides a light-emitting device, comprising: a substrate; a plurality of light-emitting diodes, wherein the light-emitting diodes are formed on the substrate; and a packaging layer, covering the light-emitting diodes, wherein the light-emitting diodes are the light-emitting diodes described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic top view of a light emitting diode chip for illustrating an embodiment of the present invention; Figure 2 is a schematic top view of a light emitting diode chip for illustrating an embodiment of the present invention; Figure 3 for Figure 2 Enlarged schematic diagram of region I, region II, and region III; Figure 4 is along Figure 1 Schematic cross-section diagram; Figure 5 is a schematic top view of a light emitting diode chip for illustrating another embodiment of the present invention; Figure 6 for Figure 5 Enlarged schematic diagram of area IV, area V, and area VI Figure 7 is a schematic structural diagram of a light emitting device in an embodiment of the present invention; Figure 8 It is a schematic top view of a light emitting diode chip in the prior art. Specific embodiments

[0007] In order to make the description more concise, the projections described below are all projections in the third direction Z with the semiconductor stack as the reference plane.

[0008] Figure 1 and Figure 2 is a schematic top view of a light emitting diode chip for illustrating an embodiment of the present invention. Figure 3 for Figure 2 Enlarged schematic diagram of region I, region II, and region III; Figure 4 is along Figure 1 Schematic cross-section diagram.

[0009] like Figure 1 and Figure 4 As shown, the light emitting diode chip of this embodiment includes a substrate 110 , a semiconductor stack 120 , a transparent conductive layer 130 , a first contact electrode 141 , a second contact electrode 142 , an insulating layer 150 , a first pad electrode 161 , and a second pad electrode 162 .

[0010] The substrate 110 may be an insulating substrate or a conductive substrate. The substrate 110 may be a growth substrate for growing the semiconductor stack 120, and may include a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, etc. In addition, the substrate 110 may include a plurality of protrusions formed on at least a portion of its upper surface. The plurality of protrusions of the substrate 110 may be formed into a regular or irregular pattern. For example, the substrate 110 may be a patterned sapphire substrate (Patterned sapphire substrate, PSS) including a plurality of protrusions formed on the upper surface. The substrate 110 may have a thickness in the range of approximately 100 μm to 200 μm.

[0011] like Figure 2 As shown, the substrate 110 has a first edge Y1, a second edge Y2, a third edge Y3 and a fourth edge Y4 connected in sequence. The edge of the substrate 110 may be equivalent to the edge of the light emitting diode. The first edge Y1 and the third edge Y3 extend along the first direction X, and the second edge Y2 and the fourth edge Y4 extend along the second direction Y. The thickness direction of the substrate 110 is the third direction Z.

[0012] The semiconductor stack 120 is located on the substrate 110. In addition, the area of ​​the lower surface of the semiconductor stack 120 may be smaller than the area of ​​the upper surface of the substrate 110, and the upper surface of the substrate 110 may be exposed along the outer edge of the semiconductor stack 120. A portion of the multiple protrusions (not shown) on the upper surface of the substrate 110 is located between the semiconductor stack 120 and the substrate 110, and the multiple protrusions (not shown) not covered by the semiconductor stack 120 are exposed at the periphery of the semiconductor stack 120.

[0013] The semiconductor stack 120 includes a first semiconductor layer 121, a second semiconductor layer 123 on the first semiconductor layer 121, and an active layer 122 between the first semiconductor layer 121 and the second semiconductor layer 123, which are sequentially stacked in the third direction Z of the substrate 110. The overall thickness of the semiconductor stack 120 may be approximately in the range of 3 μm to 10 μm.

[0014] The first semiconductor layer 121, the active layer 122 and the second semiconductor layer 123 may include III-V series nitride semiconductors, for example, nitride semiconductors such as (Al, Ga, In)N. The first semiconductor layer 121 may include n-type impurities (for example, Si, Ge, Sn), and the second semiconductor layer 123 may include p-type impurities (for example, Mg, Sr, Ba). In addition, the opposite may also be true. The active layer 122 may include a multi-layer quantum well structure (MQW), which can adjust the composition ratio of the nitride semiconductor in a manner to emit a desired wavelength. In particular, in the present embodiment, the second semiconductor layer 123 may be a p-type semiconductor layer.

[0015] Among them, Figure 2 As shown, the surface of the second semiconductor layer 123 includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4 connected in sequence, a first corner C1 connecting the first edge E1 and the second edge E2, a second corner C2 connecting the second edge E2 and the third edge E3, a third corner C3 connecting the third edge E3 and the fourth edge E4, and a first corner C4 connecting the fourth edge E4 and the first edge E1.

[0016] The first side E1 and the third side E3 extend along the first direction X, and the second side E2 and the fourth side E4 extend along the second direction Y. In one embodiment, the second side E2 is composed of multiple curved lines, which can be considered as extending along the second direction Y. The first side E1, the third side E3 and the fourth side E4 are composed of straight lines.

[0017] The semiconductor stack 120 includes a mesa M that exposes a portion of the surface of the first semiconductor layer 121. Specifically, the semiconductor stack 120 can remove the second semiconductor layer 123, the active layer 122, and a portion of the first semiconductor layer 121 through a process such as etching to form a mesa M that exposes a portion of the surface of the first semiconductor layer 121. The mesa M may be located outside the second semiconductor layer 123 and surround the second semiconductor layer 123. In another embodiment, a mesa M (through hole or through groove) may also be formed inside the semiconductor stack 120 to expose a portion of the surface of the first semiconductor layer 121.

[0018] The mesa M includes a first region M1 and a second region M2. The first region M1 is distributed along the first side E1, the third side E3 and the fourth side E4, and the second region M2 is distributed along the second side E2.

[0019] like Figure 1 and Figure 4As shown, the transparent conductive layer 130 is located on the second semiconductor layer 123. The transparent conductive layer 130 may be in ohmic contact with the second semiconductor layer 123. The transparent conductive layer 130 may include, for example, a light-transmitting conductive oxide layer such as indium tin oxide (ITO), zinc oxide (ZnO), zinc indium tin oxide (ZITO), zinc indium oxide (ZIO), zinc tin oxide (ZTO), gallium indium tin oxide (GITO), gallium indium oxide (GIO), gallium zinc oxide (GZO), aluminum doped zinc oxide (AZO), fluorine tin oxide (FTO), etc. The conductive oxide may also include various dopants.

[0020] In this embodiment, the thickness of the transparent conductive layer 130 is between 50nm and 200nm. The size of the light emitting diode is less than 300μm*150μm. If the thickness of the transparent conductive layer is less than 50nm, the current may not be able to spread, resulting in the light emitting diode not being able to obtain good ESD capability. If the thickness of the transparent conductive layer 130 is greater than 200nm, the transparent conductive layer 130 will absorb light and cause loss.

[0021] The first contact electrode 141 is formed on the first semiconductor layer 121, specifically, the first contact electrode 141 is formed on the second region M2. The first contact electrode 141 ohmically contacts the first semiconductor layer 121 and disperses current. To this end, the first contact electrode 141 includes a metal layer that ohmically contacts the first semiconductor layer 121.

[0022] In one embodiment, the first contact electrode 141 may be formed in the second region M2 in a block form.

[0023] The first contact electrode 141 does not overlap with the active layer 122 or the second semiconductor layer 123 of the mesa M, so the insulating layer used to insulate the first contact electrode 141 from the second semiconductor layer 123 is omitted. The first contact electrode 141 can be formed, for example, by a lift-off process to the semiconductor stack 120 having the transparent conductive layer 130 formed thereon. At this time, the second contact electrode 142 described below can also be formed at the same time.

[0024] The second contact electrode 142 is located on the transparent conductive layer 130 and is electrically connected to the transparent conductive layer 130 , thereby facilitating current dispersion in the second semiconductor layer 123 .

[0025] The second contact electrode 142 may include a connecting portion 142 c and an extending portion 142 b extending from the connecting portion 142 c .

[0026] In order to reduce light absorption caused by the second contact electrode 142, the second contact electrode 142 is limitedly formed on a portion of the transparent conductive layer 130. The entire area of ​​the second contact electrode 142 does not exceed 2 / 10 of the area of ​​the transparent conductive layer 130. The second contact electrode 142 may include a starting portion 142a, an extending portion 142b, and a connecting portion 142c connecting the starting portion 142a and the extending portion 142b.

[0027] The extension portion 142b has a width wider than the starting portion 142a and the connecting portion 142c, and the starting portion 142a has a width wider than the connecting portion 142c. In order to disperse the current, the extension portion 142b may have various shapes.

[0028] The first contact electrode 141 and the second contact electrode 142 may be formed together using the same material in the same process, and thus may have the same layer structure. For example, the first contact electrode 141 and the second contact electrode 142 may include an Al reflective layer, and may include Au. Specifically, the first contact electrode 141 and the second contact electrode 142 may have a layer structure of Cr / Al / Ti / Ni / Ti / Ni / Au / Ti. In another embodiment, in order to reduce costs, the first contact electrode 141 and the second contact electrode 142 may also not include Au.

[0029] The insulating layer 150 is formed on the semiconductor stack 120. Specifically, the insulating layer 150 may cover the semiconductor stack 120, the transparent conductive layer 130, the first contact electrode 141, and the second contact electrode 142. The insulating layer 150 has a first opening OP1 and a second opening OP2. The first opening OP1 exposes a portion of the surface of the first contact electrode 141, and the second opening OP2 exposes a portion of the surface of the second contact electrode 142, wherein the second opening OP2 exposes a portion of the surface of the starting portion 142a of the second contact electrode 142. The size of the first opening OP1 is smaller than the area of ​​the first contact electrode 141, and the size of the second opening OP2 is smaller than the area of ​​the starting portion 142a of the second contact electrode.

[0030] The insulating layer 150 includes a distributed Bragg reflector. The distributed Bragg reflector may be formed by repeatedly laminating dielectric layers with different refractive indices, and the dielectric layers may include TiO2, SiO2, HfO2, ZrO2, Nb2O5, MgF2, etc. For example, the insulating layer 150 may have a structure of alternately laminated TiO2 layers / SiO2 layers. The distributed Bragg reflector is made in a manner of reflecting light generated in the active layer 122, and multiple pairs are formed to improve the reflectivity. In this embodiment, the distributed Bragg reflector may include 10 to 25 pairs. The insulating layer 150 may include another insulating layer together with the distributed Bragg reflector. For example, in order to improve the adhesion between the distributed Bragg reflector and its underlying layer, it may include an interface layer located at the bottom of the distributed Bragg reflector and a protective layer covering the distributed Bragg reflector. The interface layer may be formed, for example, of a SiO2 layer, and the protective layer may be formed of SiNx. The layer formed of SiNx has excellent moisture resistance, thereby protecting the light-emitting diode chip from moisture.

[0031] The insulating layer 150 may have a thickness of about 2 μm to 5 μm. The reflectivity of the distributed Bragg reflector to the light generated in the active layer 122 may be above 90%, and a reflectivity close to 100% may be provided by controlling the type, thickness, and stacking period of the plurality of dielectric layers forming the distributed Bragg reflector. Furthermore, the distributed Bragg reflector may also have a high reflectivity to other visible light other than the light generated in the active layer 122.

[0032] The first pad electrode 161 and the second pad electrode 162 are located on the insulating layer 150 . The first pad electrode 161 contacts the first contact electrode 141 through the first opening OP1 , thereby being electrically connected to the first semiconductor layer 121 . The second pad electrode 162 contacts the second contact electrode 142 through the second opening OP2 , thereby being electrically connected to the second semiconductor layer 123 .

[0033] The first pad electrode 161 and the second pad electrode 162 can be formed together using the same material in the same process, and thus can have the same layer structure. The thickness of the first pad electrode 161 and the second pad electrode 162 can be thinner than the thickness of the insulating layer 150, for example, can be formed to a thickness of about 2 μm. The thickness of the first pad electrode 161 and the second pad electrode 162 can also be thicker than the thickness of the insulating layer 150, The first pad electrode 161 and the second pad electrode 162 are arranged along the first direction X.

[0034] In one embodiment, if Figure 1As shown, the projection of the first pad electrode 161 covers the projection of the first corner C1 and the projection of the second corner C2, and the projection of the second pad electrode 162 covers the projection of the third corner C2 and the projection of the fourth corner C4. Specifically, the projection of the first pad electrode 161 covers the second side E2, and part of the projection of the first side E1 and the third side E3, and the projection of the second pad electrode 162 covers the fourth side E4, and part of the projection of the first side E1 and the third side E3. In this way, the surface area of ​​the first pad electrode 161 and the second pad electrode 162 can be increased, and the thrust of the first pad electrode 161 and the second pad electrode 162 in the subsequent crystal bonding process can be greatly improved, that is, the bonding force between the first pad electrode 161 and the second pad electrode 162 and the crystal bonding substrate is increased, which can prevent and avoid the light-emitting element from falling off from the substrate, and improve reliability.

[0035] In one embodiment, if Figure 1 As shown, the first pad electrode 161 has a first long side 161a, a first short side 161b, a second long side 161c and a second short side 161d connected in sequence, and the extension direction of the first short side 161b and the second short side 161d is consistent with the extension direction of the first side E1 of the second semiconductor layer (first direction X), and the extension direction of the first long side 161a is consistent with the extension direction of the second side E2 of the second semiconductor layer (second direction Y). The first long side 161a, the first short side 161b and the second short side 161d of the first pad electrode 161 are projected within the mesa M. Similarly, the first long side, the first short side and the second short side of the second pad electrode 162 are projected within the mesa M. Among them, the second long side 161c of the first pad electrode 161 and the second long side projection on the semiconductor stack 120 are located within the second semiconductor layer. Through this design, the first pad electrode 161 and the second pad electrode 162 will not extend to the area of ​​the substrate 110 that is not covered by the semiconductor stack 120. Therefore, during the cutting process of the light-emitting diode, the area where the insulating layer 150 is cracked in the area of ​​the substrate 110 not covered by the semiconductor stack 120 will not be blocked by the first pad electrode 161 and the second pad electrode 162. This makes it easier to identify the cracked area in the subsequent AOI inspection, thereby improving the yield of the light-emitting diode and preventing the cracked light-emitting diode from entering the crystal bonding stage. This also prevents the solder paste from entering the cracked area after crystal bonding, causing leakage of the light-emitting diode, which is beneficial to improving the reliability of the device.

[0036] like Figure 8 As shown, Figure 8It is a schematic top view of a light-emitting diode chip in the prior art, wherein the schematic top view ignores the transparent conductive layer and the insulating layer. In the prior art, in order to maximize the light-emitting area of ​​the light-emitting diode, the second mesa region M2 is usually set at a corner between the second edge Y2 and the third edge Y3 of the light-emitting diode. Among them, the overlapping area between the projection of the first pad electrode 161 and the projection of the second semiconductor layer 123 is S1, and the overlapping area between the projection of the first pad electrode 161 and the projection of the first semiconductor layer 121 (the second mesa region M2) is S2, then the overlapping area S1 and the overlapping area S2 on the surface of the first pad electrode 161 are arranged along the second direction Y. As the size of the light-emitting diode is getting smaller and smaller, the size of the light-emitting diode is less than 300μm*150μm, especially the short side is less than 150μm, and the area of ​​the pad electrode will also be limited to become smaller and smaller. Since the area of ​​the pad electrode is limited, and the second mesa region M2 needs to meet the first contact electrode 161 formed on it, the areas of S1 and S2 are approximately equal. However, S1 and S2 of approximately equal area are mainly arranged along the second direction Y. The tension of solid crystal materials such as solder paste will cause the light-emitting diode to be pulled in the second direction Y, making the light-emitting diode very easy to shift or tilt in the second direction Y, thereby greatly affecting the display effect of the client.

[0037] In this application, reference is made to Figure 1 and Figure 2 The second area M2 of the mesa is symmetrical along a virtual center parallel line C, the first contact electrode 141 formed in the second area M2 of the mesa is symmetrical along the virtual center parallel line C, and the first opening OP1 of the insulating layer formed on the first contact electrode 141 and exposing a portion of the surface of the first contact electrode 141 is symmetrical along the virtual center parallel line C. The virtual center parallel line C is parallel to and located in the middle position between the first edge Y1 and the third edge Y3 of the substrate 110, or in other words, the virtual center parallel line C is located in the middle position between the first edge Y1 and the third edge Y3 of the light emitting diode. Figure 1 and Figure 2 As shown, the second mesa region M2 is composed of a portion of the first side X1, the second side X2, a portion of the third side X3 and the extension line of the second long side 161c of the first pad electrode in the second direction of the first semiconductor layer 121. In a preferred embodiment, the light emitting diode is symmetrical along the virtual center parallel line C axis.

[0038] Reference Figure 1 and Figure 2, the overlapping area between the projection of the first pad electrode 161 and the projection of the second semiconductor layer 123 is S1, and the overlapping area between the projection of the first pad electrode 161 and the projection of the first semiconductor layer 121 (table M) is S2. The overlapping area S1 and the overlapping area S2 are generally arranged along the first direction X, and the overlapping area S1 and the overlapping area S2 are symmetrical along the virtual center parallel line C axis. The tension of the solid crystal material such as solder paste in the first direction X is mainly affected by the area of ​​the first pad electrode 161 and the second pad electrode 162 (the first pad electrode 161 and the second pad electrode 162 have equal areas, and the tension is evenly distributed in the first direction X), and will not be affected by the arrangement of the overlapping area S1 and the overlapping area S2 along the first direction X. In the second direction Y, since the overlapping area S1 and the overlapping area S2 are symmetrical along the virtual center parallel line C axis, the tension of the solid crystal material such as solder paste in the second direction Y is evenly distributed, so that the light-emitting diode will not be pulled, so that the light-emitting diode is easily offset or skewed in the second direction Y.

[0039] In one embodiment, referring to Figure 1 and Figure 2 , the area of ​​S1 is smaller than the area of ​​S2. More specifically, the area of ​​S1 / the area of ​​the first pad electrode 161 is less than 40%, the area of ​​S2 / the area of ​​the first pad electrode 161 is greater than 60%, and theoretically the area of ​​the first pad electrode 161=the area of ​​S1+the area of ​​S2. In a preferred embodiment, the area of ​​S1 / the area of ​​the first pad electrode 161 is less than 30%, and the area of ​​S2 / the area of ​​the first pad electrode 161 is greater than 70%. By controlling S1 to be much smaller than S2 and avoiding S1 and S2 to be roughly equal, the probability of the light-emitting diode being offset or skewed can be reduced. Among them, if the size of the light-emitting diode is greater than 300μm*150μm, controlling S1 to be greater than S2 can also reduce the probability of the light-emitting diode being offset or skewed. However, the size of the light-emitting diode in this application is limited (the size is less than 300μm*150μm). If S1 is controlled to be greater than S2, the area of ​​the first contact electrode 161 is too small, which is not conducive to forming an ohmic contact.

[0040] In one embodiment, referring to Figure 1 and Figure 2, the fillet radius of the first corner C1 or the second corner C2 is greater than 2μm. The first corner C1 of the second semiconductor layer 123 has an extension line A perpendicular to the first short side 161b of the first electrode, and the extension line A has a minimum distance from the first long side 161a of the first pad electrode 161. The extension line A overlaps with the first contact electrode 141, and the extension line A does not overlap with the first opening OP1 of the insulating layer. Due to the limitation of the short side of the light-emitting diode, in the embodiment of the present application, the short side of the light-emitting diode is less than 150nm, and it is necessary to ensure that the extension line A overlaps with the first contact electrode 141, the extension line A does not overlap with the first opening OP1 of the insulating layer, and the fillet radius of the first corner C1 or the second corner C2 is greater than 2μm, so as to ensure that there is no sharp corner in the first corner C1 or the second corner C2, and to ensure that the current has enough space to diffuse here. If there is a sharp corner in the first corner C1 or the second corner C2, it may cause the ESD capability of the first corner C1 or the second corner C2 to be poor, resulting in a tip leakage effect.

[0041] In one embodiment, referring to Figure 1 and Figure 2 , the transparent conductive layer 130 includes a fifth corner C5 adjacent to the first corner C1 of the second semiconductor layer 123, and the fillet radius of the fifth corner C5 is greater than the fillet radius of 1μm. The fifth corner C5 has an extension line B perpendicular to the first short side 161b of the first electrode, and the extension line B has a minimum distance from the first long side 161a of the first pad electrode 161. The extension line B does not overlap with the first contact electrode 141, and the extension line B does not overlap with the first opening OP1 of the insulating layer. Through this design, although the light-emitting diode is affected by the limitations of the short side, it can also obtain the maximum light-emitting area. At the same time, the first corner C1, the second corner C2 and the fifth corner C5 will not form sharp corners, resulting in poor ESD capability and tip leakage effect.

[0042] In one embodiment, referring to Figure 1 and Figure 2 The minimum distance between the extension line A and the first long side 161a of the first pad electrode is greater than half the length of the first short side 161b of the first pad electrode. The length of the first side E1 of the second semiconductor layer 123 covered by the projection of the first pad electrode is less than half the length of the first short side 161b of the first pad electrode.

[0043] In one embodiment, if Figure 3 As shown, Figure 3 for Figure 2The enlarged schematic diagram of the middle area I, area II, and area III. The distance between the first corner C1 and the transparent conductive layer 130 is the first distance D1, the distance between the first side E1 and the transparent conductive layer 130 is the second distance D2, and the distance between the fourth corner C4 and the transparent conductive layer 130 is the third distance D3. The first distance D1 is greater than the second distance D2, the third distance D3 is greater than the second distance D2, and the third distance D3 is greater than the second distance D2. Among them, D1 is between 1~5μm, and D2 is between 0~4μm. If the second distance is 0, the light-emitting diode may leak electricity, reducing reliability.

[0044] However, since the size of the light-emitting diode is less than 300μm*150μm, the light-emitting area (i.e., the area of ​​the active layer 122, which is equivalent to the area of ​​the second semiconductor layer 123) is also getting smaller and smaller, and the area of ​​the transparent conductive layer 130 formed on the second semiconductor layer 123 is also limited. In order to allow the transparent conductive layer 130 to extend the current as much as possible, on the one hand, the thickness of the transparent conductive layer 130 is increased (the thickness of the transparent conductive layer is controlled to be in the range of 50nm~200nm), and on the other hand, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is made as small as possible to expand the area of ​​the transparent conductive layer 130.

[0045] In one embodiment, if Figure 5 and Figure 6 As shown, Figure 5 FIG. 1 is a schematic top view of a light emitting diode chip for illustrating another embodiment of the present invention. Figure 6 for Figure 5The enlarged schematic diagram of the middle area IV, area V, and area VI. The distance between the transparent conductive layer 130 and the second semiconductor layer 123 is between 0.5 and 3 μm. The distance between the transparent conductive layer 130 and the second semiconductor layer 123 is controlled to be 0.5 to 3 μm, and the area of ​​the transparent conductive layer 130 is increased as much as possible while ensuring that there is a safe distance between the transparent conductive layer 130 and the second semiconductor layer 123, that is, the reliability of the light-emitting diode can be guaranteed. In addition, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere. Especially at the corners (the first corner C1, the second corner C2, the third corner C3 or the fourth corner C4), for example, the first distance D1 between the first corner C1 and the transparent conductive layer 130, the second distance D2 between the first edge E1 and the transparent conductive layer 130, and the third distance D3 between the fourth corner C4 and the transparent conductive layer 130, the first distance D1 is equal to the second distance D2, and the third distance D3 is equal to the second distance D2. Since the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is in the micron level and there are measuring instrument and manual errors, the first distance D1 is between 75%D2 and 125%D2, and the third distance D3 is between 75%D2 and 125%D2, both of which are the first distance D1 equal to the second distance D2, and the third distance D3 equal to the second distance D2. Similarly, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere, which also satisfies the measurement error within ±25%.

[0046] In order to ensure that the distance between the transparent conductive layer 130 and the second semiconductor layer 123 is equal everywhere, in the present application, the semiconductor stack 120 and the transparent conductive layer 130 use the same yellow light mask, and at the same time, the transparent conductive layer 130 is etched inwardly using the isotropic principle of wet etching, and by controlling the etching time and rate, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 can be controlled to be between 0.5 and 3 μm, and the distance between the transparent conductive layer 130 and the second semiconductor layer 123 can be ensured to be equal everywhere. Even at some corners, the distance between the transparent conductive layer 130 and the second semiconductor layer 123 can be ensured to be equal everywhere.

[0047] In one embodiment, if Figure 5 As shown, no current blocking layer (insulating layer) is disposed between the transparent conductive layer 130 and the second semiconductor layer 123 , so that the transparent conductive layer 130 is in full contact with the second semiconductor layer 123 .

[0048] In one embodiment, if Figure 5As shown, the fillet radius of the four corners of the second semiconductor layer 123 is greater than the fillet radius of the four corners of the transparent conductive layer 130. At the same time, it is necessary to ensure that the fillet radius of the four corners of the second semiconductor layer 123 is greater than 2.5 μm, and the fillet radius of the four corners of the transparent conductive layer 130 is greater than 1 μm, otherwise the first corner C1 or the second corner C2 of the second semiconductor layer 123 will have a sharp tip, so that the fifth corner C5 adjacent to the first corner C1 or the sixth corner C6 adjacent to the second corner C2 will have a more extreme tip, so that problems such as tip leakage may occur here.

[0049] In one embodiment, a light emitting device is provided, referring to Figure 7 The light emitting device includes a substrate 10, a plurality of light emitting diodes 20 formed on the substrate 10, and a packaging layer 30 covering the plurality of light emitting diodes 20. The light emitting diodes 20 can be fixed on the substrate 10 by solder paste or the like. The light emitting diodes 20 are the light emitting diodes in the above embodiment, and also have the above technical effects.

Claims

1. A light emitting diode, comprising: A semiconductor stack, comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence; A transparent conductive layer formed on the second semiconductor layer; A first pad electrode, formed on the first semiconductor layer and electrically connected to the first semiconductor layer; A second pad electrode is formed on the second semiconductor layer and is electrically connected to the second semiconductor layer; The distance between the transparent conductive layer and the second semiconductor layer is between 0.5 μm and 3 μm, and the distance between the transparent conductive layer and the second semiconductor layer is equal everywhere.

2. The light emitting diode according to claim 1, characterized in that: The surface of the second semiconductor layer includes a first edge, a second edge, and a first corner connecting the first edge and the second edge, the projection of the first pad electrode on the semiconductor stack covers the projection of the first corner on the semiconductor stack, the transparent conductive layer includes a fifth corner adjacent to the first corner, and the fillet radius of the first corner is greater than the fillet radius of the fifth corner.

3. The light emitting diode according to claim 2, characterized in that: The fillet radius of the first corner is ≥2.5 μm, and the fillet radius of the fifth corner is ≥1 μm.

4. The light emitting diode according to claim 1, characterized in that: The transparent conductive layer is in complete contact with the second semiconductor layer.

5. A light emitting diode, comprising: A semiconductor stack, comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence; A transparent conductive layer formed on the second semiconductor layer; A first pad electrode, formed on the first semiconductor layer and electrically connected to the first semiconductor layer; A second pad electrode is formed on the second semiconductor layer and is electrically connected to the second semiconductor layer; The surface of the second semiconductor layer includes a first side, a second side, and a first corner connecting the first side and the second side, and the projection of the first pad electrode on the semiconductor stack covers the projection of the first corner on the semiconductor stack; The fillet radius of the first corner is ≥2.5 μm, the distance between the first corner and the transparent conductive layer is a first distance D1, the distance between the first side or the second side and the transparent conductive layer is a second distance D2, and D1 is between 75%D2 and 125%D2.

6. The light emitting diode according to claim 5, characterized in that: The D1 is between 0.5 μm and 3 μm, and the D2 is between 0.5 μm and 3 μm.

7. The light emitting diode according to claim 5, characterized in that: The transparent conductive layer includes a fifth corner adjacent to the first corner of the second semiconductor layer, the fillet radius of the fifth corner is ≥1 μm, and the fillet radius of the fifth corner is smaller than the fillet radius of the first corner.

8. The light emitting diode according to any one of claims 1 or 5, characterized in that: The surface of the second semiconductor layer includes a first side, a second side, a third side and a fourth side, and the surface of the second semiconductor layer also includes a first corner connecting the first side and the second side, a second corner connecting the second side and the third side, a third corner connecting the third side and the fourth side, and a fourth corner connecting the fourth side and the first side. The first pad electrode has a first long side, a first short side, a second long side and a second short side connected in sequence, an extension direction of the first short side is consistent with an extension direction of the first side of the second semiconductor layer, and an extension direction of the first long side is consistent with an extension direction of the second side of the second semiconductor layer.

9. The light emitting diode according to claim 8, characterized in that: The projection of the first pad electrode on the semiconductor stack covers the second side and part of the first and third sides on the semiconductor stack, and the projection of the second pad electrode on the semiconductor stack covers the fourth side and part of the first and third sides on the semiconductor stack.

10. The light emitting diode according to claim 8, characterized in that: The projection of the first pad electrode on the semiconductor stack covers the projections of the first corner and the second corner on the semiconductor stack, and the projection of the second pad electrode on the semiconductor stack covers the projections of the third corner and the fourth corner on the semiconductor stack.

11. The light emitting diode according to claim 8, characterized in that: The first corner has an extension line A perpendicular to the first short side and has a minimum distance from the first long side of the first pad electrode, and the extension line A of the first corner overlaps with the first contact electrode.

12. The light emitting diode according to claim 11, characterized in that: The minimum distance between the extension line A and the first long side of the first pad electrode is greater than half the length of the first short side of the first pad electrode.

13. The light emitting diode according to claim 11, characterized in that: The projection of the first pad electrode on the semiconductor stack covers a length of the first side that is less than half of the length of the first short side of the first pad electrode.

14. The light emitting diode according to any one of claims 1 or 5, characterized in that: The light emitting diode comprises a first edge, a second edge, a third edge and a fourth edge which are connected in sequence. The light emitting diode is symmetrical along a central parallel line, and the central parallel line is parallel and located at a middle position between the first edge and the third edge.

15. The light emitting diode according to any one of claims 1 or 5, characterized in that: The thickness of the transparent conductive layer is between 50 and 200 nm.

16. The light emitting diode according to any one of claims 1 or 5, characterized in that: The size of the light emitting diode is less than 300 μm*150 μm.

17. A light emitting device, comprising: substrate; A plurality of light-emitting diodes according to any one of claims 1 or 5, wherein the light-emitting diodes are formed on a substrate; The encapsulation layer covers the light emitting diode.

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