Display device

Abstract

According to the present disclosure, a display device includes: a substrate including a display area and a non-display area; an outer pixel in the display area and in a first direction from an edge of the substrate; a dummy hole in the non-display area and between an edge of the substrate and the outer pixel; and dummy lines in the non-display area and extending in a second direction different from the first direction between the dummy holes. A dummy line is between the first insulating layer and the second insulating layer, and a dummy hole passes through the first insulating layer and the second insulating layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0141512, filed on October 20, 2023, and all benefits obtained from the application, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] As information technology develops, the importance of display devices, which are a connecting medium between users and information, has become prominent. In response to this, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0004] The display device may include a plurality of pixels, and an image may be displayed through the pixels. Each of the pixels may include a plurality of transistors. When hydrogen diffuses into the semiconductor constituting the channel of the transistor, the channel may become conductive and the threshold voltage of the transistor may change. Therefore, there is a problem that it is difficult to display an accurate image. Summary of the invention

[0005] A technical challenge to be addressed is to provide a display device capable of preventing hydrogen diffusion into the transistor channel.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate including a display area and a non-display area; an outer pixel located in the display area and located in a first direction from an edge of the substrate; a dummy hole located in the non-display area and located between the edge of the substrate and the outer pixel; and a dummy line located in the non-display area and extending between the dummy holes in a second direction different from the first direction. The dummy line is located between a first insulating layer and a second insulating layer, and the dummy hole passes through the first insulating layer and the second insulating layer.

[0007] The display device may further include: a third insulating layer on the second insulating layer, and the dummy hole may include a portion of the third insulating layer therein.

[0008] The dummy holes may not include electrode material therein.

[0009] One end of the dummy line may be connected to the first power line in a region adjacent to the first corner of the substrate, and the other end of the dummy line may be connected to the first power line in a region adjacent to the second corner of the substrate.

[0010] The rest of the dummy line except for one end of the dummy line and the other end of the dummy line may not be connected to the first power line.

[0011] The first electric force line may be located between an edge of the substrate and a dummy hole closest to the edge among the dummy holes, and may extend in the second direction.

[0012] Each of the outer pixels may include a transistor, and at least one of the transistors may be an oxide semiconductor transistor.

[0013] The oxide semiconductor transistor may be a transistor located closest to an edge of the substrate among the plurality of transistors.

[0014] The scan line connected to the oxide semiconductor transistor may be located in the same electrode layer as the dummy line.

[0015] The oxide semiconductor transistor may be further connected to a sub-scan line overlapping the scan line.

[0016] According to an embodiment of the present disclosure, a display device includes: a substrate including a display area and a non-display area; an outer pixel located in the display area and located in a first direction from an edge of the substrate; and a dummy line located in the non-display area and extending in a second direction different from the first direction between the edge of the substrate and the outer pixel. Each of the outer pixels includes a plurality of transistors including at least one oxide semiconductor transistor, the oxide semiconductor transistor being a transistor located closest to the edge of the substrate among the plurality of transistors, and a scan line connected to the oxide semiconductor transistor and the dummy line are located in the same electrode layer.

[0017] A vertical distance between a scan line connected to the oxide semiconductor transistor and the substrate may be a maximum vertical distance among vertical distances between scan lines connected to the outer pixels and the substrate.

[0018] The oxide semiconductor transistor may be further connected to a sub-scan line, and the sub-scan line may be positioned to vertically overlap between the substrate and the scan line.

[0019] The display device may further include: a dummy hole located in the non-display area and between an edge of the substrate and the outer pixel.

[0020] The dummy line may be extended so as not to vertically overlap the dummy hole.

[0021] The dummy line may be located between the first insulating layer and the second insulating layer, and the dummy hole may pass through the first insulating layer and the second insulating layer.

[0022] The display device may further include: a third insulating layer on the second insulating layer, and the dummy hole may include a portion of the third insulating layer therein.

[0023] The dummy holes may not include electrode material therein.

[0024] One end of the dummy line may be connected to the first power line in a region adjacent to the first corner of the substrate, and the other end of the dummy line may be connected to the first power line in a region adjacent to the second corner of the substrate.

[0025] The first electric force line may be located between an edge of the substrate and a dummy hole closest to the edge among the dummy holes, and may extend in the second direction.

[0026] The display device according to the present disclosure can prevent hydrogen from diffusing into a transistor channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in further detail with reference to the accompanying drawings.

[0028] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0030] Figure 3 It is a graphic driver Figure 2 Pixel method diagram.

[0031] Figure 4A , Figure 4B and Figure 4C is a diagram illustrating a structure of a display panel according to an embodiment of the present disclosure.

[0032] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 is a diagram illustrating a first region of a pixel unit according to an embodiment of the present disclosure.

[0033] Fig.15A and Fig. 15B is a cross-sectional view of a non-display area and a display area according to an embodiment of the present disclosure.

[0034] Fig.16 is a diagram illustrating a second region of a pixel unit according to an embodiment of the present disclosure.

[0035] Fig.17 is a diagram illustrating a third region of a pixel unit according to an embodiment of the present disclosure.

[0036] Fig.18 and Fig.19is a diagram illustrating the effect of preventing hydrogen diffusion according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0038] In order to clearly describe the present disclosure, parts not related to the description are omitted, and the same or similar elements are represented by the same reference numerals throughout the specification. Therefore, reference numerals in one figure may be used in other figures.

[0039] In addition, for the convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore the present disclosure is not necessarily limited to the size and thickness shown in the drawings. In the drawings, the thickness may be exaggerated to clearly indicate different layers and regions.

[0040] In addition, the expression "same" in the specification may mean "substantially the same". That is, the expression "same" may be sufficiently identical to be understood by ordinary technicians as being identical. Other expressions may also be expressions in which "substantially" is omitted.

[0041] Figure 1 is a diagram illustrating a display device 10 according to an embodiment of the present disclosure.

[0042] refer to Figure 1 , the display device 10 according to an embodiment of the present disclosure may include a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel unit 14 , and an emission driver 15 .

[0043] The timing controller 11 may receive the grayscale of the input image (or input frame). The grayscale may include a first color grayscale, a second color grayscale, and a third color grayscale. The first color grayscale may be a grayscale for representing a first color, the second color grayscale may be a grayscale for representing a second color, and the third color grayscale may be a grayscale for representing a third color.

[0044] In addition, the timing controller 11 can receive a control signal for an image. Such control signals may include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync) and a data enable signal. The vertical synchronization signal may include a plurality of pulses, and may indicate that the previous frame period ends and the current frame period begins based on the time point at which each of the pulses is generated. The interval between adjacent pulses of the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include a plurality of pulses, and may indicate that the previous horizontal period ends and the new horizontal period begins based on the time point at which each of the pulses is generated. The interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may have an enable level in a specific horizontal period and a disable level in the remaining period. When the data enable signal is at an enable level, the data enable signal may indicate that a color grayscale is supplied in the corresponding horizontal period.

[0045] The timing controller 11 may provide a clock signal and a grayscale rendered or corrected to correspond to the specification of the display device 10 to the data driver 12. In addition, the timing controller 11 may provide a clock signal and a scan start signal to the scan driver 13. The timing controller 11 may provide a clock signal and an emission stop signal to the emission driver 15.

[0046] The data driver 12 may generate a data voltage VD to be supplied to the data line using the grayscale and the clock signal received from the timing controller 11. For example, the data driver 12 may sample the grayscale using the clock signal and apply the data voltage VD corresponding to the grayscale to the data line in units of pixel rows. A pixel row refers to pixels connected to the same scan line. The data line may extend in a first direction DR1 in the pixel unit 14. The data lines may be arranged parallel to each other in a second direction DR2 perpendicular to the first direction DR1.

[0047] The scan driver 13 may receive a clock signal and a scan start signal from the timing controller 11 to generate a scan signal SC to be provided to the scan line. The scan driver 13 may sequentially provide the scan signal SC having a pulse of an on level to the scan line. For example, the scan driver 13 may be constructed in the form of a shift register, and may generate the scan signal SC by sequentially transmitting the scan start signal in the form of a pulse of an on level to the next stage circuit under the control of the clock signal.

[0048] The scan driver 13 may include a plurality of sub-scan drivers according to the type of the scan signal SC. At this time, each of the plurality of sub-scan drivers may be constructed in the form of a shift register. The scan lines may extend in the second direction DR2 in the pixel unit 14. The scan lines may be arranged parallel to each other in the first direction DR1.

[0049] The emission driver 15 may receive a clock signal and an emission stop signal, etc. from the timing controller 11 to generate an emission signal EC to be provided to the emission line. The emission driver 15 may sequentially provide the emission signal EC having a pulse of a cut-off level to the emission line. For example, the emission driver 15 may be constructed in the form of a shift register, and may generate the emission signal EC in a method of transmitting an emission stop signal in the form of a pulse of a cut-off level to a next-stage circuit under the control of a clock signal. The emission line may extend in the second direction DR2 in the pixel unit 14. The emission lines may be arranged parallel to each other in the first direction DR1.

[0050] The pixel unit 14 may include a first pixel emitting light of a first color, a second pixel emitting light of a second color, and a third pixel emitting light of a third color. The first color, the second color, and the third color may be different colors. For example, the first color may be one of red, green, and blue, the second color may be one of red, green, and blue except the first color, and the third color may be one of red, green, and blue except the first color and the second color. In addition, magenta, cyan, and yellow may be used instead of red, green, and blue as the first to third colors.

[0051] The pixels PXij of the pixel unit 14 may be arranged in a diamond shape, for example. RGB stripe, S stripe, RealRGB and normal of various shapes.

[0052] The pixels PXij of the pixel unit 14 may be located on a plane defined by the first direction DR1 and the second direction DR2. The emission direction may be a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2.

[0053] Figure 2 is a diagram illustrating a pixel PXij according to an embodiment of the present disclosure.

[0054] refer to Figure 2, the pixel PXij may include a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC includes transistors T1, T2, T3, T4, T5, T6, T7 and T8 and a storage capacitor Cst. The pixel PXij may refer to a pixel connected to the i-th first scan line (hereinafter also referred to as the first scan line) GWi and the j-th data line (hereinafter also referred to as the data line) VDj. Each of i and j may be an integer greater than 0. The second scan line GCi, the third scan line GIi, the fourth scan line GBi and the emission line EMi may be the i-th line. In an embodiment, at least one of the second scan line GCi, the third scan line GIi, the fourth scan line GBi and the emission line EMi may not be the i-th line. For example, adjacent pixel rows may share an emission line. In this case, the number of emission lines becomes less than the number of first scan lines.

[0055] Here, the pixel PXij may be a first pixel for expressing a first color. Since the second pixel for expressing a second color and the third pixel for expressing a third color may also be configured in the same manner as the first pixel, repeated description is omitted.

[0056] In the present embodiment, the P-type transistor may be a polycrystalline silicon semiconductor transistor. In the polycrystalline silicon semiconductor transistor, the channel of the active layer may include a polycrystalline silicon semiconductor. For example, the polycrystalline silicon semiconductor transistor may be a low temperature polycrystalline silicon (LTPS) thin film transistor. The polycrystalline silicon semiconductor transistor has high electron mobility and therefore has fast driving characteristics.

[0057] In the present embodiment, the N-type transistor may be an oxide semiconductor transistor. In the oxide semiconductor transistor, the channel of the active layer may include an oxide semiconductor. For example, the oxide semiconductor transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. The oxide semiconductor transistor has a charge mobility lower than that of a polycrystalline silicon semiconductor transistor. Therefore, the amount of leakage current generated in the off state of the oxide semiconductor transistor may be less than the amount of leakage current of the polycrystalline silicon semiconductor transistor.

[0058] The gate electrode of the first transistor T1 may be connected to the first node N1, the first electrode may be connected to the second node N2, and the second electrode may be connected to the third node N3. The first transistor T1 may further include a sub-gate electrode (or a back-gate electrode). The sub-gate electrode may receive the first power voltage ELVDD. The first transistor T1 may be a driving transistor. The first transistor T1 may be a P-type transistor.

[0059] The gate electrode of the second transistor T2 may be connected to the first scan line GWi, the first electrode may be connected to the data line VDj, and the second electrode may be connected to the second node N2. The second transistor T2 may be a scan transistor. The second transistor T2 may be a P-type transistor.

[0060] The gate electrode of the third transistor T3 may be connected to the second scan line GCi, the first electrode may be connected to the first node N1, and the second electrode may be connected to the third node N3. The third transistor T3 may be a diode-connected transistor. The third transistor T3 may be an N-type transistor. The third transistor T3 may further include a sub-gate electrode (or a back gate electrode).

[0061] The gate electrode of the fourth transistor T4 can be connected to the third scan line GIi, the first electrode can be connected to the first node N1, and the second electrode can receive the first initialization voltage VINT. The fourth transistor T4 can be a gate initialization transistor. The fourth transistor T4 can be an N-type transistor. The fourth transistor T4 can further include a sub-gate electrode (or a back gate electrode).

[0062] A gate electrode of the fifth transistor T5 may be connected to the emission line EMi, a first electrode may receive the first power voltage ELVDD, and a second electrode may be connected to the second node N2. The fifth transistor T5 may be a first emission control transistor. The fifth transistor T5 may be a P-type transistor.

[0063] A gate electrode of the sixth transistor T6 may be connected to the emission line EMi, a first electrode may be connected to the third node N3, and a second electrode may be connected to the fourth node N4. The sixth transistor T6 may be a second emission control transistor. The sixth transistor T6 may be a P-type transistor.

[0064] The gate electrode of the seventh transistor T7 may be connected to the fourth scan line GBi, the first electrode may receive the second initialization voltage VAINT, and the second electrode may be connected to the fourth node N4. The seventh transistor T7 may be an anode initialization transistor. The seventh transistor T7 may be a P-type transistor.

[0065] A gate electrode of the eighth transistor T8 may be connected to the fourth scan line GBi, a first electrode may receive the bias voltage VOBS, and a second electrode may be connected to the second node N2. The eighth transistor T8 may be a P-type transistor.

[0066] A first electrode of the storage capacitor Cst may receive the first power voltage ELVDD, and a second electrode may be connected to the first node N1.

[0067] The anode of the light emitting element LD can be connected to the fourth node N4, and the cathode can receive the second power voltage ELVSS. The light emitting element LD can emit light of one color of the first color, the second color and the third color. The light emitting element LD can be a light emitting diode. The light emitting element LD can be composed of an organic light emitting diode, an inorganic light emitting diode or a quantum dot / well light emitting diode, etc. In the present embodiment, each pixel PXij is only provided with a light emitting element LD, but in an embodiment, each pixel can be provided with a plurality of light emitting elements. At this time, the plurality of light emitting elements can be connected in series, in parallel, or in series and parallel, etc.

[0068] Figure 3 It is a graphic driver Figure 2 FIG. 1 shows the method for pixels PXij.

[0069] First, an emission signal of a turn-off level (high level) is applied to the emission line EMi, the fifth transistor T5 and the sixth transistor T6 are turned off, and thus the pixel PXij is in a non-emission state.

[0070] Next, a scan signal of a turn-on level (high level) is applied to the third scan line GIi, and thus the fourth transistor T4 is turned on. Accordingly, the first initialization voltage VINT is applied to the first node N1. The first initialization voltage VINT may be a sufficiently low voltage and may bias the first transistor T1 to turn on.

[0071] Next, a scan signal of an on level (high level) is applied to the second scan line GCi, and thus the third transistor T3 is turned on. In addition, a scan signal of an on level (low level) is applied to the first scan line GWi, and thus the second transistor T2 is turned on.

[0072] Therefore, the data voltage of the data line VDj may be applied to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3 in the on state. At this time, the voltage of the first node N1 may be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst may maintain the difference between the first power voltage ELVDD and the compensation voltage.

[0073] Next, a scan signal of a turn-on level (low level) is applied to the fourth scan line GBi, and thus the seventh transistor T7 and the eighth transistor T8 are turned on. Since the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light emitting element LD, and the light emitting element LD can be initialized to a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power voltage ELVSS. Accordingly, the low grayscale expression of the light emitting element LD can be promoted. In addition, since the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS.

[0074] Next, the emission signal of the on level (low level) is applied to the emission line EMi, and thus the fifth transistor T5 and the sixth transistor T6 can be turned on. Accordingly, a path of the driving current flowing from the line of the first power voltage ELVDD to the line of the second power voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6 and the light emitting element LD is formed.

[0075] The amount of driving current may be adjusted according to the voltage held in the storage capacitor Cst. The light emitting element LD emits light having a brightness corresponding to the amount of driving current. The light emitting element LD may emit light until an emission signal of a cut-off level is applied to the emission line EMi.

[0076] FIG. 4A to FIG. 4C is a diagram illustrating a structure of a display panel DP according to an embodiment of the present disclosure.

[0077] Figure 4A is a diagram illustrating a substrate SUB according to an embodiment of the present disclosure. Figure 4B is a diagram illustrating a display panel DP according to an embodiment of the present disclosure.

[0078] The substrate SUB may include a display area DA, a non-display area NDA, a first additional area ADA1, and a second additional area ADA2.

[0079] The display area DA may have a quadrilateral shape such as a rectangular shape. Each corner of the display area DA may have an angled shape or a curved shape. In addition, in the case of a circular display, the display area DA may have a circular shape. In addition, the display area DA may be configured in a shape such as a polygonal shape or an elliptical shape other than the quadrilateral shape. As described above, the shape of the display area DA may be set differently depending on the product.

[0080] The pixels may be located in the display area DA. Depending on the type of the display panel DP, each pixel may include a light emitting diode or a liquid crystal layer.

[0081] The non-display area NDA may surround the display area DA. For example, the non-display area NDA may have a rectangular shape. Each corner of the non-display area NDA may have an angled shape or a curved shape. Figure 4B The non-display area NDA is illustrated under the assumption that each corner of the non-display area NDA has a curved shape. The non-display area NDA may have a circular shape. Since minimizing the non-display area NDA is beneficial to a narrow frame structure, the shape of the non-display area NDA may be similar to that of the display area DA.

[0082] The first additional area ADA1 may be located between the non-display area NDA and the second additional area ADA2. The first additional area ADA1 may be connected to the non-display area NDA at a first boundary ED1. The first additional area ADA1 may be connected to the second additional area ADA2 at a second boundary ED2. Each of the first boundary ED1 and the second boundary ED2 may extend in the second direction DR2.

[0083] The width of the first additional area ADA1 in the second direction DR2 may be narrowed from the first boundary ED1 to the second boundary ED2. That is, the width of the first additional area ADA1 in the second direction DR2 may be narrowed toward the first direction DR1. Accordingly, the first additional area ADA1 may include a curved first side surface RC1 and a second side surface RC2. The side surfaces RC1 and RC2 may protrude toward the inside of the substrate SUB (e.g., the center of the substrate SUB).

[0084] exist Figure 4B , the first additional area ADA1 is shown to include two side surfaces RC1 and RC2 in the second direction DR2 and the opposite direction of the second direction DR2. In an embodiment, because the boundary located in the second direction DR2 coincides with the boundary of the non-display area NDA, the first additional area ADA1 may include only the first side surface RC1. In an embodiment, because the boundary located in the direction opposite to the second direction DR2 coincides with the boundary of the non-display area NDA, the first additional area ADA1 may include only the second side surface RC2.

[0085] The second additional area ADA2 may have a rectangular shape. Each corner of the second additional area ADA2 located in the first direction DR1 may have an angled shape or a curved shape.

[0086] The encapsulation layer TFE may be located on the pixel. For example, the encapsulation layer TFE may cover the pixel in the display area DA, and the boundary of the encapsulation layer TFE may be located in the non-display area NDA. The encapsulation layer TFE may cover the light emitting element and the circuit element of the pixel in the display area DA, thereby preventing damage from external moisture or impact.

[0087] The sensing electrodes SC1 and SC2 may be located on the encapsulation layer TFE. The sensing electrodes SC1 and SC2 may sense the touch, hovering, gesture, proximity, etc. of the user's body. The sensing electrodes SC1 and SC2 may be configured in a form varying according to various types such as resistive, capacitive, electromagnetic (EM), and optical. For example, when the sensing electrodes SC1 and SC2 are configured as capacitive, the sensing electrodes SC1 and SC2 may be configured as self-capacitive or mutual capacitive, etc. In the following, for ease of description, the case where the sensing electrodes SC1 and SC2 are configured as mutual capacitive is described as an example.

[0088] When the sensing electrodes SC1 and SC2 are configured as a mutual capacitance type, a driving signal may be transmitted through a sensing line corresponding to the first sensing electrode SC1, and a sensing signal may be received through a sensing line corresponding to the second sensing electrode SC2 that forms a mutual capacitance with the first sensing electrode SC1. When the user's body approaches, the mutual capacitance between the first sensing electrode SC1 and the second sensing electrode SC2 may change, and whether the user touches may be detected based on the difference in the sensing signal corresponding to the change. In an embodiment, a driving signal may be transmitted through a sensing line corresponding to the second sensing electrode SC2, and a sensing signal may be received through a sensing line corresponding to the first sensing electrode SC1 that forms a mutual capacitance with the second sensing electrode SC2.

[0089] The pads PDE1, PDE2, and PDE3 may be located in the second additional area ADA2. The pads PDE1 and PDE3 may be connected to the sensing electrodes SC1 and SC2 located on the encapsulation layer TFE through the sensing lines IST1 and IST2. The pads PDE1 and PDE3 may be connected to an external touch integrated circuit (IC). In addition, the pad PDE2 may be connected to a pixel or a driver of a pixel located under the encapsulation layer TFE through a display line DST. The driver may include a scan driver, an emission driver, a data driver, and the like. The driver may be located under the encapsulation layer TFE, or may be located on an external display IC connected through the pad PDE2.

[0090] In the case of mutual capacitance type, the touch IC can transmit a driving signal through the first sensing line IST1 and receive a sensing signal through the second sensing line IST2. In an embodiment, a driving signal can be transmitted through the second sensing line IST2, and a sensing signal can be received through the first sensing line IST1. For reference, in the case of self-capacitance type, there may be no difference in the driving method of the first sensing line IST1 and the second sensing line IST2. The display line DST may include a control line, a data line, a power line, etc., and a signal may be provided so that the pixel can display an image. The signal may be provided from a driver connected to the display line DST.

[0091] Figure 4A The substrate SUB is bent, and Figure 4B The substrate SUB is not bent. After the components are stacked on the substrate SUB, the display panel DP can be formed as follows: Figure 4B The substrate SUB shown in FIG. 1 is not bent. Figure 4A is bent as shown in FIG.

[0092] The substrate SUB may include a first bending area BA1 extending from a first side surface RC1 of the first additional area ADA1 to overlap with the non-display area NDA. In addition, the first bending area BA1 may extend to overlap with the display area DA. That is, each of the display area DA, the non-display area NDA, and the first additional area ADA1 may partially overlap with the first bending area BA1. The first bending area BA1 may have a width in the second direction DR2, and a length may extend in the first direction DR1. The first bending axis BX1 may be defined as a folding line extending from the center of the first bending area BA1 in the first direction DR1. According to an embodiment, the first bending area BA1 may be a portion that reduces stress by removing a portion of an insulating layer, etc., differently from other peripheral portions. According to an embodiment, the first bending area BA1 may have the same configuration as other peripheral portions.

[0093] The substrate SUB may include a third bending area BA3 extending from the second side surface RC2 of the first additional area ADA1 to overlap with the non-display area NDA. In addition, the third bending area BA3 may extend to overlap with the display area DA. That is, each of the display area DA, the non-display area NDA and the first additional area ADA1 may partially overlap with the third bending area BA3. The third bending area BA3 may have a width in the second direction DR2, and a length may extend in the first direction DR1. The third bending axis BX3 may be defined as a folding line extending from the center of the third bending area BA3 in the first direction DR1. According to an embodiment, the third bending area BA3 may be a portion that reduces stress by removing a portion of an insulating layer, etc., differently from other peripheral portions. According to an embodiment, the third bending area BA3 may have the same configuration as other peripheral portions.

[0094] The second additional area ADA2 may include a second bending area BA2. The second bending area BA2 may have a width in the first direction DR1, and a length may extend in the second direction DR2. The second bending axis BX2 may be defined as a folding line extending from the center of the second bending area BA2 in the second direction DR2. According to an embodiment, the second bending area BA2 may be a portion that reduces stress by removing a portion of an insulating layer, etc., differently from other peripheral portions. According to an embodiment, the second bending area BA2 may have the same configuration as other peripheral portions.

[0095] The first to third bending areas BA1, BA2, and BA3 may not overlap with each other.

[0096] Here, the term "folding" means that the shape is not fixed, but can be transformed from an original shape to another shape, and can include being folded, bent or curled along one or more bending axes. The side surface frame width of the display panel DP in the second direction DR2 and in the direction opposite to the second direction DR2 can be reduced by the first bending area BA1 and the third bending area BA3. In addition, the side surface frame width of the display panel DP in the first direction DR1 can be reduced by the second bending area BA2.

[0097] Figure 4C is a diagram illustrating a stacked structure of a pixel unit 14 according to an embodiment of the present disclosure.

[0098] refer to Figure 4C The pixel unit 14 may have a structure in which a substrate SUB, a first electrode layer CEL1, a first insulating layer INL1, a first active layer ACL1, a second insulating layer INL2, a second electrode layer CEL2, a third insulating layer INL3, a third electrode layer CEL3, a fourth insulating layer INL4, a second active layer ACL2, a fifth insulating layer INL5, a fourth electrode layer CEL4, a sixth insulating layer INL6, a fifth electrode layer CEL5, a seventh insulating layer INL7 and a sixth electrode layer CEL6 are sequentially stacked.

[0099] The substrate SUB may be formed of various materials such as glass, polymers, and metals. Depending on the application product, the substrate SUB may be selected as one of a rigid substrate and a flexible substrate. When the substrate SUB is configured to include a polymer organic material, the substrate SUB may be composed of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. On the other hand, the substrate SUB may be formed of fiberglass reinforced plastic (FRP).

[0100] The first active layer ACL1 and the second active layer ACL2 may be semiconductor layers. For example, the first active layer ACL1 may be composed of a polysilicon semiconductor, and the second active layer ACL2 may be composed of an oxide semiconductor. The first active layer ACL1 may include channels, first electrodes, and second electrodes of polysilicon semiconductor transistors T1, T2, T5, T6, T7, and T8. The second active layer ACL2 may include channels, first electrodes, and second electrodes of oxide semiconductor transistors T3 and T4. The first electrode and the second electrode of each of the transistors T1 to T8 may be doped with impurities for conduction.

[0101] The first electrode layer CEL1, the second electrode layer CEL2, the third electrode layer CEL3, the fourth electrode layer CEL4, the fifth electrode layer CEL5 and the sixth electrode layer CEL6 may be conductive layers. Each electrode layer may be composed of a single layer or multiple layers and may be composed of known conductors such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and platinum (Pt).

[0102] The first insulating layer INL1, the second insulating layer INL2, the third insulating layer INL3, the fourth insulating layer INL4, the fifth insulating layer INL5, the sixth insulating layer INL6 and the seventh insulating layer INL7 may be inserted to electrically separate the active layers ACL1 and ACL2 from the first to sixth electrode layers CEL1, CEL2, CEL3, CEL4, CEL5 and CEL6. Necessary electrode patterns may be connected to each other through contact holes formed in each of the insulating layers INL1, INL2, INL3, INL4, INL5, INL6 and INL7. The insulating layers INL1, INL2, INL3, INL4, INL5, INL6 and INL7 may be composed of an organic insulating layer, an inorganic insulating layer or an organic / inorganic insulating layer, etc., and may be composed of a single layer or a multilayer. For example, the insulating layers INL1, INL2, INL3, INL4, INL5, INL6 and INL7 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0103] In the following, Figures 5 to 17 , the insulating layers INL1 , INL2 , INL3 , INL4 , INL5 , INL6 , and INL7 are not shown separately.

[0104] Figures 5 to 14is a diagram illustrating a first area AR1 of a pixel unit according to an embodiment of the present disclosure.

[0105] Reference again Figure 4B , the substrate SUB may include a first area AR1, a second area AR2, and a third area AR3. The first area AR1, the second area AR2, and the third area AR3 may be areas located at the edge of the substrate SUB (e.g., an edge located in a direction opposite to the first direction DR1 from the center of the substrate SUB). The first area AR1 may be an area adjacent to a first corner of the substrate SUB, and the third area AR3 may be an area adjacent to a second corner of the substrate SUB. The second area AR2 may be an area located between the first area AR1 and the third area AR3. Pixels located in the first area AR1, the second area AR2, and the third area AR3 may be referred to as outer pixels. The outer pixel may indicate a pixel located at a position closest to the edge of the substrate SUB. For example, the outer pixel may be a pixel having the smallest distance in the first direction DR1 from the edge of the substrate SUB.

[0106] Based on the first area AR1 description Figures 5 to 14 Since the configurations of the second area AR2 and the third area AR3 are similar to that of the first area AR1, repeated descriptions are omitted. Fig.16 and Fig.17 The differences among the first area AR1 , the second area AR2 , and the third area AR3 are described.

[0107] refer to Figure 5 , shows an exemplary pattern of the first electrode layer CEL1. A portion of the pattern of the first electrode layer CEL1 may constitute a sub-gate electrode T1sg of the first transistor T1.

[0108] refer to Figure 6 , shows an exemplary pattern of the first active layer ACL1. The first active layer ACL1 may include channels T1c, T2c, T5c, T6c, T7c, and T8c of transistors T1, T2, T5, T6, T7, and T8. Each of the spaced-apart portions of the first active layer ACL1 with the channel therebetween may constitute a first electrode and a second electrode of the transistors T1, T2, T5, T6, T7, and T8.

[0109] refer to Figure 7, shows an exemplary pattern of the second electrode layer CEL2. The second electrode layer CEL2 may include gate electrodes T1g, T2g, T5g, T6g, T7g, and T8g of transistors T1, T2, T5, T6, T7, and T8. The gate electrodes T1g, T2g, T5g, T6g, T7g, and T8g may overlap with channels T1c, T2c, T5c, T6c, T7c, and T8c, respectively, in the third direction DR3.

[0110] In addition, some patterns of the second electrode layer CEL2 may constitute the first scan line GWi, the fourth scan line GBi, the first initialization line VINTL, and the second electrode Cst2e of the storage capacitor Cst. The first initialization voltage VINT may be applied to the first initialization line VINTL.

[0111] refer to Figure 8 , shows an exemplary pattern of the third electrode layer CEL3. Some patterns of the third electrode layer CEL3 may constitute the third-a scan line GIia and the first electrode Cst1e of the storage capacitor Cst. The third-a scan line GIia may be a sub-scan line connected to the fourth transistor T4. The sub-scan line may be connected to the sub-gate electrode (or back gate electrode) of the fourth transistor T4. The third-a scan line GIia is similar to the one referenced later. Fig.10 The third-b scanning line GIib described may constitute a reference Figure 2 Described third scan line GIi.

[0112] refer to Fig. 9 , shows an exemplary pattern of the second active layer ACL2. The second active layer ACL2 may include channels T3c and T4c of transistors T3 and T4. Each of the spaced-apart portions of the second active layer ACL2 with the channels interposed therebetween may constitute first and second electrodes of transistors T3 and T4.

[0113] The fourth transistor T4 , which is an oxide semiconductor transistor, may be a transistor located closest to the edge of the substrate SUB among the transistors T1 to T8 of the outer pixel.

[0114] refer to Fig.10 , shows an exemplary pattern of the fourth electrode layer CEL4. The fourth electrode layer CEL4 may include gate electrodes T3g and T4g of transistors T3 and T4. The gate electrodes T3g and T4g may overlap with channels T3c and T4c, respectively, in the third direction DR3.

[0115] In addition, some patterns of the fourth electrode layer CEL4 may constitute the second scan line GCi, the third-b scan line GIib, the emission line EMi, the bias line VOBSL, and the dummy line DML. A bias voltage VOBS may be applied to the bias line VOBSL.

[0116] The first contact hole GCTH may be a hole etched to connect the pattern of the fourth electrode layer CEL4 to an electrode layer or an active layer under the pattern.

[0117] The dummy line DML may be located between an edge of the substrate SUB and an outer pixel. The dummy line DML may be located in the non-display area NDA.

[0118] refer to Fig.10 , Fig.16 and Fig.17 The dummy line DML may extend across the first area AR1, the second area AR2, and the third area AR3 in the second direction DR2. One end DMLE1 of the dummy line DML may be located in the first area AR1. The other end DMLE2 of the dummy line DML may be located in the third area AR3.

[0119] It can be seen that the third-b scan line GIib connected to the fourth transistor T4 which is an oxide semiconductor transistor is located in the same electrode layer as the dummy line DML. The vertical distance between the third-b scan line GIib connected to the fourth transistor T4 and the substrate SUB may be the maximum vertical distance among the vertical distances between the scan lines GWi, GBi, GIia, GIib and GCi connected to the outer pixels and the substrate SUB. That is, the fourth electrode layer CEL4 may be located above the second electrode layer CEL2 and the third electrode layer CEL3 (i.e., located above the second electrode layer CEL2 and the third electrode layer CEL3 in the third direction DR3).

[0120] refer to Fig.11 , showing that Figures 5 to 10 Overlaid layout.

[0121] refer to Fig.12 , an exemplary pattern of the fifth electrode layer CEL5 is shown.

[0122] Some patterns of the fifth electrode layer CEL5 can constitute the first-a power line ELVDDLa, the second power line ELVSSL, the horizontal bridge line BRSH and the second initialization line VAINTL. The second initialization voltage VAINT can be applied to the second initialization line VAINTL. The first power voltage ELVDD can be applied to the first-a power line ELVDDLa. The second power voltage ELVSS can be applied to the second power line ELVSSL. The first-a power line ELVDDLa is referred to later. Fig.13 The described first-b power line ELVDDLb may constitute the first power line.

[0123] The data driver 12 (or the timing controller 11), the scan driver 13, and the emission driver 15 may be constructed in the form of an IC, and the signal lines of the data driver 12 may be locally connected to the pad electrodes of the pixel unit 14. The horizontal bridge line BRSH may act as a bridge so that dense lines connected to the pad electrodes may be widely spread and connected throughout the pixel unit 14.

[0124] The second contact hole PCTH may be a hole etched to connect the pattern of the fifth electrode layer CEL5 to the electrode layer or active layer under the pattern. Some of the second contact holes PCTH may be dummy holes. The dummy holes may not be holes for electrical connection, but may function as channels for hydrogen discharge. The dummy holes may be located in the non-display area NDA.

[0125] The third contact hole OCTH may be a hole etched to connect the pattern of the fifth electrode layer CEL5 to the electrode layer or the active layer under the pattern.

[0126] refer to Fig.13 , shows an exemplary pattern of the sixth electrode layer CEL6. Some patterns of the sixth electrode layer CEL6 may constitute the first-b power line ELVDDLb, the data line VDj, and the vertical bridge line BRSV. The first power voltage ELVDD may be applied to the first-b power line ELVDDLb.

[0127] The fourth contact hole VIAH may be a hole etched to connect the pattern of the sixth electrode layer CEL6 to an electrode layer or an active layer under the pattern.

[0128] The vertical bridge wire BRSV may play the same role as the horizontal bridge wire BRSH. When the horizontal bridge wire BRSH extends in the second direction DR2, the vertical bridge wire BRSV may extend in the first direction DR1. The corresponding horizontal bridge wire BRSH and the vertical bridge wire BRSV may be connected to each other.

[0129] refer to Fig.14 , showing Figures 5 to 13 Overlaid layout.

[0130] The dummy hole DMH may be located between the edge of the substrate SUB and the outer pixel. The dummy hole DMH may be located in the non-display area NDA. The dummy hole DMH may include a portion of the upper insulating layer (e.g., the seventh insulating layer INL7). The dummy hole DMH may not include the electrode material therein. The dummy hole DMH may prevent the diffusion of hydrogen and discharge hydrogen to the outside.

[0131] The dummy line DML may extend in a second direction DR2 different from the first direction DR1 between the dummy holes DMH. The dummy line DML may be located between the fifth insulating layer INL5 and the sixth insulating layer INL6. The dummy hole DMH may pass through the fifth insulating layer INL5 and the sixth insulating layer INL6. The dummy hole DMH and the dummy line DML may not overlap each other in the third direction DR3 so that the dummy line DML is not damaged when the dummy hole DMH is etched.

[0132] The dummy line DML may be connected to the first-b power line ELVDDLb. For example, one end DMLE1 of the dummy line DML may be connected to the first-b power line ELVDDLb in an area (e.g., a first area AR1) adjacent to a first corner of the substrate SUB. The first-b power line ELVDDLb may be located between an edge of the substrate SUB and a dummy hole among the dummy holes DMH that is closest to the edge of the substrate SUB, and may extend in the second direction DR2.

[0133] The dummy line DML to which the first power voltage ELVDD is applied may perform a hydrogen absorption function, thereby preventing diffusion of hydrogen and preventing conduction of a transistor channel.

[0134] Fig.15A and Fig. 15B is a cross-sectional view of a non-display area NDA and a display area DA according to an embodiment of the present disclosure.

[0135] Fig.15A is along Fig.14 A cross-sectional view taken along line AA′ in a non-display area NDA. Fig. 15B is an exemplary cross-sectional view of any polysilicon semiconductor transistor TFT1, oxide semiconductor transistor TFT2, and light emitting element LD in the display area DA. Fig.15A and Fig. 15B When and Figures 4C to 14 The contents described together and the duplicate contents are omitted.

[0136] The first barrier layer BRR1 may be located between the substrate SUB and the first electrode layer CEL1. The second barrier layer BRR2 may be located between the first electrode layer CEL1 and the first insulating layer INL1. The barrier layers BRR1 and BRR2 may block unnecessary components such as moisture or oxygen from entering from the outside. The barrier layers BRR1 and BRR2 may be made of the same or similar material as the above-mentioned insulating layer.

[0137] A single insulating layer or a plurality of insulating layers INL8 and INL9 may be located on the sixth electrode layer CEL6.

[0138] The light emitting element LD may include an anode electrode ANE, a light emitting layer EML, and a cathode electrode CTE.

[0139] The anode electrode ANE may be located on the insulating layer INL9 and may be connected to a partial pattern of the sixth electrode layer CEL6 through a contact hole. The anode electrode ANE may be formed of a metal layer such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and alloys thereof, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and / or indium tin zinc oxide (ITZO), etc. The anode electrode ANE may be formed of one type of metal, but is not limited thereto, and may be formed of an alloy of two or more types of metals such as Ag and Mg.

[0140] When it is desired to provide an image in a lower direction of the substrate SUB, the anode electrode ANE may be formed of a transparent conductive layer, and when it is desired to provide an image in an upper direction of the substrate SUB, the anode electrode ANE may be formed of a metal reflective layer and / or a transparent conductive layer.

[0141] A pixel defining layer PDL is provided on the substrate SUB on which the anode electrode ANE is formed, which separates the emission area of ​​each pixel. The pixel defining layer PDL may be an organic insulating layer formed of an organic material. As the organic material, an organic insulating material such as a polyacrylate compound, a polyimide compound, a fluorine-based carbon compound such as polytetrafluoroethylene, and a benzocyclobutene compound may be used.

[0142] The pixel defining layer PDL may expose the upper surface of the anode electrode ANE and may protrude from the substrate along the circumference of the emission region. The light emitting layer EML may be provided in the emission region surrounded by the pixel defining layer PDL.

[0143] The light emitting layer EML may include a low molecular weight material or a high molecular weight material. The low molecular weight material may include copper phthalocyanine (CuPc), N,N-bis(naphthalene-1-yl)-N,N'-diphenyl-benzidine (N,N'-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine) (NPB) and tris(8-hydroxyquinoline)aluminum (Alq 3 ) etc. These materials can be formed by vacuum deposition method. The polymer material can include PEDOT, polyvinylene (PPV) and polyfluorene.

[0144] The light emitting layer EML may be provided as a single layer, or may be provided as a multilayer including various functional layers. When the light emitting layer EML is provided as a multilayer, the light emitting layer EML has a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or complex structure. The light emitting layer EML may be formed by a screen printing or inkjet printing method or laser induced thermal imaging (LITI), etc.

[0145] According to an embodiment, at least a portion of the light emitting layer EML may be integrally formed across the plurality of anode electrodes ANE, or may be separately provided to correspond to each of the plurality of anode electrodes ANE.

[0146] A cathode electrode CTE may be provided on the light emitting layer EML. The cathode electrode CTE may be provided for each pixel, or may be provided to cover most of the display area DA and may be shared by a plurality of pixels.

[0147] The cathode electrode CTE may be formed of a metal layer such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr and a transparent conductive layer such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), etc. In an embodiment of the present disclosure, the cathode electrode CTE may be formed as a multilayer including a double layer or more layers of a metal thin film, for example, may be formed as a triple layer of ITO / Ag / ITO.

[0148] When it is desired to provide an image in a lower direction of the substrate SUB, the cathode electrode CTE may be formed of a metal reflective layer and / or a transparent conductive layer, and when it is desired to provide an image in an upper direction of the substrate SUB, the cathode electrode CTE may be formed of a transparent conductive layer.

[0149] Fig.16 2 is a diagram illustrating a second area AR2 of a pixel unit according to an embodiment of the present disclosure. Fig.16 In FIG. 1 , the second region AR2 of the fourth electrode layer CEL4 is shown.

[0150] The other part of the dummy line DML except one end DMLE1 and the other end DMLE2 may not be connected to the first-b power line ELVDDLb. That is, in the second area AR2, the dummy line DML may not be connected to the first-b power line ELVDDLb. According to this embodiment, the dummy line DML and the first-b power line ELVDDLb may be minimized. Fig.12 The overlap of the second power line ELVSSL is shown in FIG.

[0151] Fig.17 is a diagram illustrating a third area AR3 of a pixel unit according to an embodiment of the present disclosure. Fig.17 , the third area AR3 of the fourth electrode layer CEL4 is shown.

[0152] The other end DMLE2 of the dummy line DML may be connected to the first-b power line ELVDDLb in a region adjacent to the second corner of the substrate SUB (eg, the third region AR3 ).

[0153] For example, when the other end DMLE2 of the dummy line DML is not connected to the first-b power line ELVDDLb, a voltage deviation may occur between one end DMLE1 and the other end DMLE2 of the dummy line DML due to an IR drop phenomenon. According to this embodiment, the first power voltage ELVDD may be uniformly applied to the dummy line DML.

[0154] Fig.18 and Fig.19 is a diagram illustrating the effect of preventing hydrogen diffusion according to an embodiment of the present disclosure.

[0155] refer to Fig.18 , it can be seen that the results of comparing the object simulation REF1 and the simulation PRS1 to which the embodiments of the present disclosure are applied.

[0156] In the simulation REF1 without the dummy line DML, it can be seen that hydrogen (upper color spots of the layout) invades and diffuses into the area of ​​the pixel circuit.

[0157] On the other hand, referring to the simulation PRS1 according to the embodiment of the present disclosure, it can be seen that hydrogen is not diffused to the dummy lines DML extending between the dummy holes DMH.

[0158] refer to Fig.19 , it can be seen that the results of the comparison object simulations REF21, REF22 and REF23 and the simulation PRS2 to which the embodiments of the present disclosure are applied.

[0159] In the comparison object simulations REF21, REF22 and REF23, the third-b scan line GIib is configured in an island shape in the fourth electrode layer CEL4. On the other hand, in the simulation PRS2 to which the embodiment of the present disclosure is applied, the third-b scan line GIib is configured in a line shape in the fourth electrode layer CEL4.

[0160] When comparing the results of the simulations, it can be seen that the diffusion of hydrogen (color spots of the layout) is minimal in the simulated PRS2 to which the embodiments of the present disclosure are applied.

[0161] The drawings mentioned so far and the detailed description of the present disclosure described in this article are only examples of the present disclosure, which are only used to describe the present disclosure and are not intended to limit the meaning and scope of the present disclosure described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments according to the present disclosure are possible. Therefore, the true scope of the present disclosure should be determined by the technical spirit of the claims.

Claims

1. A display device, comprising: A substrate including a display area and a non-display area; outer pixels located in the display area and in a first direction from an edge of the substrate; a dummy hole located in the non-display area and between the edge of the substrate and the outer pixel; as well as a dummy line located in the non-display area and extending between the dummy holes in a second direction different from the first direction, Wherein, the dummy line is located between the first insulating layer and the second insulating layer, and The dummy hole passes through the first insulating layer and the second insulating layer.

2. The display device according to claim 1, further comprising: a third insulating layer, located on the second insulating layer, The dummy hole includes a portion of the third insulating layer therein.

3. The display device according to claim 1, wherein: One end of the dummy line is connected to a first power line in a region adjacent to a first corner of the substrate, and The other end of the dummy line is connected to the first power line in a region adjacent to a second corner of the substrate.

4. The display device according to claim 3, wherein: The first electric force line is located between the edge of the substrate and a dummy hole among the dummy holes that is closest to the edge, and extends in the second direction.

5. The display device according to any one of claims 1 to 4, wherein: Each of the outer pixels comprises a transistor, and At least one of the transistors is an oxide semiconductor transistor.

6. The display device according to claim 5, wherein: The oxide semiconductor transistor is a transistor located closest to the edge of the substrate among the transistors.

7. The display device according to claim 6, wherein: A scan line connected to the oxide semiconductor transistor is located in the same electrode layer as the dummy line.

8. A display device, comprising: A substrate including a display area and a non-display area; outer pixels located in the display area and in a first direction from an edge of the substrate; as well as a dummy line located in the non-display area and extending in a second direction different from the first direction between the edge of the substrate and the outer pixel, wherein each of the outer pixels comprises a plurality of transistors including at least one oxide semiconductor transistor, The oxide semiconductor transistor is a transistor located closest to the edge of the substrate among the plurality of transistors, A scan line connected to the oxide semiconductor transistor and the dummy line are located in the same electrode layer.

9. The display device according to claim 8, wherein: A vertical distance between the scan line connected to the oxide semiconductor transistor and the substrate is a maximum vertical distance among vertical distances between the scan line connected to the outer pixel and the substrate.

10. The display device according to claim 8, further comprising: a dummy hole located in the non-display area and between the edge of the substrate and the outer pixel, The dummy line is extended so as not to vertically overlap with the dummy hole.

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