Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel comprises a substrate; the first active layer and the multiple conductive layers are arranged on one side of the substrate, the first active layer and the multiple conductive layers form at least one pixel unit, and the pixel unit comprises two pixel circuits in mirror symmetry; the first active layer comprises a first active area and a second active area, the multi-layer conducting layer comprises a first conducting layer, the first conducting layer comprises a first signal wire and a second signal wire, the orthographic projection of the first signal wire on the substrate covers the orthographic projection of the first active area on the substrate, and the orthographic projection of the second signal wire on the substrate covers the orthographic projection of the second active area on the substrate. The orthographic projection of the second signal wire on the substrate covers the orthographic projection of the second active region on the substrate; in the same pixel unit, orthographic projections of the first signal wires in the two pixel circuits on the substrate are separated, and the first interval size between the first active areas in the two pixel circuits is larger than the second interval size between the second active areas. The scheme is beneficial to improving the layout space utilization rate.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the display performance of display panels.

[0003] Currently, the layout space utilization rate of display panels is low, which is not conducive to achieving high PPI (Pixels per inch, pixel density) design, and thus is not conducive to improving display effects. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to improve the layout utilization of the display panel.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising:

[0006] substrate;

[0007] A first active layer and a multi-layer conductive layer are arranged on one side of the substrate, wherein the first active layer and the multi-layer conductive layer constitute at least one pixel unit, and the pixel unit includes two pixel circuits with mirror symmetry;

[0008] The first active layer includes a first active area and a second active area, the multi-layer conductive layer includes a first conductive layer, the first conductive layer is located on a side of the first active layer away from the substrate, the first conductive layer includes a first signal line and a second signal line, the orthographic projection of the first signal line on the substrate covers the orthographic projection of the first active area on the substrate, and the orthographic projection of the second signal line on the substrate covers the orthographic projection of the second active area on the substrate;

[0009] In the same pixel unit, the orthographic projections of the first signal wirings in the two pixel circuits on the substrate are separated, and the orthographic projections of the second signal wirings in the two pixel circuits on the substrate are overlapped;

[0010] Wherein, in the same pixel unit, a first spacing dimension between the first active areas in two pixel circuits is greater than a second spacing dimension between the second active areas.

[0011] Optionally, the two pixel circuits in the same pixel unit are arranged along a first direction, the first signal wiring and the second signal wiring are arranged along a second direction and extend along the first direction, and the first direction intersects with the second direction;

[0012] In the first direction, the first active areas of two pixel circuits in the same pixel unit are adjacent;

[0013] Optionally, the second active area and the first active area are located on the same side of the pixel circuit;

[0014] Optionally, in the first direction, the first spacing size is greater than or equal to 4um, and the second spacing size is greater than or equal to 2um;

[0015] Optionally, an orthographic projection of the first signal routing line on the substrate is separated from an orthographic projection of the second signal routing line on the substrate.

[0016] Optionally, an orthographic projection area of ​​the first signal wiring on the substrate is larger than an orthographic projection area of ​​the first active region on the substrate;

[0017] Optionally, at a position close to a midline of the pixel unit, an edge of the first signal routing line in the same pixel circuit exceeds an edge of the first active area by at least 1 um.

[0018] Optionally, the pixel circuit comprises a driving transistor, at least one auxiliary transistor and a first transistor;

[0019] The first active region includes a channel region of the driving transistor and a channel region of the auxiliary transistor, and the channel region of the driving transistor is connected to the channel region of the auxiliary transistor;

[0020] The second active region includes a channel region of the first transistor, and the channel region of the first transistor is connected to the auxiliary transistor through the first active layer;

[0021] Optionally, an orthographic projection of a channel region of the auxiliary transistor on the substrate partially overlaps with an orthographic projection of a channel region of the first transistor on the substrate;

[0022] Or, an orthographic projection of a channel region of the auxiliary transistor on the substrate is separated from an orthographic projection of a channel region of the first transistor on the substrate;

[0023] Optionally, at least part of the channel region of the driving transistor extends along a first direction, the channel region of the auxiliary transistor extends along a second direction, the channel region of the first transistor extends along the second direction, and the first direction intersects the second direction;

[0024] Optionally, the first direction intersects the second direction perpendicularly;

[0025] Optionally, the overlapping position of the first signal line and the first active area respectively forms the gate of the auxiliary transistor and the gate of the driving transistor, and the overlapping position of the second signal line and the second active area forms the gate of the first transistor.

[0026] Optionally, the pixel circuit includes two auxiliary transistors, namely a second transistor and a third transistor, a channel region of the second transistor and a channel region of the third transistor extend along the second direction, and the channel region of the second transistor and the channel region of the third transistor are connected;

[0027] Optionally, an orthographic projection of a channel region of the second transistor on the substrate and an orthographic projection of a channel region of the third transistor on the substrate at least partially overlap;

[0028] Optionally, the widths of the channel region of the second transistor and the channel region of the third transistor are equal, and the lengths of the channel region of the second transistor and the channel region of the third transistor are equal;

[0029] Optionally, the width of the channel region of the second transistor and the channel region of the third transistor is less than or equal to the width of the channel region of the driving transistor.

[0030] Optionally, the display panel further includes a data line, wherein the data line is connected to a first electrode of the first transistor through a first type via hole, a second electrode of the first transistor is connected to a first electrode of the second transistor through the first active layer, a second electrode of the second transistor is connected to a first electrode of the driving transistor through the first active layer, and the first transistor is used to transmit a data voltage on the data line to a gate of the driving transistor;

[0031] Optionally, the pixel circuit further includes a fourth transistor and a fifth transistor, and the display panel further includes a third signal line, a first connecting line and a power line, the third signal line extends along the first direction, and the third signal line and the first active layer overlap position respectively form the gate of the fourth transistor and the gate of the fifth transistor, the first electrode of the fourth transistor is connected to the power line through the first connecting line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor through the first active layer, the second electrode of the third transistor is connected to the first electrode of the driving transistor through the first active layer, the second electrode of the driving transistor is connected to the first electrode of the fifth transistor through the first active layer, and the second electrode of the fifth transistor is connected to the light-emitting element;

[0032] Optionally, the first electrode of the fourth transistor is connected to one end of the first connection line through the first type via hole, and the power line is connected to the other end of the first connection line through the first type via hole or directly;

[0033] Optionally, the pixel circuit further includes a storage capacitor, a first plate of the storage capacitor is connected to the gate of the driving transistor, and a second plate of the storage capacitor is connected to the other end of the first connecting line through the first type of via hole;

[0034] Optionally, the multi-layer conductive layer further includes a second conductive layer, a third conductive layer and a fourth conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate, the third conductive layer is located on a side of the second conductive layer away from the substrate, and the fourth conductive layer is located on a side of the third conductive layer away from the substrate;

[0035] Optionally, the third signal wiring and the first plate of the storage capacitor are located in the first conductive layer, and the second plate of the storage capacitor is located in the second conductive layer;

[0036] Optionally, the first connection line is located in the third conductive layer, and the data line and the power line are located in the fourth conductive layer;

[0037] Optionally, the orthographic projection of the third signal routing line on the substrate is located on a side of the orthographic projection of the first signal routing line on the substrate away from the orthographic projection of the second signal routing line on the substrate.

[0038] Optionally, the pixel circuit further includes a sixth transistor, the display panel further includes a fourth signal line and a first initialization signal line, the fourth signal line and the first initialization signal line both extend along the first direction, the fourth signal line overlaps the first active layer to form a gate of the sixth transistor, a first electrode of the sixth transistor is connected to the first initialization signal line through the first type of via, and a second electrode of the sixth transistor is connected to the light-emitting element through the first type of via;

[0039] Optionally, the orthographic projection of the fourth signal routing line on the substrate is located on a side of the orthographic projection of the third signal routing line on the substrate away from the orthographic projection of the first signal routing line on the substrate;

[0040] Optionally, the first initialization signal line is located in the third conductive layer, and the fourth signal line is located in the first conductive layer;

[0041] Optionally, the pixel circuit further includes a seventh transistor, the display panel further includes a second initialization signal line and a second connection line, the position where the fourth signal line overlaps the first active layer also forms a gate of the seventh transistor, a first electrode of the seventh transistor is connected to the second initialization signal line through the first type of via, and a second electrode of the seventh transistor is connected to the first electrode of the third transistor through the second connection line;

[0042] Optionally, the second electrode of the seventh transistor is connected to one end of the second connection line through the first type via hole, and the first electrode of the third transistor is connected to the other end of the second connection line through the first type via hole;

[0043] Optionally, the orthographic projection of the second initialization signal line on the substrate is located between the orthographic projection of the third signal line on the substrate and the orthographic projection of the first initialization signal line on the substrate, and the orthographic projection of the second initialization signal line on the substrate is located on a side of the orthographic projection of the third signal line on the substrate away from the orthographic projection of the first signal line on the substrate;

[0044] Optionally, the second connection line is located in the third conductive layer, and the second initialization signal line is located in the third conductive layer;

[0045] Optionally, an orthographic projection of the second initialization signal line on the substrate at least partially overlaps with an orthographic projection of the fourth signal line on the substrate;

[0046] Optionally, an orthographic projection of the second connecting line on the substrate intersects with an orthographic projection of the third signal line on the substrate.

[0047] Optionally, the pixel circuit further includes an eighth transistor, the display panel further includes a second active layer and a fifth signal wiring, the fifth signal wiring extends along the first direction, the fifth signal wiring and the second active layer overlap to form a first gate of the eighth transistor, the first electrode of the eighth transistor is connected to the second electrode of the driving transistor through a third connecting line, and the second electrode of the eighth transistor is connected to the gate of the driving transistor through a fourth connecting line;

[0048] Optionally, the first electrode of the eighth transistor is connected to one end of the third connection line through a second type via, the second electrode of the driving transistor is connected to the other end of the third connection line through the first type via, the second electrode of the eighth transistor is connected to one end of the fourth connection line through the second type via, and the gate of the driving transistor is connected to the other end of the fourth connection line through the first type via;

[0049] Optionally, the fifth signal trace is located in the second conductive layer;

[0050] Optionally, the display panel further includes a sixth signal line, the sixth signal line extends along the first direction, and the sixth signal line overlaps the second active layer to form a second gate of the eighth transistor; wherein the first gate of the eighth transistor is a top gate, and the second gate of the eighth transistor is a bottom gate, or the first gate of the eighth transistor is a bottom gate, and the second gate of the eighth transistor is a top gate;

[0051] Optionally, an orthographic projection of the sixth signal routing line on the substrate at least partially overlaps with an orthographic projection of the fifth signal routing line on the substrate;

[0052] Optionally, the fifth signal routing line and the sixth signal routing line are arranged in different layers;

[0053] Optionally, the multi-layer conductive layer further includes a fifth conductive layer, the fifth conductive layer is located between the second conductive layer and the third conductive layer, and the sixth signal trace is located in the fifth conductive layer;

[0054] Optionally, the second active layer is located between the second conductive layer and the fifth conductive layer;

[0055] Optionally, the orthographic projections of the fifth signal routing and the sixth signal routing on the substrate are both located between the orthographic projection of the first signal routing on the substrate and the orthographic projection of the second signal routing on the substrate;

[0056] Optionally, the pixel circuit further includes a ninth transistor, the display panel further includes a seventh signal line and a third initialization signal line, the third initialization signal line and the seventh signal line extend along the first direction, the seventh signal line overlaps the second active layer to form a first gate of the ninth transistor, a first electrode of the ninth transistor is connected to the third initialization signal line through a fifth connection line, and a second electrode of the ninth transistor is connected to the second electrode of the eighth transistor through the second active layer;

[0057] Optionally, the first electrode of the ninth transistor is connected to one end of the fifth connection line through the second type via hole, and the third initialization signal line is connected to the other end of the fifth connection line through the second type via hole;

[0058] Optionally, the seventh signal line is located in the second conductive layer, and the third initialization signal line is located in the fifth conductive layer;

[0059] Optionally, the display panel further includes an eighth signal line, the eighth signal line extends along the first direction, and the eighth signal line overlaps with the second active layer to form a second gate of the ninth transistor; wherein the first gate of the ninth transistor is a top gate, and the second gate of the ninth transistor is a bottom gate, or the first gate of the ninth transistor is a bottom gate, and the second gate of the ninth transistor is a top gate;

[0060] Optionally, the eighth signal line is located in the fifth conductive layer, and an orthographic projection of the eighth signal line on the substrate at least partially overlaps with an orthographic projection of the seventh signal line on the substrate;

[0061] Optionally, the orthographic projections of the eighth signal routing and the seventh signal routing on the substrate are both located on a side of the orthographic projection of the second signal routing on the substrate away from the orthographic projection of the first signal routing on the substrate;

[0062] Optionally, the orthographic projection of the third initialization signal line on the substrate is located on a side of the orthographic projection of the eighth signal line on the substrate away from the orthographic projection of the first signal line on the substrate;

[0063] Optionally, the second active layer extends along the second direction;

[0064] Optionally, the material of the first active layer includes polysilicon, and the material of the second active layer includes metal oxide.

[0065] Optionally, optionally, the material of the first active layer includes polysilicon, and the material of the second active layer includes metal oxide.

[0066] Optionally, a groove is provided at a corner position of the channel region of the driving transistor on the extension path.

[0067] According to another aspect of the present invention, a display device is provided. The display device includes the display panel provided by any embodiment of the present invention.

[0068] The technical solution provided by the embodiment of the present invention is that in the same pixel unit, when the spacing between two first signal routing lines that are arranged in the same layer and are not connected in two mirror-symmetrical pixel circuits meets the design requirements, the first active layer above and / or below the position where the first active layer overlaps with the first signal routing line is bent so that the first active layer at this position and the first active layer above and / or below it are not on the same straight line, thereby making the first spacing dimension between the first active areas in the two pixel circuits larger than the second spacing dimension between the second active areas, so as to save the layout space at the second active area, thereby improving the layout space utilization, and facilitating the realization of high PPI design.

[0069] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0071] Figure 1 A schematic diagram of a layout structure of a display panel provided in the related art;

[0072] Figure 2 A schematic diagram of a layout structure of a display panel provided by an embodiment of the present invention;

[0073] Figure 3 A schematic structural diagram of a first active layer provided by an embodiment of the present invention;

[0074] Figure 4 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0075] Figure 5 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention;

[0076] Figure 6 A schematic diagram of the structure of another first active layer provided by an embodiment of the present invention;

[0077] Figure 7 A schematic diagram of the structure of another first active layer provided by an embodiment of the present invention;

[0078] Figure 8 A schematic diagram of the structure of another first active layer provided by an embodiment of the present invention;

[0079] Fig. 9 A schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0080] Fig.10 A schematic diagram of another display panel layout structure provided by an embodiment of the present invention;

[0081] Fig.11 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0082] Fig.12A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0083] Fig.13 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0084] Fig.14 A schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0085] Fig.15 A schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0086] Fig.16 A schematic diagram of the structure of another first active layer provided by an embodiment of the present invention;

[0087] Fig.17 A schematic diagram of the structure of another first active layer provided by an embodiment of the present invention;

[0088] Fig.18 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0089] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0090] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0091] As described in the background art, the space utilization rate of the display panel in the related art is low. The inventors have found through research that the main reason is that the equipment capacity leads to the limitation of the process technology. Figure 1FIG. 1 is a schematic diagram of a layout structure of a display panel provided in the related art, and specifically shows the structure of the driving transistor T0 in the pixel circuit of the display panel with a mirror arrangement. Figure 1 , the display panel includes an active layer and a gate layer arranged in a stacked manner, the active layer position covered by the gate layer is the channel region of the driving transistor T0, and the source region S01 and the drain region S02 are on both sides of the channel region. In the process requirements, in the same film layer, the spacing between two lines used to transmit different signals is greater than or equal to 2um, that is, W0≥2um. When the layout space is tight, it is usually designed according to the minimum value of 2um. When the gate G of the driving transistor T0 overlaps with the source region S01 to form other transistors, its gate G must exceed a part of the active layer, that is, the edge of the gate G extends to the right and covers the edge of the source region S01. According to the design requirements, the spacing between the gates G in two adjacent pixel circuits must be greater than or equal to 2um, so W0 must also be increased accordingly, which leads to the spacing between the active layers at the upper and lower positions where the gate G overlaps with the source region S01 to form a transistor. It also increases, occupies the layout space, which is not conducive to high PPI design.

[0092] In view of the above problems, an embodiment of the present invention provides a display panel to improve the utilization rate of layout space. Figure 2 A schematic diagram of a layout structure of a display panel provided by an embodiment of the present invention, Figure 3 A schematic diagram of the structure of a first active layer provided in an embodiment of the present invention, referring to Figure 2 and Figure 3 , the display panel provided in this embodiment includes:

[0093] Substrate: The substrate is used to provide protection and support for other film layers of the display panel. The substrate can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. Each conductive layer can be made of any conductive material, such as a metal, alloy, metal oxide or non-metallic conductive material.

[0094] The first active layer 20 and the multi-layer conductive layer are arranged on one side of the substrate. The first active layer 20 and the multi-layer conductive layer constitute at least one pixel unit 100. The pixel unit 100 includes two mirror-symmetrical pixel circuits; wherein the two pixel circuits in the same pixel unit 100 are mirror-symmetrical about the center line MIL1. The first active layer 20 can be made of polycrystalline silicon material. It can be understood that at least one insulating layer is arranged between each two adjacent conductive layers, and at least one insulating layer is also arranged between the first active layer 20 and the conductive layer adjacent thereto; the material of the insulating layer can be set to an inorganic material or an organic material according to the requirements, which is not specifically limited here.

[0095] The first active layer 20 includes a first active area 201 and a second active area 202, the multi-layer conductive layer includes a first conductive M1 layer, the first conductive layer M1 is located on a side of the first active layer 20 away from the substrate, the first conductive layer M1 includes a first signal line SL1 and a second signal line SL2, the orthographic projection of the first signal line SL1 on the substrate covers the orthographic projection of the first active area 201 on the substrate, and the orthographic projection of the second signal line SL2 on the substrate covers the orthographic projection of the second active area 202 on the substrate;

[0096] In the same pixel unit 100 , the orthographic projections of the first signal lines SL1 in the two pixel circuits on the substrate are separated, and the orthographic projections of the second signal lines SL2 in the two pixel circuits on the substrate are overlapped.

[0097] The first signal line SL1 and the first active layer 20 can constitute the driving transistor T0 in the pixel circuit, the second signal line SL2 and the first active layer 20 can constitute the switching transistor in the pixel circuit, the first active area 201 can include the channel area of ​​the driving transistor T0, and the second active area 202 can include the channel area of ​​other switching transistors. In this embodiment, in order to ensure the stability of the driving transistor T0, the first signal line SL1 needs to cover the edge of the first active area 201. And the signals transmitted by the gates of the driving transistors T0 in the two pixel circuits may be different, therefore, there is a gap between the two first signal lines SL2 set in the same layer.

[0098] In this embodiment, in the same pixel unit 100, the first spacing dimension d1 between the first active areas 201 in the two pixel circuits is greater than the second spacing dimension d2 between the second active areas 202, and d2 does not increase with the increase of d1, so as to reduce the spacing at the second active areas 202, thereby improving the layout space utilization.

[0099] It should be noted that, in the present embodiment, the spacing size refers to the minimum distance between the edge of the first active layer 20 of one pixel circuit and the edge of the first active layer 20 of another pixel circuit.

[0100] According to the technical solution provided by the embodiment of the present invention, in the same pixel unit, when the spacing between two first signal lines SL1 that are arranged in the same layer and are not connected in two mirror-symmetrical pixel circuits meets the design requirements, the first active layer 20 above and / or below the overlapping position of the first active layer 20 with the first signal line SL1 is bent so that the first active layer 20 at this position and the first active layer 20 above and / or below it are not on the same straight line, thereby making the first spacing dimension d1 between the first active areas 201 in the two pixel circuits larger than the second spacing dimension d2 between the second active areas 202, so as to save the layout space at the second active area 202, thereby improving the layout space utilization, and facilitating the realization of high PPI design.

[0101] Optionally, two pixel circuits in the same pixel unit 100 are arranged along a first direction X, the first signal line SL1 and the second signal line SL2 are arranged along a second direction Y and extend along the first direction X, and the first direction X intersects with the second direction Y, for example, the first direction X intersects with the second direction Y perpendicularly. In the first direction X, the first active areas 201 of the two pixel circuits in the same pixel unit 100 are adjacent, and the second active area 202 and the first active area 201 are located on the same side of the pixel circuit, which is beneficial to the layout.

[0102] Optionally, an orthographic projection of the first signal line SL1 on the substrate is separated from an orthographic projection of the second signal line SL2 on the substrate to form different transistors.

[0103] Figure 4 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, specifically: Figure 2 The cross-sectional structure of the display panel along the cutting line AA' is shown, wherein the Z direction is the thickness direction of the display panel, and the reference Figures 2 to 4 The orthographic projection area of ​​the first signal line SL1 on the substrate 10 is larger than the orthographic projection area of ​​the first active area 201 on the substrate 10 to ensure that the orthographic projection of the first signal line SL1 on the substrate 10 completely covers the orthographic projection of the first active area 201 on the substrate 10, thereby ensuring the stability of the formed transistor.

[0104] In this embodiment, at the position of the center line MIL1 close to the pixel unit 100, the edge of the first signal line SL1 in the same pixel circuit exceeds the edge of the first active area 201 by at least 1um, that is, d3≥1um. The spacing between the two first signal lines SL1 arranged on the same layer is at least 2um. Therefore, in order to meet the process technology requirements, in the first direction X, the first spacing dimension d1 is greater than or equal to 4um. At the overlap position of the signal lines on the same layer and interconnected with the first active layer 20, such as the overlap position of the second signal line SL2 with the first active layer 20, the first active layer 20 is bent so that d2<d1, thereby saving the wiring space of the first active layer 20 at the overlap position of the second signal line SL2 with the first active layer 20, thereby improving the layout utilization. Here, d2≥2um.

[0105] Figure 5 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 6 A schematic diagram of another structure of the first active layer provided in an embodiment of the present invention, referring to Figure 5 and Figure 6 On the basis of the above embodiments, optionally, the pixel circuit includes a driving transistor T0, at least one auxiliary transistor (a second transistor T2 and / or a third transistor T3) and a first transistor T1, and the first transistor T1 can be used to write a data voltage Vdata to the driving transistor T0. The first active area 201 includes a channel area 2011 of the driving transistor T0 and a channel area 2012 of the auxiliary transistor, and the channel area 2011 of the driving transistor T0 is connected to the channel area 2012 of the auxiliary transistor.

[0106] Specifically, the first signal line SL1 and the first active area 201 overlap to form the gate of the auxiliary transistor and the gate of the driving transistor T0, respectively, and the gate of the auxiliary transistor and the gate of the driving transistor T0 are an integrated structure. In other words, it is equivalent to extending the gate of the driving transistor T0 along the first direction X, so that the gate of the driving transistor T0 covers the edge of the first active layer 20 to form an auxiliary transistor. Here, it can be understood that the first signal line SL1 covers the entire first active area 201, and the source area of ​​the driving transistor T0 is used to form the channel area of ​​the auxiliary transistor, so that the channel area 2011 of the driving transistor T0 is connected to the channel area 2012 of the auxiliary transistor. On the basis of not increasing the layout area, the extension of the channel area of ​​the driving transistor DTFT can be achieved. Since the channel area of ​​the driving transistor DTFT is directly connected to the channel area of ​​each auxiliary transistor ATFT, the space occupied by the source area of ​​the driving transistor DTFT and the drain area of ​​the auxiliary transistor ATFT can be saved to maximize the use of the layout space.

[0107] Continue to refer Figure 6The overlapping position of the second signal line SL2 and the second active area 202 forms the gate of the first transistor T1. The second active area 202 includes a channel area 2021 of the first transistor T1. The channel area 2021 of the first transistor T1 is connected to the auxiliary transistor through the first active layer 20.

[0108] Optionally, at least part of the channel region 2011 of the driving transistor T0 extends along the first direction X, the channel region 2012 of the auxiliary transistor extends along the second direction Y, and the channel region 2021 of the first transistor T1 extends along the second direction Y. Here, the orthographic projection of the channel region 2012 of the auxiliary transistor on the substrate 10 partially overlaps with the orthographic projection of the channel region 2021 of the first transistor T1 on the substrate 10. In the same pixel unit 100, when the first spacing dimension d1 between the first active regions 201 in the two pixel circuits is fixed, by overlapping the orthographic projection of the channel region 2012 of the auxiliary transistor on the substrate 10 and the orthographic projection of the channel region 2021 of the first transistor T1 on the substrate 10, the second spacing dimension d2 between the second active regions 202 can be appropriately increased to meet different design requirements within a limited layout space.

[0109] Figure 7 A schematic diagram of another structure of the first active layer provided in an embodiment of the present invention, referring to Figure 7 On the basis of the above embodiment, optionally, the orthographic projection of the channel region 2012 of the auxiliary transistor on the substrate 10 is separated from the orthographic projection of the channel region 2021 of the first transistor T1 on the substrate 10. In the same pixel unit 100, when the first spacing dimension d1 between the first active regions 201 in two pixel circuits is fixed, by separating the orthographic projection of the channel region 2012 of the auxiliary transistor on the substrate 10 from the orthographic projection of the channel region 2021 of the first transistor T1 on the substrate 10, the second spacing dimension d2 between the second active regions 202 can be appropriately reduced, so as to further save the occupied space of the first active layer 20, which is conducive to realizing a high PPI design.

[0110] Figure 8 A schematic diagram of another structure of the first active layer provided in an embodiment of the present invention, referring to Figure 5 and Figure 8On the basis of the above embodiments, optionally, the pixel circuit includes two auxiliary transistors, namely, a second transistor T2 and a third transistor T3, a channel region 2111 of the second transistor T2 and a channel region 2113 of the third transistor T3 extend along the second direction Y, and the channel region 2111 of the second transistor T2 and the channel region 2112 of the third transistor T3 are connected. That is, the second transistor T2, the third transistor T3 and the driving transistor T1 are three transistors whose channel regions are connected together by adopting the same process, and the first transistor T1 is used to write the data voltage Vdata to the gate of the driving transistor in the data writing stage.

[0111] In this embodiment, the channel region 2011 of the driving transistor T0 is connected to the channel region 2111 of the second transistor T2 and the channel region 2112 of the third transistor T3. In the data writing stage, the data voltage Vdata is written through the first transistor T1, the second transistor T2, the driving transistor T0 and the eighth transistor T8. Since the channel region 2011 of the driving transistor T0 is connected to the channel region 2111 of the second transistor T2, the channel length of the driving transistor T0 as a whole (the driving transistor T0 and the second transistor T2 as a whole form a new driving transistor) can be increased, which is conducive to making the threshold voltage of the new driving transistor more stable and improving the threshold voltage compensation effect. In the light emitting stage, the third transistor T3 and the driving transistor T0 jointly form a transistor with a channel region with a larger length to reduce the overall width-to-length ratio of the driving transistor T0, thereby increasing the driving capability of the driving transistor T0, which is more conducive to grayscale development and improving the display effect.

[0112] Optionally, an orthographic projection of a channel region 2111 of the second transistor T2 on the substrate 10 and an orthographic projection of a channel region 2112 of the third transistor T3 on the substrate 10 at least partially overlap, so as to further save the layout space occupied by the first active layer 20 .

[0113] In an optional implementation manner provided in this embodiment, the widths of the channel region 2111 of the second transistor T2 and the channel region 2112 of the third transistor T3 are equal (both are W1), and the lengths of the channel region 2111 of the second transistor T2 and the channel region 2112 of the third transistor T3 are equal, so that the sizes of the channel regions of the second transistor T2 and the third transistor T3 can be the same, and the parameters of the two are completely consistent, so as to improve the display effect.

[0114] Optionally, since the first active layer 20 at the second transistor T2 and the third transistor T3 is bent, the channel region 2111 of the second transistor T2 and the channel region 2112 of the third transistor T3 can be appropriately enlarged, so that the width of the channel region 2111 of the second transistor T2 and the channel region 2112 of the third transistor T3 is greater than the width of the channel region 2021 of the first transistor T1, and less than or equal to the width of the channel region 2011 of the driving transistor T0, that is, W1≤W2. By controlling the width of the channel region, the length of the channel region of the new driving transistor can be effectively increased.

[0115] Of course, in other embodiments, the width of the channel region 2111 of the second transistor T2 and the channel region 2112 of the third transistor T3 may also be greater than the width of the channel region 2011 of the driving transistor T0, and may be adjusted according to actual process technology and requirements as long as the width-to-length ratio of the new driving transistor can be reduced.

[0116] Fig. 9 A schematic diagram of another display panel layout structure provided by an embodiment of the present invention, Fig.10 Another display panel provided by the embodiment of the present invention is shown in FIG. Figure 5 , Fig. 9 and Fig.10 On the basis of the above embodiments, optionally, the display panel further includes a data line (not shown in the figure), the data line is connected to the first electrode of the first transistor T1 through the first type via K1, the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 through the first active layer 20, the second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1 through the first active layer 20, and the first transistor T1 is used to transmit the data voltage Vdata on the data line to the gate G of the driving transistor T0 in response to the first scanning signal SP1.

[0117] Optionally, the pixel circuit also includes a fourth transistor T4 and a fifth transistor T5, and the display panel also includes a third signal line SL3, a first connecting line L1 and a power line. The third signal line SL3 extends along the first direction X, and the overlapping position of the third signal line SL3 and the first active layer 20 respectively forms the gate of the fourth transistor T4 and the gate of the fifth transistor T5. The first electrode of the fourth transistor T4 is connected to the power line through the first connecting line L1, the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3 through the first active layer 20, the second electrode of the third transistor T3 is connected to the first electrode of the driving transistor T0 through the first active layer 20, the second electrode of the driving transistor T0 is connected to the first electrode of the fifth transistor T5 through the first active layer 20, and the second electrode of the fifth transistor T5 is connected to the light-emitting element (the light-emitting element may be an OLED).

[0118] Specifically, the fourth transistor T4 and the fifth transistor T5 are light-emitting control transistors, which are used to respond to the light-emitting control signal EM to turn on in the light-emitting stage to control the driving current generated by the driving transistor T0 to drive the light-emitting element to emit light. Among them, the fourth transistor T4 is connected to the power line in a cross-line bridge manner, and the fifth transistor T5 can be directly connected to the light-emitting element through the first active layer 20 and the via hole. Fig.11 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Fig.10 The cross-sectional structure of the display panel shown along the cutting line BB' is shown in FIG. Fig.10 and Fig.11 , the first electrode of the fourth transistor T4 is connected to one end of the first connection line L1 through the first type via K1, and the power line is connected to the other end of the first connection line L1 through the first type via K1 or directly. For example, if the power line and the first connection line L1 are arranged in the same layer, the power line can be directly connected to the first connection line L1 (that is, the power line and the first connection line L1 are the same line), and the first connection line L1 is connected to the first electrode of the fourth transistor T4 through the first type via, and the first electrode of the fourth transistor T4 is located in the first active layer 20. When the power line and the first connection line L1 are arranged in different layers, the first connection line L1 plays a bridging role, and one end of the first connection line L1 is punched to connect to the first electrode of the fourth transistor T4, and the other end is punched to connect to the power line.

[0119] Optionally, continue to refer to Figures 9 to 11 The pixel circuit further includes a storage capacitor Cst, a first plate C1 of the storage capacitor Cst is connected to the gate G of the driving transistor T0, and a second plate C2 of the storage capacitor Cst is connected to the other end of the first connection line L1 through a first type via K1. The gate G of the driving transistor T0 can be reused as the first plate C1 of the storage capacitor Cst. The first plate C1 and the second plate C2 of the storage capacitor Cst are arranged in different layers, and the overlapping part of the two forms the storage capacitor Cst.

[0120] Optionally, since the second plate C2 of the storage capacitor Cst is connected to the power line to access the first power supply voltage VDD, the signals accessed by the second plates C2 of the two storage capacitors Cst in the same pixel unit 100 are consistent and can be connected together. In the same pixel unit 100, the second plates C2 of the two storage capacitors Cst can be connected as an integrated structure, which is beneficial to reducing the number of vias in the display panel. Here, the second plate C2 of the storage capacitor Cst is connected to the first connection line L1 through the first type via K1 to connect to the power line.

[0121] Optionally, the multi-layer conductive layer further includes a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer (not shown in the figure), the second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 10, the third conductive layer M3 is located on the side of the second conductive layer M2 away from the substrate 10, and the fourth conductive layer is located on the side of the third conductive layer M3 away from the substrate 10. Among them, a first insulating layer 11 is arranged between the first active layer 20 and the first conductive layer M1, a second insulating layer 12 is arranged between the first conductive layer M1 and the second conductive layer M2, a third insulating layer 13, a fourth insulating layer 14 and a fifth insulating layer 15 are arranged between the second conductive layer M2 and the third conductive layer M3 (in other embodiments, there may be only one insulating layer), a sixth insulating layer 16 is arranged between the third conductive layer M3 and the fourth conductive layer, and a seventh insulating layer 17 is also arranged on the side of the fourth conductive layer away from the substrate 10.

[0122] In this embodiment, the third signal line SL3 and the first plate C1 of the storage capacitor Cst are located in the first conductive layer M1, the second plate C2 of the storage capacitor Cst is located in the second conductive layer M2, the first connection line L1 is located in the third conductive layer M3, and the data line and the power line are located in the fourth conductive layer.

[0123] Optionally, the orthographic projection of the third signal line SL3 on the substrate 10 is located on a side of the orthographic projection of the first signal line SL1 on the substrate 10 away from the orthographic projection of the second signal line SL2 on the substrate 10, which facilitates layout.

[0124] Continue to refer Fig.10 The pixel circuit further includes a sixth transistor T6, and the display panel further includes a fourth signal line SL4 and a first initialization signal line RL1. The fourth signal line SL4 and the first initialization signal line RL1 both extend along the first direction X. The fourth signal line SL4 overlaps the first active layer 20 to form a gate of the sixth transistor T6. The first electrode of the sixth transistor T6 is connected to the first initialization signal line RL1 through the first type via K1, and the second electrode of the sixth transistor T6 is connected to the light emitting element through the first type via K1. The sixth transistor T6 is used to transmit the first initialization voltage Vrefn2 to the first electrode of the light emitting element in response to the second scanning signal SP2 in the initialization stage to initialize the first electrode of the light emitting element.

[0125] The orthographic projection of the fourth signal line SL4 on the substrate 10 is located on a side of the orthographic projection of the third signal line SL3 on the substrate 10 away from the orthographic projection of the first signal line SL1 on the substrate 10 .

[0126] Optionally, the first initialization signal line RL1 is located in the third conductive layer M3, and the fourth signal line SL4 is located in the first conductive layer M1. The orthographic projection of the first initialization signal line RL1 on the substrate 10 is located on a side of the orthographic projection of the fourth signal line SL4 on the substrate 10 away from the orthographic projection of the first signal line SL1 on the substrate 10.

[0127] Optionally, the pixel circuit further includes an eighth transistor T8, the display panel further includes a second active layer 30 and a fifth signal wire SL5, the fifth signal wire SL5 extends along the first direction X, the fifth signal wire SL5 and the second active layer 30 overlap to form a first gate of the eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the second electrode of the driving transistor T0 through the third connecting wire L3, and the second electrode of the eighth transistor T8 is connected to the gate of the driving transistor T0 through the fourth connecting wire L4. Wherein, the material of the second active layer 30 is metal oxide, and the eighth transistor T8 is an N-type transistor, which is conducive to reducing the leakage current of the driving transistor T0. The eighth transistor T8 is used to compensate the threshold voltage of the driving transistor T0 in response to the third scanning signal SN2 in the compensation phase (concurrently with the data writing phase). Wherein, the second active layer 30 extends along the second direction Y.

[0128] Optionally, the eighth transistor T8 can be a vertical dual-gate transistor. The display panel also includes a sixth signal line SL6, which extends along the first direction X, and the sixth signal line SL6 overlaps the second active layer 30 to form a second gate of the eighth transistor T8; wherein the first gate of the eighth transistor T8 is a top gate, and the second gate of the eighth transistor T8 is a bottom gate, or the first gate of the eighth transistor T8 is a bottom gate, and the second gate of the eighth transistor T8 is a top gate. The top gate and the bottom gate of the eighth transistor T8 are connected to the same signal. In this way, during the driving process, current can flow through the upper and lower surfaces of the channel of the eighth transistor T8, thereby increasing the driving current, which is conducive to quickly realizing the on-off control of the eighth transistor T8, and the dual-gate structure is adopted, which can effectively reduce the size of the transistor compared to the single-gate structure.

[0129] The orthographic projection of the sixth signal line SL6 on the substrate 10 at least partially intersects with the orthographic projection of the fifth signal line SL5 on the substrate 10 to form a vertical dual-gate transistor.

[0130] Fig.12 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Fig.10 The cross-sectional structure of the display panel along the cutting line CC' is shown in FIG. Figure 10-12The first electrode of the eighth transistor T8 is connected to one end of the third connection line L3 through the second type via K2, the second electrode of the driving transistor T0 is connected to the other end of the third connection line L3 through the first type via K1, the second electrode of the eighth transistor T8 is connected to one end of the fourth connection line L4 through the second type via K2, and the gate G of the driving transistor T0 is connected to the other end of the fourth connection line L4 through the first type via K1.

[0131] Optionally, the multi-layer conductive layer further includes a fifth conductive layer M5, the fifth conductive layer M5 is located between the second conductive layer M2 and the third conductive layer M3, and the fifth insulating layer 15 covers the fifth conductive layer M5. The fifth signal line SL5 and the sixth signal line SL6 are arranged in different layers, for example, the fifth signal line SL5 is located in the second conductive layer M2, and the sixth signal line SL6 is located in the fifth conductive layer M5. The second active layer 30 is located between the second conductive layer M2 and the fifth conductive layer M5.

[0132] Optionally, the orthographic projections of the fifth signal line SL5 and the sixth signal line SL6 on the substrate 10 are both located between the orthographic projection of the first signal line SL1 and the orthographic projection of the second signal line SL2 on the substrate 10, which is beneficial for saving layout space while forming the eighth transistor T8.

[0133] In this embodiment, the second type via K2 (red via) is a via leading to the second active layer 30. For example, the second type via K2 leads from the third conductive layer M3 to the second active layer 30. The first type via K1 (blue via) is another via. The first type via K1 can lead from the third conductive layer M3 to the first active layer 20, or from the third conductive layer M3 to the second conductive layer M2.

[0134] Continue to refer Fig.10 and Fig.12 The pixel circuit further includes a ninth transistor T9, and the display panel further includes a seventh signal line SL7 and a third initialization signal line RL3. The third initialization signal line RL3 and the seventh signal line SL7 extend along the first direction X. The seventh signal line SL7 overlaps the second active layer 30 to form a first gate of the ninth transistor T9. The first electrode of the ninth transistor T9 is connected to the third initialization signal line RL3 through the fifth connection line L5, and the second electrode of the ninth transistor T9 is connected to the second electrode of the eighth transistor T8 through the second active layer 30.

[0135] Specifically, the first electrode of the ninth transistor T9 is connected to one end of the fifth connection line L5 through the second type via K2, and the third initialization signal line RL3 is connected to the other end of the fifth connection line L5 through the second type via K2. The ninth transistor T9 is used to transmit the third initialization voltage Vrefn1 to the gate G of the driving transistor T0 in response to the fourth scanning signal SN1 in the initialization stage to initialize the gate G of the driving transistor T0.

[0136] The display panel further includes an eighth signal line SL8, the eighth signal line SL8 extends along the first direction X, and the eighth signal line SL8 overlaps with the second active layer 30 to form a second gate of a ninth transistor T9; wherein the first gate of the ninth transistor T9 is a top gate, and the second gate of the ninth transistor T9 is a bottom gate, or the first gate of the ninth transistor T9 is a bottom gate, and the second gate of the ninth transistor T9 is a top gate. The ninth transistor T9 adopts a vertical dual-gate structure, and has the same beneficial effects as the eighth transistor T8, which will not be described in detail.

[0137] The orthographic projection of the eighth signal line SL8 on the substrate 10 at least partially overlaps with the orthographic projection of the seventh signal line SL7 on the substrate 10 to form a vertical dual-gate transistor, which is beneficial to saving layout space.

[0138] Optionally, the orthographic projections of the eighth signal line SL8 and the seventh signal line SL7 on the substrate 10 are both located on a side of the orthographic projection of the second signal line SL2 on the substrate 10 away from the orthographic projection of the first signal line SL1 on the substrate 10 .

[0139] The eighth signal line SL8 and the third initialization signal line RL3 are both located in the fifth conductive layer M5, and the seventh signal line SL7 is located in the second conductive layer.

[0140] Optionally, the orthographic projection of the third initialization signal line RL3 on the substrate 10 is located on a side of the orthographic projection of the eighth signal line SL8 on the substrate 10 away from the orthographic projection of the first signal line SL1 on the substrate 10 .

[0141] RL3' is a third initialization signal line connected to the next row of pixel circuits. By overlapping the orthographic projection of the third initialization signal line RL on the substrate 10 with the orthographic projection of the fourth signal line SL4 on the substrate 10, it is beneficial to save layout space, thereby improving layout space utilization.

[0142] Fig.13 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.13On the basis of the above embodiments, the pixel circuit provided in this embodiment further includes a seventh transistor T7, which is connected to the first electrode of the third transistor M3 and is used to transmit the second initialization voltage Vrefp to the first electrode of the second transistor M2, so that the first electrode and the second electrode of the third transistor M3 and the first electrode and the second electrode of the driving transistor M0 have the same potential, which is beneficial to improving the transient characteristics of the driving transistor T0, and further beneficial to improving the problems of low-frequency flicker and afterimage, and improving the display effect.

[0143] Fig.14 A schematic diagram of another display panel layout structure provided by an embodiment of the present invention, Fig.15 A schematic diagram of another display panel layout structure provided by an embodiment of the present invention, referring to Figure 13-Figure 15 The display panel further includes a second initialization signal line RL2 and a second connection line L2. The fourth signal line SL4 and the first active layer 20 overlap to form a gate of the seventh transistor T7. The first electrode of the seventh transistor T7 is connected to the second initialization signal line RL2 through the first type via K1, and the second electrode of the seventh transistor T7 is connected to the first electrode of the third transistor T3 through the second connection line L2. For example, the second electrode of the seventh transistor T7 is connected to one end of the second connection line L2 through the first type via K1, and the first electrode of the third transistor T3 is connected to the other end of the second connection line L2 through the first type via K1.

[0144] Optionally, the orthographic projection of the second initialization signal line RL2 on the substrate 10 is located between the orthographic projection of the third signal line SL3 on the substrate 10 and the orthographic projection of the first initialization signal line RL1 on the substrate 10, and the orthographic projection of the second initialization signal line RL2 on the substrate 10 is located on the side of the orthographic projection of the third signal line RL3 on the substrate 10 away from the orthographic projection of the first signal line SL1 on the substrate 10. The orthographic projection of the second initialization signal line RL2 on the substrate 10 at least partially overlaps with the orthographic projection of the fourth signal line RL4 on the substrate 10, which is beneficial to saving layout space. Among them, the orthographic projection of the second connecting line L2 on the substrate 10 intersects with the orthographic projection of the third signal line SL3 on the substrate 10, which is convenient for layout.

[0145] Optionally, the second connection line L2 is located in the third conductive layer M3, and the second initialization signal line RL2 is located in the third conductive layer M3.

[0146] It should be noted that the extension direction of each signal line mentioned in the embodiment of the present invention is the overall extension direction of the signal line on the display panel. When it is refined to the structure in a pixel circuit, in order to avoid the wiring positions of each signal line and related structures, the signal line may have some bending and step areas.

[0147] Fig.16 Another structural schematic diagram of the first active layer provided by an embodiment of the present invention, Fig.17 Another structural schematic diagram of the first active layer provided by an embodiment of the present invention, referring to Figure 8 , Fig.16 Fig.17 , in this embodiment, the channel region 2011 of the driving transistor T0 can be in an "Ω" shape (as shown in Figure 8 ), or can be in a "one" shape (as shown in Fig.16 ), or can be in a Z shape (as shown in Fig.17 ). By different channel shapes, different device sizes can be adjusted to meet different design requirements.

[0148] In the actual manufacturing process, the distances at the two corner positions of the channel region are relatively close. Due to equipment precision reasons, arc angles are formed at the corner positions, thus changing the aspect ratio of the transistor and affecting the actual size and parameters of the transistor. In this embodiment, the channel region 2011 of the driving transistor T0 is provided with grooves at the corner positions on the extension path. During the manufacturing process, the groove positions will be filled to achieve compensation of the channel region, so that the graphic structure made by the actual factory equipment is a right angle at the corner positions, which will not affect the aspect ratio of the transistor, and thus the parameters of the driving transistor T0 are more in line with the design values. For example, the grooves can be realized by digging holes at the corner positions.

[0149] Of course, in other embodiments, grooves can be provided at all corner positions of the first active layer 20 and the second active layer 30, so that the parameters of all transistors are in line with the design values.

[0150] Optionally, an embodiment of the present invention further provides a display device, and this display device includes the display panel provided by any embodiment of the present invention. Therefore, this display device also has the beneficial effects described in any of the above embodiments. Fig.18 A structural schematic diagram of a display device provided by an embodiment of the present invention. In this embodiment, the display device 200 can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: display panels in products such as televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control devices, touch interaction terminals, etc. The embodiments of the present invention do not make special limitations on this.

[0151] It should be understood that various forms of processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0152] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A first active layer and a multi-layer conductive layer are arranged on one side of the substrate, wherein the first active layer and the multi-layer conductive layer constitute at least one pixel unit, and the pixel unit includes two pixel circuits with mirror symmetry; The first active layer includes a first active area and a second active area, the multi-layer conductive layer includes a first conductive layer, the first conductive layer is located on a side of the first active layer away from the substrate, the first conductive layer includes a first signal line and a second signal line, the orthographic projection of the first signal line on the substrate covers the orthographic projection of the first active area on the substrate, and the orthographic projection of the second signal line on the substrate covers the orthographic projection of the second active area on the substrate; In the same pixel unit, the orthographic projections of the first signal wirings in the two pixel circuits on the substrate are separated, and the orthographic projections of the second signal wirings in the two pixel circuits on the substrate are overlapped; Wherein, in the same pixel unit, a first spacing dimension between the first active areas in two pixel circuits is greater than a second spacing dimension between the second active areas.

2. The display panel according to claim 1, characterized in that: The two pixel circuits in the same pixel unit are arranged along a first direction, the first signal wiring and the second signal wiring are arranged along a second direction and extend along the first direction, and the first direction intersects with the second direction; In the first direction, the first active areas of two pixel circuits in the same pixel unit are adjacent; Preferably, the second active area and the first active area are located on the same side of the pixel circuit; Preferably, in the first direction, the first spacing size is greater than or equal to 4um, and the second spacing size is greater than or equal to 2um; Preferably, an orthographic projection of the first signal trace on the substrate is separated from an orthographic projection of the second signal trace on the substrate.

3. The display panel according to claim 1, characterized in that: The orthographic projection area of ​​the first signal wiring on the substrate is larger than the orthographic projection area of ​​the first active region on the substrate; Preferably, at a position close to a midline of the pixel unit, an edge of the first signal wiring in the same pixel circuit exceeds an edge of the first active area by at least 1 um.

4. The display panel according to claim 1, characterized in that: The pixel circuit includes a driving transistor, at least one auxiliary transistor and a first transistor; The first active region includes a channel region of the driving transistor and a channel region of the auxiliary transistor, and the channel region of the driving transistor is connected to the channel region of the auxiliary transistor; The second active region includes a channel region of the first transistor, and the channel region of the first transistor is connected to the auxiliary transistor through the first active layer; Preferably, an orthographic projection of the channel region of the auxiliary transistor on the substrate partially overlaps with an orthographic projection of the channel region of the first transistor on the substrate; Or, an orthographic projection of a channel region of the auxiliary transistor on the substrate is separated from an orthographic projection of a channel region of the first transistor on the substrate; Preferably, at least part of the channel region of the driving transistor extends along a first direction, the channel region of the auxiliary transistor extends along a second direction, the channel region of the first transistor extends along the second direction, and the first direction intersects the second direction; Preferably, the first direction intersects the second direction perpendicularly; Preferably, the overlapping position of the first signal line and the first active area respectively forms the gate of the auxiliary transistor and the gate of the driving transistor, and the overlapping position of the second signal line and the second active area forms the gate of the first transistor.

5. The display panel according to claim 4, characterized in that: The pixel circuit includes two auxiliary transistors, which are a second transistor and a third transistor, respectively, a channel region of the second transistor and a channel region of the third transistor extend along the second direction, and the channel region of the second transistor and the channel region of the third transistor are connected; Preferably, an orthographic projection of a channel region of the second transistor on the substrate and an orthographic projection of a channel region of the third transistor on the substrate at least partially overlap; Preferably, the widths of the channel region of the second transistor and the channel region of the third transistor are equal, and the lengths of the channel region of the second transistor and the channel region of the third transistor are equal; Preferably, the width of the channel region of the second transistor and the channel region of the third transistor is less than or equal to the width of the channel region of the driving transistor.

6. The display panel according to claim 5, characterized in that: The display panel further includes a data line, wherein the data line is connected to a first electrode of the first transistor through a first type via hole, a second electrode of the first transistor is connected to a first electrode of the second transistor through the first active layer, a second electrode of the second transistor is connected to a first electrode of the driving transistor through the first active layer, and the first transistor is used to transmit a data voltage on the data line to a gate of the driving transistor; Preferably, the pixel circuit further includes a fourth transistor and a fifth transistor, the display panel further includes a third signal line, a first connecting line and a power line, the third signal line extends along the first direction, the third signal line and the first active layer overlap position respectively form the gate of the fourth transistor and the gate of the fifth transistor, the first electrode of the fourth transistor is connected to the power line through the first connecting line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor through the first active layer, the second electrode of the third transistor is connected to the first electrode of the driving transistor through the first active layer, the second electrode of the driving transistor is connected to the first electrode of the fifth transistor through the first active layer, and the second electrode of the fifth transistor is connected to the light emitting element; Preferably, the first electrode of the fourth transistor is connected to one end of the first connection line through the first type via hole, and the power line is connected to the other end of the first connection line through the first type via hole or directly; Preferably, the pixel circuit further comprises a storage capacitor, a first plate of the storage capacitor is connected to the gate of the driving transistor, and a second plate of the storage capacitor is connected to the other end of the first connecting line through the first type of via hole; Preferably, the multi-layer conductive layer further comprises a second conductive layer, a third conductive layer and a fourth conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate, the third conductive layer is located on a side of the second conductive layer away from the substrate, and the fourth conductive layer is located on a side of the third conductive layer away from the substrate; Preferably, the third signal wiring and the first plate of the storage capacitor are located on the first conductive layer, and the second plate of the storage capacitor is located on the second conductive layer; Preferably, the first connecting line is located in the third conductive layer, and the data line and the power line are located in the fourth conductive layer; Preferably, the orthographic projection of the third signal routing line on the substrate is located on a side of the orthographic projection of the first signal routing line on the substrate away from the orthographic projection of the second signal routing line on the substrate.

7. The display panel according to claim 6, characterized in that: The pixel circuit further includes a sixth transistor, and the display panel further includes a fourth signal line and a first initialization signal line, the fourth signal line and the first initialization signal line both extend along the first direction, the fourth signal line overlaps the first active layer to form a gate of the sixth transistor, a first electrode of the sixth transistor is connected to the first initialization signal line through the first type of via hole, and a second electrode of the sixth transistor is connected to the light-emitting element through the first type of via hole; Preferably, the orthographic projection of the fourth signal routing line on the substrate is located on a side of the orthographic projection of the third signal routing line on the substrate away from the orthographic projection of the first signal routing line on the substrate; Preferably, the first initialization signal line is located in the third conductive layer, and the fourth signal line is located in the first conductive layer; Preferably, the pixel circuit further includes a seventh transistor, the display panel further includes a second initialization signal line and a second connection line, the fourth signal line and the first active layer overlap position also form a gate of the seventh transistor, the first electrode of the seventh transistor is connected to the second initialization signal line through the first type of via hole, and the second electrode of the seventh transistor is connected to the first electrode of the third transistor through the second connection line; Preferably, the second electrode of the seventh transistor is connected to one end of the second connection line through the first type via hole, and the first electrode of the third transistor is connected to the other end of the second connection line through the first type via hole; Preferably, the orthographic projection of the second initialization signal line on the substrate is located between the orthographic projection of the third signal line on the substrate and the orthographic projection of the first initialization signal line on the substrate, and the orthographic projection of the second initialization signal line on the substrate is located on a side of the orthographic projection of the third signal line on the substrate away from the orthographic projection of the first signal line on the substrate; Preferably, the second connecting line is located in the third conductive layer, and the second initialization signal line is located in the third conductive layer; Preferably, the orthographic projection of the second initialization signal line on the substrate at least partially overlaps with the orthographic projection of the fourth signal line on the substrate; Preferably, an orthographic projection of the second connecting line on the substrate intersects with an orthographic projection of the third signal line on the substrate.

8. The display panel according to claim 6, characterized in that: The pixel circuit further includes an eighth transistor, the display panel further includes a second active layer and a fifth signal wiring, the fifth signal wiring extends along the first direction, the fifth signal wiring and the second active layer overlap to form a first gate of the eighth transistor, the first electrode of the eighth transistor is connected to the second electrode of the driving transistor through a third connecting line, and the second electrode of the eighth transistor is connected to the gate of the driving transistor through a fourth connecting line; Preferably, the first electrode of the eighth transistor is connected to one end of the third connection line through the second type via, the second electrode of the driving transistor is connected to the other end of the third connection line through the first type via, the second electrode of the eighth transistor is connected to one end of the fourth connection line through the second type via, and the gate of the driving transistor is connected to the other end of the fourth connection line through the first type via; Preferably, the fifth signal trace is located in the second conductive layer; Preferably, the display panel further comprises a sixth signal line, the sixth signal line extends along the first direction, and the second gate of the eighth transistor is formed at a position where the sixth signal line overlaps with the second active layer; wherein the first gate of the eighth transistor is a top gate, and the second gate of the eighth transistor is a bottom gate, or the first gate of the eighth transistor is a bottom gate, and the second gate of the eighth transistor is a top gate; Preferably, the orthographic projection of the sixth signal line on the substrate at least partially overlaps with the orthographic projection of the fifth signal line on the substrate; Preferably, the fifth signal routing line and the sixth signal routing line are arranged in different layers; Preferably, the multi-layer conductive layer further includes a fifth conductive layer, the fifth conductive layer is located between the second conductive layer and the third conductive layer, and the sixth signal trace is located in the fifth conductive layer; Preferably, the second active layer is located between the second conductive layer and the fifth conductive layer; Preferably, the orthographic projections of the fifth signal routing and the sixth signal routing on the substrate are both located between the orthographic projection of the first signal routing on the substrate and the orthographic projection of the second signal routing on the substrate; Preferably, the pixel circuit further includes a ninth transistor, the display panel further includes a seventh signal line and a third initialization signal line, the third initialization signal line and the seventh signal line extend along the first direction, the seventh signal line overlaps the second active layer to form a first gate of the ninth transistor, a first electrode of the ninth transistor is connected to the third initialization signal line through a fifth connection line, and a second electrode of the ninth transistor is connected to the second electrode of the eighth transistor through the second active layer; Preferably, the first electrode of the ninth transistor is connected to one end of the fifth connection line through the second type via hole, and the third initialization signal line is connected to the other end of the fifth connection line through the second type via hole; Preferably, the seventh signal line is located in the second conductive layer, and the third initialization signal line is located in the fifth conductive layer; Preferably, the display panel further comprises an eighth signal line, the eighth signal line extends along the first direction, and the eighth signal line overlaps with the second active layer to form a second gate of the ninth transistor; wherein the first gate of the ninth transistor is a top gate, and the second gate of the ninth transistor is a bottom gate, or the first gate of the ninth transistor is a bottom gate, and the second gate of the ninth transistor is a top gate; Preferably, the eighth signal line is located in the fifth conductive layer, and an orthographic projection of the eighth signal line on the substrate at least partially overlaps with an orthographic projection of the seventh signal line on the substrate; Preferably, the orthographic projections of the eighth signal routing and the seventh signal routing on the substrate are both located on a side of the orthographic projection of the second signal routing on the substrate away from the orthographic projection of the first signal routing on the substrate; Preferably, the orthographic projection of the third initialization signal line on the substrate is located on a side of the orthographic projection of the eighth signal line on the substrate away from the orthographic projection of the first signal line on the substrate; Preferably, the second active layer extends along the second direction; Preferably, the material of the first active layer includes polysilicon, and the material of the second active layer includes metal oxide.

9. The display panel according to claim 4, characterized in that: The channel region of the driving transistor is in an "Ω" shape, a "I" shape or a Z shape; Preferably, a groove is provided at a corner position of the channel region of the driving transistor on the extension path.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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