Display panel and preparation method thereof

Abstract

The invention relates to a display panel and a preparation method thereof, the display panel comprises a substrate, a shielding layer and a driving circuit layer, the shielding layer is arranged between the substrate and the driving circuit layer and at least partially covers one side, facing the driving circuit layer, of the substrate, and a cathode layer in the driving circuit layer is connected with the shielding layer. The cathode layer is arranged on the substrate to provide cathode voltage for the shielding layer, so that the shielding layer has a stable shielding electric field provided by the cathode layer, a polarization electric field generated in the substrate can be shielded, the influence of the polarization electric field on the driving circuit layer is avoided, and the ghosting problem of the display panel is solved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a display panel and a method for manufacturing the display panel. Background Art

[0002] In the field of display panel technology, when a display panel displays a high-contrast pattern, such as a black-and-white checkerboard pattern, the white and black areas will generate high and low charge states in the pixels, respectively. These charge differences lead to the capture and release of carriers at the interface between the drive circuit layer and the substrate of the display panel. Due to the capture and release of carriers, the threshold voltage (Vth) of the TFT (thin film transistor) in the drive circuit layer is changed, causing the substrate to form an additional electric field due to charge accumulation, which further causes afterimages in the display panel. Summary of the invention

[0003] Based on this, it is necessary to provide a display panel and a method for manufacturing the display panel to address the above problems.

[0004] In a first aspect, the present application provides a display panel comprising a substrate, a shielding layer and a driving circuit layer, wherein the shielding layer is arranged between the substrate and the driving circuit layer and at least partially covers a side of the substrate facing the driving circuit layer, and a cathode layer in the driving circuit layer is connected to the shielding layer to provide a cathode voltage to the shielding layer.

[0005] In one embodiment, the transmittance of the shielding layer is greater than or equal to 60%;

[0006] Preferably, the thickness of the shielding layer is 15Å~25Å;

[0007] Preferably, the shielding layer is doped with a preset element;

[0008] Preferably, the preset element includes at least one of boron and phosphorus;

[0009] Preferably, the shielding layer includes an amorphous silicon layer or an ITO layer.

[0010] In one embodiment, the shielding layer covers the entire side of the substrate facing the driving circuit layer.

[0011] In one embodiment, the driving circuit layer includes a cathode layer and a pixel circuit layer, the pixel circuit layer is arranged on a side of the shielding layer away from the substrate, the cathode layer is arranged on a side of the pixel circuit layer away from the shielding layer, and provides a cathode voltage to the shielding layer through the pixel circuit layer;

[0012] Preferably, the pixel circuit layer comprises a first groove, the first groove extending from a surface of the pixel circuit layer facing the cathode layer to a surface of the pixel circuit layer facing the shielding layer, and part of the cathode layer is arranged on an inner wall of the first groove to provide the cathode voltage to the shielding layer;

[0013] Preferably, the shielding layer also includes a second groove, which extends from the surface of the shielding layer facing the pixel circuit layer to the surface of the shielding layer facing the substrate, and the second groove is connected to the first groove. Part of the cathode layer is also arranged on the side wall of the second groove to provide the cathode voltage to the shielding layer.

[0014] In one embodiment, the first groove includes a first partial groove and a second partial groove, the first partial groove is located on the top of the second partial groove, and part of the cathode layer is provided on the surface of the first partial groove and the second partial groove, so as to provide a cathode voltage to the shielding layer through the first partial groove and the second partial groove;

[0015] Preferably, the first portion of grooves and the second portion of grooves have different sizes;

[0016] Preferably, the opening size of the second portion of the groove is 8um~20um.

[0017] In a second aspect, the present application further provides a method for preparing a display panel, the method comprising:

[0018] providing a substrate;

[0019] Depositing a shielding layer on the surface of the substrate so that the shielding layer at least partially covers the surface of the substrate;

[0020] A driving circuit layer is prepared on a side of the shielding layer away from the substrate, so that the cathode layer in the driving circuit layer is connected to the shielding layer to provide a cathode voltage to the shielding layer.

[0021] In one embodiment, depositing a shielding layer on the surface of the substrate comprises:

[0022] The shielding layer is prepared on the entire surface of the substrate so that the shielding layer covers the entire surface of the substrate.

[0023] In one embodiment, before preparing the driving circuit layer on the side of the shielding layer facing away from the substrate, the method further includes:

[0024] doping a predetermined element into the shielding layer;

[0025] Preferably, the preset element includes at least one of boron and phosphorus.

[0026] In one embodiment, a driving circuit layer is prepared on a side of the shielding layer facing away from the substrate, comprising:

[0027] Depositing a pixel circuit layer on a side of the shielding layer facing away from the substrate;

[0028] Etching a first groove from a surface of the pixel circuit layer facing the cathode layer to a surface of the pixel circuit layer facing the shielding layer;

[0029] Depositing a cathode layer on a side of the pixel circuit layer away from the shielding layer and on an inner wall of the first groove, so that the cathode layer passes through the pixel circuit layer to provide a cathode voltage to the shielding layer;

[0030] Preferably, before depositing the cathode layer on the side of the pixel circuit layer away from the shielding layer and the inner wall of the first groove, the method further comprises:

[0031] Etching a second groove from the surface of the shielding layer facing the pixel circuit layer to the surface of the shielding layer facing the substrate, wherein the second groove is connected to the first groove;

[0032] Depositing a cathode layer on a side of the pixel circuit layer away from the shielding layer and an inner wall of the first groove includes:

[0033] The cathode layer is deposited on a portion of the pixel circuit layer away from the shielding layer and on inner walls of the first groove and the second groove.

[0034] In one embodiment, etching a first groove from a surface of the pixel circuit layer facing the cathode layer to a surface of the pixel circuit layer facing the shielding layer comprises:

[0035] Etching a first portion of the groove from the surface of the pixel circuit layer facing the cathode layer to the surface of the pixel circuit layer facing the shielding layer;

[0036] Etching a second portion of the groove from a side of the first portion of the groove away from the pixel circuit layer in the thickness direction of the pixel circuit layer toward the direction of the pixel circuit layer toward the shielding layer;

[0037] Preferably, the first portion groove and the second portion groove have different sizes.

[0038] The above-mentioned display panel and the method for preparing the display panel, the display panel includes a substrate, a shielding layer and a driving circuit layer, the shielding layer is arranged between the substrate and the driving circuit layer and at least partially covers the side of the substrate facing the driving circuit layer, the cathode layer in the driving circuit layer is connected to the shielding layer to provide a cathode voltage to the shielding layer, so that the shielding layer has a stable shielding electric field provided by the cathode layer, which can shield the polarization electric field generated in the substrate to avoid its influence on the driving circuit layer, thereby improving the afterimage problem of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 is a schematic structural diagram of a display panel in an embodiment of the present application;

[0041] FIG. 2 ( a ) is a schematic diagram of the structure of a first groove in an embodiment of the present application;

[0042] FIG2( b ) is a second schematic diagram of the structure of the first groove in one embodiment of the present application;

[0043] FIG. 2 ( c ) is a third structural schematic diagram of the first groove in one embodiment of the present application;

[0044] Figure 3 This is a schematic diagram of the structure of the second groove in one embodiment of the present application;

[0045] Figure 4 is a schematic diagram of a process of manufacturing a display panel in an embodiment of the present application;

[0046] Figure 5 It is a schematic diagram of a process of preparing a driving circuit layer on a side of a shielding layer facing away from a substrate in one embodiment of the present application.

[0047] Description of Figure Numbers:

[0048] Substrate: 110; shielding layer: 120; second groove: 121; driving circuit layer: 130; cathode layer: 131; pixel circuit layer: 132; first ILD layer boundary: 1321; second ILD layer boundary: 1322; organic material layer: 321; first buffer layer: 322; second buffer layer: 323; first electrode layer: 324; gate insulating layer: 325; capacitor dielectric layer: 3261; second electrode layer: 3262; first metal layer: 3263; first Second metal layer: 327; dielectric layer: 328; planarization layer: 3291; third electrode layer: 3292; fourth electrode layer: 3293; fifth electrode layer: 3294; ​​sixth electrode layer: 3295; first conductive layer: 3301; second conductive layer: 3302; pixel layer: 3311; spacer layer: 3312; pixel defining layer: 3313; seventh electrode layer: 332; first groove: 133; first portion of groove: 1331; second portion of groove: 1332. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0050] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0052] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0053] See also Figure 1 , Figure 1 A schematic diagram of the structure of a display panel in an embodiment of the present application is shown. The display panel in this embodiment includes a substrate 110, a shielding layer 120 and a driving circuit layer 130. The shielding layer 120 is arranged between the substrate 110 and the driving circuit layer 130 and at least partially covers the side of the substrate 110 facing the driving circuit layer 130. The cathode layer 131 in the driving circuit layer 130 is connected to the shielding layer 120 to provide a cathode voltage to the shielding layer 120.

[0054] The substrate 110 may be made of polyimide (PI), which has extremely high heat resistance and ultra-low thermal expansion coefficient, and can ensure the stability of the display screen during manufacturing. The shielding layer 120 is made of a transparent conductive layer material, which has a stable shielding electric field under the action of the cathode layer 131 in the driving circuit layer 130 while ensuring transmittance, thereby isolating the driving circuit layer 130 from the substrate 110 and shielding the polarization electric field generated in the substrate 110.

[0055] The driving circuit layer 130 may include a cathode layer 131 and a pixel circuit layer 132. The cathode layer 131 refers to a conductive film layer that provides a cathode voltage ELVSS. Its preparation material may be Ti / Al / Ti (titanium aluminum titanium), but is not limited thereto. The pixel circuit layer 132 includes a plurality of functional film layers to realize the display function. Depending on the type of display panel, the structure of the corresponding pixel circuit is also different. For example, in this embodiment, the structure of the pixel circuit layer 132 including a plurality of functional film layers including a thin film transistor (TFT) is shown, such as Figure 1As shown, the pixel circuit layer 132 may include an organic material layer 321 (such as a Blue Emitting Layer, BL layer), a first buffer layer 322 (such as SiNx, a silicon nitride film), a second buffer layer 323 (such as SiOx, a silicon oxide film), a first electrode layer 324 (such as including a Source source region, an ACT channel region, and a Drain drain region), a gate insulating layer (Gate Insulator, GI) 325, a capacitor dielectric layer (C Insulator, CI) 3261, a second electrode layer 3262 (such as an electrode receiving a dimming signal EM), a first metal layer 3263, a second metal layer 327, a dielectric layer (Inter-Layer Dielectric, ILD) 328, and a planarization layer. The pixel circuit layer 132 may include a first electrode layer 3291 (e.g., a source electrode Source, S), a fourth electrode layer 3293 (e.g., a drain electrode Drain, D), a fifth electrode layer 3294 (e.g., an electrode for receiving a positive power supply voltage ELVDD), a sixth electrode layer 3295 (e.g., a gate electrode Gate, G), a first conductive layer 3301 (e.g., ITO / Ag / ITO, tin-doped indium oxide, ITO / silver, Ag), a second conductive layer 3302 (e.g., an anode ANODE: ITO / Ag / ITO), a pixel layer 3311 (e.g., OLED, Organic Light-Emitting Diode, organic light-emitting semiconductor), a spacer (Spacer, SPC) layer 3312, a pixel defining layer (Pixel Define Layer, PDL) 3313, a seventh electrode layer 332 (e.g., a cathode Cathode: Mg / Ag, magnesium / silver), etc. It can be understood that in other embodiments, the pixel circuit layer 132 may also be other structures, not limited thereto.

[0056] For example, Figure 1 Also shown are multiple areas corresponding to the display screen, such as area A, area B, area C, area D, area E, and area F. Area A may be a Cutting area, i.e., an area used to cut a large-size glass substrate to form an independent display screen during the display screen manufacturing process. Area B may be a Crack Dam area, i.e., an area in the display screen designed to prevent cracks from extending inward. Area C may be a Dam area, i.e., a cofferdam structure in the display screen. Area D may be a cathode overlap area. Area E may be a cathode overlap area + GIP (Gate in Panel), and area F may be an Active Area.

[0057] For example, Figure 1The cathode layer 131 is shown to be located in the Dam region and the cathode overlap region. When preparing the display panel in this embodiment, two-step inorganic etching can be performed at the first ILD (Inter-Layer Dielectric) layer boundary 1321 and the second ILD layer boundary 1322 to form an overlap groove, so that the cathode layer 131 is further deposited, so that the cathode layer 131 (ELVSS (Ti / Al / Ti)) at a preset position of the display panel is connected to the lower shielding layer 120 through the overlap groove, so that the lower shielding layer 120 has a cathode (ELVSS) potential, such as -3.0V.

[0058] In this embodiment, the display panel includes a substrate 110, a shielding layer 120 and a driving circuit layer 130. The shielding layer 120 is arranged between the substrate 110 and the driving circuit layer 130 and at least partially covers the side of the substrate 110 facing the driving circuit layer 130. The cathode layer 131 in the driving circuit layer 130 is connected to the shielding layer 120 to provide a cathode voltage to the shielding layer 120, so that the shielding layer 120 has a stable shielding electric field provided by the cathode layer 131, which can shield the polarization electric field generated in the substrate 110 and avoid its influence on the driving circuit layer 130, thereby improving the afterimage problem of the display panel.

[0059] It is understandable that the present application relates to a display panel. In order to improve the performance of the display panel, it is necessary to ensure that the newly added shielding layer meets certain transmittance requirements while ensuring uniformity. In one embodiment, the transmittance of the shielding layer is greater than or equal to 60%, such as the transmittance of the shielding layer can be 65%, 70%, 75%, 80%, etc., which can ensure that the display performance of the display panel meets the requirements.

[0060] In one embodiment, the thickness of the shielding layer is 15Å~25Å. For example, it can be 15Å, 16Å, 17Å, 18Å, 19Å, 20Å, 21Å, 22Å, 23Å, 24Å, 25Å, etc., but is not limited thereto. The thickness of the shielding layer of the display panel in this embodiment is 15Å~25Å, which can ensure the uniformity of the shielding layer structure while ensuring that its transmittance is greater than or equal to 60%.

[0061] The shielding layer in the present application can be a metal material layer or a non-metal material layer. The material used for the shielding layer is a transparent material layer, which is a non-metal layer, and the shielding layer covers the substrate and does not need to be patterned. In addition, in order to reduce the resistivity of the shielding layer in this embodiment, the cathode layer is used to provide a cathode voltage to the shielding layer, and the contact area between the shielding layers is increased. In addition, the resistivity of the shielding layer can also be reduced by doping the shielding layer with a preset element. In one embodiment, the shielding layer is doped with a preset element to reduce the resistivity of the shielding layer. Preferably, the preset element can be at least one of boron and phosphorus. And the doping concentration can be 10 15 ±5×10 14 , but not limited thereto. Depending on the doping element, the doping method may also be different. For example, boron may be doped by ion implantation, and phosphorus may be doped by chemical deposition, but not limited thereto.

[0062] In one embodiment, the shielding layer includes an amorphous silicon layer or an ITO layer (Indium Tin Oxide layer).

[0063] Among them, the amorphous silicon layer, also known as the a-Si layer, is a thin film made of hydrogenated amorphous silicon (a-Si:H). It can ensure a certain transmittance while having a stable shielding electric field under the action of the cathode voltage, thereby ensuring the isolation of the polarization electric field of the substrate. In addition, the amorphous silicon layer also has the advantages of small size, light weight, and low power consumption.

[0064] The ITO layer is a transparent conductive film made of tin-doped indium oxide (Indium Tin Oxide). The ITO layer has a transmittance of up to 80%-90% for visible light, making the image on the screen clearly visible. In addition, the ITO layer also has a low resistivity and is not easy to chemically react with other substances. The ITO layer can have a stable shielding electric field under the action of the cathode layer in the drive circuit layer, thereby effectively isolating the polarization electric field of the substrate.

[0065] In this embodiment, in order to ensure that the shielding layer has a certain transmittance and effectively isolate the polarization electric field of the substrate, an amorphous silicon layer or an ITO layer can be used as the shielding layer.

[0066] In one embodiment, the shielding layer covers the entire substrate on the side facing the driving circuit layer, which can ensure the shielding effect of the shielding layer, shield the polarization electric field generated in the substrate to a greater extent, and avoid its influence on the driving circuit layer, thereby further improving the afterimage problem of the display panel.

[0067] In one embodiment, continue to refer to the attached Figure 3The driving circuit layer 130 includes a cathode layer 131 and a pixel circuit layer 132. The pixel circuit layer 132 is disposed on the side of the shielding layer 120 away from the substrate 110. The cathode layer 131 is disposed on the side of the pixel circuit layer 132 away from the shielding layer 120, and provides a cathode voltage to the shielding layer 120 through the pixel circuit layer 132. In this embodiment, the cathode layer 131 is directly connected to the shielding layer 120 through the pixel circuit layer 132, which can ensure that the cathode layer 131 can continuously and stably provide the cathode voltage to the shielding layer 120, so that the shielding layer 120 has a stable shielding electric field under the action of the cathode voltage, thereby having a strong isolation capability.

[0068] In one embodiment, referring to FIG2 (a), FIG2 (a) shows a schematic diagram of the structure of the first groove 133, the pixel circuit layer 132 includes the first groove 133, the first groove 133 extends from the surface of the pixel circuit layer 132 facing the cathode layer 131 to the surface of the pixel circuit layer 132 facing the shielding layer 120, and part of the cathode layer 131 is arranged on the inner wall of the first groove 133 to provide a cathode voltage to the shielding layer 120.

[0069] Among them, the first groove 133 can be etched in one step or in steps in the pixel circuit layer 132, and the shapes of the first groove 133 obtained by different etching methods are also different. For example, if it is a one-step etching, the first groove 133 can be a first-order inverted trapezoid as shown in Figure 2 (b); if it is a step-by-step etching. If it is a two-step etching, it can be a second-order inverted trapezoid as shown in Figure 2 (c), but it is not limited to this. In this embodiment, the first groove 133 is set in the pixel circuit layer 132, so that the cathode layer 131 is directly connected to the shielding layer 120 through the first groove 133, and the cathode voltage can be continuously and stably provided to the shielding layer 120.

[0070] In one embodiment, see the attached Figure 3 , attached Figure 3 The schematic diagram of the structure of the second groove 121 is shown. In order to more clearly illustrate the structure of the second groove 121, the attached Figure 3 The cathode layer 131 is not shown. The shielding layer 120 in this embodiment further includes a second groove 121, which extends from the surface of the shielding layer 120 facing the pixel circuit layer 132 to the surface of the shielding layer 120 facing the substrate 110, and the second groove 121 is connected to the first groove 133. Part of the cathode layer 131 is also provided on the side wall of the second groove 121 to provide a cathode voltage to the shielding layer 120.

[0071] In this embodiment, a second groove 121 is further provided in the shielding layer 120. On the one hand, since the thickness of the shielding layer 120 is much smaller than the thickness of the pixel circuit layer 132, it is easy to over-etch and directly etch to the shielding layer 120 when etching the first groove 133. Therefore, in order to reduce the difficulty of etching, the second groove 121 can be directly provided in the shielding layer 120. On the other hand, the second groove 121 is provided in the shielding layer 120, so that the cathode layer 131 is not only connected to the surface of the shielding layer 120, but is further connected to the inside of the shielding layer 120, and the cathode voltage can be uniformly and stably provided to the shielding layer 120, which is conducive to forming a strong shielding electric field in the shielding layer 120.

[0072] In one embodiment, referring to FIG. 2 (c), the first groove 133 in this embodiment includes a first partial groove 1331 and a second partial groove 1332, wherein the first partial groove 1331 is located at the top of the second partial groove 1332, and a portion of the cathode layer 131 is disposed on the surface of the first partial groove 1331 and the second partial groove 1332 to provide a cathode voltage to the shielding layer 120 through the first partial groove 1331 and the second partial groove 1332; the first partial groove 1331 and the second partial groove 1332 have different sizes.

[0073] The first portion groove 1331 and the second portion groove 1332 can be understood as a second-order groove formed by two-step etching when etching the first groove 133. In this embodiment, etching the first groove 133 in two steps to form the first portion groove 1331 and the second portion groove 1332 of different sizes is conducive to reducing the etching difficulty and avoiding one-step etching from damaging the substrate 110 or the shielding layer 120. In addition, the sizes of the first portion groove 1331 and the second portion groove 1332 are different, wherein the size of the second portion groove 1332 is smaller than the size of the first portion groove 1331, which is conducive to uniform deposition of the cathode layer 131.

[0074] In one embodiment, referring to FIG. 2( c ), in this embodiment, the opening size d1 of the second portion groove 1332 is 8 um to 20 um.

[0075] The opening dimension d1 of the second partial groove 1332 may refer to the maximum length of the second partial groove 1332 in a direction parallel to the substrate 110 .

[0076] For example, as shown in FIG. 2( c ), if the cross section of the second partial groove 1332 is a trapezoid, the opening size d1 of the second partial groove 1332 may be the size of the longer side of the two parallel sides of the trapezoid.

[0077] In another exemplary embodiment, if the cross section of the second partial groove 1332 is a rectangle, the opening dimension d1 of the second partial groove 1332 may be the long dimension of the rectangle.

[0078] It is understandable that the shape of the second portion groove 1332 and the corresponding cross-sectional shape may be other and are not limited to the above examples.

[0079] In this embodiment, in order to achieve exposure and development and more uniform deposition of the cathode layer 131, the opening size of the second portion groove 1332 should not be too small, so in this embodiment, the opening size d1 of the second portion groove 1332 is set to 8um~20um, which is conducive to exposure and development. Exemplarily, the opening size d1 of the second portion groove 1332 can be 8um, 9um, 10um, 11um, 12um, 13um, 14um, 15um, 16um, 17um, 18um, 19um, 20um, etc., but is not limited thereto.

[0080] Based on the same inventive concept, the embodiment of the present application also provides a method for preparing the above display panel. The implementation solution provided by the method is similar to the implementation solution recorded in the above display panel, so the specific limitations in one or more display panel preparation method embodiments provided below can refer to the above limitations on the display panel, and will not be repeated here.

[0081] In one embodiment, see the attached Figure 4 The present application also provides a method for preparing a display panel, which includes the following steps S401~S403.

[0082] Step S401, providing a substrate.

[0083] In step S402 , a shielding layer is deposited on the surface of the substrate, so that the shielding layer at least partially covers the surface of the substrate.

[0084] Exemplarily, the shielding layer may be deposited on the surface of the substrate by chemical vapor deposition, but is not limited thereto.

[0085] Step S403 , preparing a driving circuit layer on the side of the shielding layer facing away from the substrate, so that the cathode layer in the driving circuit layer is connected to the shielding layer to provide a cathode voltage to the shielding layer.

[0086] In this embodiment, a shielding layer is deposited between the substrate and the cathode layer in the driving circuit, so that the shielding layer has a stable shielding electric field provided by the cathode layer, which can shield the polarization electric field generated in the substrate and prevent it from affecting the driving circuit layer, thereby improving the afterimage problem of the display panel.

[0087] In one embodiment, depositing a shielding layer on the surface of the substrate includes: preparing the shielding layer on the entire surface of the substrate, so that the shielding layer covers the entire surface of the substrate.

[0088] In one embodiment, the transmittance of the shielding layer is greater than or equal to 60%. In this embodiment, the transmittance of the shielding layer is greater than or equal to 60%, which can ensure that the display performance of the display panel meets the requirements.

[0089] In one embodiment, the thickness of the shielding layer deposited on the substrate surface is 15Å-25Å.

[0090] In one embodiment, before preparing the driving circuit layer on the side of the shielding layer facing away from the substrate, the method further includes: doping a preset element in the shielding layer. Preferably, the preset element includes at least one of boron and phosphorus.

[0091] Based on the same inventive concept, the embodiment of the present application also provides a display panel manufacturing method for manufacturing the display panel involved above. The implementation solution provided by the method to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more display panel manufacturing method embodiments provided below can refer to the above limitations on the display panel structure, and will not be repeated here.

[0092] In one embodiment, see the attached Figure 5 , preparing a driving circuit layer on a side of the shielding layer away from the substrate, including the following steps S501~S503.

[0093] Step S501 , depositing a pixel circuit layer on a side of the shielding layer facing away from the substrate.

[0094] Step S502 , etching a first groove from the surface of the pixel circuit layer facing the cathode layer to the surface of the pixel circuit layer facing the shielding layer.

[0095] Specifically, the first groove can be formed by dry etching from the surface of the pixel circuit layer facing the cathode layer to the surface of the pixel circuit layer facing the shielding layer under preset conditions, such as etching under the action of CF4 and O2, but not limited thereto.

[0096] Step S503 , depositing a cathode layer on a side of the pixel circuit layer away from the shielding layer and on an inner wall of the first groove, so that the cathode layer passes through the pixel circuit layer to provide a cathode voltage to the shielding layer.

[0097] In one embodiment, before depositing the cathode layer on the side of the pixel circuit layer away from the shielding layer and the inner wall of the first groove, the method further includes: etching a second groove from the surface of the shielding layer facing the pixel circuit layer to the surface of the shielding layer facing the substrate, and the second groove is connected to the first groove. Depositing the cathode layer on the side of the pixel circuit layer away from the shielding layer and the inner wall of the first groove includes: depositing the cathode layer on a portion of the side of the pixel circuit layer away from the shielding layer, the first groove, and the inner wall of the second groove.

[0098] In one embodiment, a first groove is formed from the surface of the pixel circuit layer facing the cathode layer to the surface of the pixel circuit layer facing the shielding layer, including: etching a first partial groove from the surface of the pixel circuit layer facing the cathode layer to the surface of the pixel circuit layer facing the shielding layer; etching a second partial groove from the side of the first partial groove away from the pixel circuit layer in the thickness direction of the pixel circuit layer to the direction of the pixel circuit layer facing the shielding layer; the sizes of the first partial groove and the second partial groove are different.

[0099] In one embodiment, the opening size of the second portion of the groove etched on the surface of the first portion of the groove is 8um-20um.

[0100] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0101] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the application. It should be noted that, for a person of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: It includes a substrate, a shielding layer and a driving circuit layer, wherein the shielding layer is arranged between the substrate and the driving circuit layer and at least partially covers a side of the substrate facing the driving circuit layer, and the cathode layer in the driving circuit layer is connected to the shielding layer to provide a cathode voltage to the shielding layer.

2. The display panel according to claim 1, characterized in that: The transmittance of the shielding layer is greater than or equal to 60%; Preferably, the thickness of the shielding layer is 15Å~25Å; Preferably, the shielding layer is doped with a preset element; Preferably, the preset element includes at least one of boron and phosphorus; Preferably, the shielding layer includes an amorphous silicon layer or an ITO layer.

3. The display panel according to claim 1 or 2, characterized in that: The shielding layer covers the entire substrate on one side facing the driving circuit layer.

4. The display panel according to claim 1, characterized in that: The driving circuit layer comprises a cathode layer and a pixel circuit layer, wherein the pixel circuit layer is arranged on a side of the shielding layer away from the substrate, and the cathode layer is arranged on a side of the pixel circuit layer away from the shielding layer, and provides a cathode voltage to the shielding layer through the pixel circuit layer; Preferably, the pixel circuit layer comprises a first groove, the first groove extending from a surface of the pixel circuit layer facing the cathode layer to a surface of the pixel circuit layer facing the shielding layer, and part of the cathode layer is arranged on an inner wall of the first groove to provide the cathode voltage to the shielding layer; Preferably, the shielding layer also includes a second groove, which extends from the surface of the shielding layer facing the pixel circuit layer to the surface of the shielding layer facing the substrate, and the second groove is connected to the first groove. Part of the cathode layer is also arranged on the side wall of the second groove to provide the cathode voltage to the shielding layer.

5. The display panel according to claim 4, characterized in that: The first groove includes a first partial groove and a second partial groove, the first partial groove is located at the top of the second partial groove, and part of the cathode layer is arranged on the surface of the first partial groove and the second partial groove, so as to provide a cathode voltage to the shielding layer through the first partial groove and the second partial groove; Preferably, the first portion of grooves and the second portion of grooves have different sizes; Preferably, the opening size of the second portion of the groove is 8um~20um.

6. A method for preparing a display panel, characterized in that: The method comprises: providing a substrate; Depositing a shielding layer on the surface of the substrate so that the shielding layer at least partially covers the surface of the substrate; A driving circuit layer is prepared on a side of the shielding layer away from the substrate, so that the cathode layer in the driving circuit layer is connected to the shielding layer to provide a cathode voltage to the shielding layer.

7. The method for preparing a display panel according to claim 6, wherein: Depositing a shielding layer on the surface of the substrate comprises: The shielding layer is prepared on the entire surface of the substrate so that the shielding layer covers the entire surface of the substrate.

8. The method for preparing a display panel according to claim 6, wherein: Before preparing the driving circuit layer on the side of the shielding layer facing away from the substrate, the method further includes: doping a predetermined element into the shielding layer; Preferably, the preset element includes at least one of boron and phosphorus.

9. The method for preparing a display panel according to claim 6, wherein: A driving circuit layer is prepared on a side of the shielding layer facing away from the substrate, comprising: Depositing a pixel circuit layer on a side of the shielding layer facing away from the substrate; Etching a first groove from a surface of the pixel circuit layer facing the cathode layer to a surface of the pixel circuit layer facing the shielding layer; Depositing a cathode layer on a side of the pixel circuit layer away from the shielding layer and on an inner wall of the first groove, so that the cathode layer passes through the pixel circuit layer to provide a cathode voltage to the shielding layer; Preferably, before depositing the cathode layer on the side of the pixel circuit layer away from the shielding layer and the inner wall of the first groove, the method further comprises: Etching a second groove from the surface of the shielding layer facing the pixel circuit layer to the surface of the shielding layer facing the substrate, wherein the second groove is connected to the first groove; Depositing a cathode layer on a side of the pixel circuit layer away from the shielding layer and an inner wall of the first groove includes: The cathode layer is deposited on a portion of the pixel circuit layer away from the shielding layer and on inner walls of the first groove and the second groove.

10. The method for preparing a display panel according to claim 9, characterized in that: Etching a first groove from a surface of the pixel circuit layer facing the cathode layer to a surface of the pixel circuit layer facing the shielding layer, comprising: Etching a first portion of the groove from the surface of the pixel circuit layer facing the cathode layer to the surface of the pixel circuit layer facing the shielding layer; Etching a second portion of the groove from a side of the first portion of the groove away from the pixel circuit layer in the thickness direction of the pixel circuit layer toward the direction of the pixel circuit layer toward the shielding layer; Preferably, the first portion groove and the second portion groove have different sizes.

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