Display device

Abstract

The present disclosure relates to a display device including a substrate on which a plurality of island portions and a plurality of bridge portions connecting the plurality of island portions to each other are defined, a plurality of pixels disposed in each of the plurality of island portions, and a wiring disposed in each of the plurality of bridge portions and connected to the plurality of pixels, the plurality of islands and the plurality of bridges are defined based on a cutout portion of the substrate, and an apex of the cutout portion between one of the plurality of islands and a bridge connected to the one of the plurality of islands is an intersection of a straight line and a curved line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits of Korean Patent Application No. 10-2018-0034642, filed on Mar. 26, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Aspects of the present disclosure relate to a display device. Background Art

[0004] Currently, well-known display devices include liquid crystal displays ("LCDs"), plasma display panels ("PDPs"), organic light emitting diode ("OLED") displays, field effect displays ("FEDs"), electrophoretic displays, and the like.

[0005] Since OLED displays have self-luminous properties and do not require an additional light source, unlike LCDs, OLED displays can have reduced thickness and weight. In addition, OLED displays are gaining attention as next-generation display devices because they have high-quality properties such as low power consumption, high brightness, and high response speed.

[0006] Recently, bendable, foldable or stretchable display devices have been developed. Specifically, in a stretchable display device, since a light-emitting element is formed on a stretchable substrate, when the stretchable substrate is stretched, the light-emitting element or wiring stacked on the upper portion of the stretchable substrate may be damaged. Summary of the invention

[0007] Exemplary embodiments of the present invention provide an organic light emitting diode ("OLED") display in which light emitting elements stacked on a stretchable substrate can be effectively prevented from being damaged even if the stretchable substrate is repeatedly extended or retracted.

[0008] Exemplary embodiments of the present invention also provide an OLED display in which a short circuit of wirings can be effectively prevented even if a stretchable substrate is repeatedly extended or retracted.

[0009] According to an embodiment of the present disclosure, a display device includes a substrate, a plurality of pixels and a wiring, wherein a plurality of island portions and a plurality of bridging portions connecting the plurality of island portions to each other are defined on the substrate, a plurality of pixels are arranged in each of the plurality of island portions, and a wiring is arranged in each of the plurality of bridging portions and connected to the plurality of pixels, wherein the plurality of island portions and the plurality of bridging portions are defined based on a cutout portion of the substrate, and a vertex of the cutout portion between one of the plurality of island portions and a bridging portion connected to the one of the plurality of island portions is an intersection of a straight line and a curve.

[0010] In an embodiment, the straight line may be a portion of an edge of one of the plurality of island portions, and the curved line may be a portion of an edge of a bridge portion connected to the one of the plurality of island portions.

[0011] In an embodiment, each of the plurality of island portions may be divided into a first region, an edge region surrounding the first region, and a second region positioned outside the edge region.

[0012] In an embodiment, the display device may further include a first inorganic insulating layer, a second inorganic insulating layer, a third inorganic insulating layer, and a fourth inorganic insulating layer sequentially stacked on the plurality of island portions, and a first organic insulating layer covering a portion of the fourth inorganic insulating layer and the plurality of bridge portions.

[0013] In an implementation, a portion of the fourth inorganic insulating layer may overlap a remaining region of each of the plurality of island portions except for an edge region.

[0014] In an implementation, the first organic insulating layer may include an opening corresponding to the edge region.

[0015] In an implementation, the display device may further include an encapsulation layer filling at least a portion of the opening of the first organic insulating layer.

[0016] In an implementation, the fourth inorganic insulating layer may contact the encapsulation layer in at least a portion of the edge region.

[0017] In an embodiment, each of the plurality of pixels may include a light emitting device and a transistor controlling an amount of current flowing through the light emitting device.

[0018] In an embodiment, the light emitting device may include a first pixel electrode located on a first organic insulating layer, an emission layer located on the first pixel electrode, and a second pixel electrode located on the emission layer, and the second pixel electrode may fill at least a portion of an opening of the first organic insulating layer defined in the first organic insulating layer corresponding to an edge area.

[0019] In an implementation, the second pixel electrode may contact the fourth inorganic insulating layer in at least a portion of the edge region.

[0020] In an embodiment, the display device may further include a pixel defining layer defining a light emitting region of each of the plurality of pixels and a spacer on the pixel defining layer. In such an embodiment, the pixel defining layer may be disposed on the first organic insulating layer in the plurality of island portions.

[0021] In embodiments, a spacer may be positioned in the second region.

[0022] In an embodiment, the light emitting area may be positioned in the first zone.

[0023] In an embodiment, the plurality of pixels may include a first pixel displaying a first color, a second pixel displaying a second color, and a third pixel displaying a third color.

[0024] In an embodiment, the light emitting region of the second pixel may be positioned between the light emitting region of the first pixel and the light emitting region of the third pixel.

[0025] In an embodiment, an area of ​​the light emitting region of the second pixel may be greater than an area of ​​the light emitting region of the first pixel or the third pixel.

[0026] In an embodiment, the shape of the light emitting region of the first pixel may be the same as the shape of the light emitting region of the third pixel.

[0027] In an embodiment, the display device may further include a contact electrode disposed on the first organic insulating layer and spaced apart from the first pixel electrode. In such an embodiment, the second pixel electrode may be disposed on the contact electrode in such a manner that at least a portion of the contact electrode contacts the second pixel electrode.

[0028] In an embodiment, the contact electrode may be positioned in the second region.

[0029] In an embodiment, the contact electrode may be positioned in the first region.

[0030] In an implementation, the contact electrode may be electrically connected to a wiring extending from the bridge portion to the island portion.

[0031] In an embodiment, the display device may further include a second organic insulating layer on the bridge portion. In such an embodiment, in the bridge portion, the wiring may be disposed on the second organic insulating layer, and in the bridge portion, the first organic insulating layer may be disposed on the wiring and the second organic insulating layer.

[0032] In an embodiment, at least a portion of the wiring positioned in the bridge portion may have a bent shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features of the present invention will become more apparent by describing in more detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0034] Figure 1 is a block diagram schematically illustrating a configuration of an organic light emitting diode (OLED) display according to an exemplary embodiment of the present invention;

[0035] Figure 2 and Figure 3 is a diagram showing a portion of a substrate included in an OLED display according to an exemplary embodiment of the present invention;

[0036] Figure 4 It is shown Figure 1 A diagram of the configuration of the pixel PXL shown in FIG.

[0037] Figure 5 and Figure 6 It is shown Figure 4 A cross-sectional view of the structure of the pixel PXL shown in FIG.

[0038] Figure 7 is a plan view of a configuration applied to an OLED display according to an exemplary embodiment of the present invention;

[0039] Figure 8 It is along Figure 7 A cross-sectional view taken along line I1-I1';

[0040] Fig. 9 It is along Figure 7 A cross-sectional view taken along line I2-I2';

[0041] Fig.10 It is along Figure 7 A cross-sectional view taken along line I3-I3';

[0042] Fig.11 It is shown along Figure 7 A view of an alternative exemplary embodiment of a cross-sectional view taken along line I1-I1' of FIG.

[0043] Figure 12 to Figure 14 is a plan view of a portion of the configuration of an OLED device according to an alternative exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0044] Now, the present invention will be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. More specifically, these embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the text, the same reference numerals refer to the same elements.

[0045] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be an intervening element between the element and the other element. Conversely, when an element is referred to as being directly "on" another element, there is no intervening element. In the following disclosure, when a part (or element, device, etc.) is referred to as being "connected" to another part (or element, device, etc.), it will be understood that the part may be "directly connected" to the other part, or "electrically connected" to the other part via an intervening part (or element, device, etc.). In order to make the present invention clear, parts that are not relevant to the description are omitted from the drawings, and in all drawings, the same reference numerals are used to refer to the same or similar parts.

[0046] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first section" discussed below can be referred to as the second element, second component, second region, second layer or second section.

[0047] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It will also be understood that when used in this specification, the terms "comprising" and / or "comprising", "including" and / or "including" represent the existence of the features, regions, wholes, steps, operations, elements and / or components described, but do not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their combinations.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one drawing is flipped, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" may encompass both "lower" and "upper" orientations according to the particular orientation of the drawing. Similarly, if the device in one drawing is flipped, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Thus, the exemplary terms "below..." or "below..." may encompass both upper and lower orientations.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0050] In this article, exemplary embodiments are described with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, variations in the shapes shown will be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but should include deviations in shapes, for example, caused by manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and the shapes of these regions are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the appended claims.

[0051] Hereinafter, exemplary embodiments of a display according to the present invention will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 is a block diagram schematically illustrating a configuration of an organic light emitting diode ("OLED") display according to an exemplary embodiment of the present invention.

[0053] refer to Figure 1 , an exemplary embodiment of the OLED display 1 according to the present invention may include a display panel 300 and a display driver 400 .

[0054] The display panel 300 may include a plurality of pixels PXL, a plurality of data lines D1 to Dq connected to the pixels PXL, and a plurality of scan lines S1 to Sp connected to the pixels PXL.

[0055] Each of the pixels PXL may receive a data signal and a scan signal through a corresponding data line among the data lines D1 to Dq and a corresponding scan line among the scan lines S1 to Sp, respectively.

[0056] In such an embodiment, the pixel PXL may be connected to a first power source ELVDD and a second power source ELVSS.

[0057] Each of the pixels PXL may include a light emitting element (eg, an organic light emitting diode), and may generate light corresponding to a data signal by a current flowing from a first power source ELVDD through the light emitting element to a second power source ELVSS.

[0058] The display driver 400 may include a scan driver 410 , a data driver 420 , and a timing controller 450 .

[0059] The scan driver 410 may provide the scan signals to the scan lines S1 to Sp in response to the scan driver control signal SCS. In one exemplary embodiment, for example, the scan driver 410 may sequentially provide the scan signals to the scan lines S1 to Sp.

[0060] The scan driver 410 may be disposed (eg, directly mounted) on a substrate on which the pixels PXL are disposed or may be connected to the substrate through a separate member such as a flexible circuit board to be connected with the scan lines S1 to Sp.

[0061] The data driver 420 may receive the data driver control signal DCS and the image data DATA from the timing controller 450 to generate a data signal.

[0062] The data driver 420 may provide the generated data signals to the data lines D1 to Dq.

[0063] The data driver 420 may be disposed (eg, directly mounted) on a substrate on which the pixels PXL are disposed or may be connected to the substrate through a separate component element such as a flexible circuit board to be connected with the data lines D1 to Dq.

[0064] When a scan signal is supplied to a specific scan line, some of the pixels PXL connected to the specific scan line may receive data signals transmitted from the data lines D1 to Dq, and such pixels PXL may emit light having brightness corresponding to the received data signals.

[0065] The timing controller 450 may generate control signals for controlling the scan driver 410 and the data driver 420 .

[0066] In one exemplary embodiment, for example, the control signal may include a scan driver control signal SCS for controlling the scan driver 410 and a data driver control signal DCS for controlling the data driver 420 .

[0067] The timing controller 450 may generate a scan driver control signal SCS and a data driver control signal DCS based on an external input signal.

[0068] In one exemplary embodiment, for example, the external input signal may include a dot clock DCLK, a data enable signal DE, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync.

[0069] In an exemplary embodiment, the timing controller 450 may provide a scan driver control signal SCS to the scan driver 410 and a data driver control signal DCS to the data driver 420 .

[0070] The timing controller 450 may convert external image data RGB input from the outside into image data DATA corresponding to the specification of the data driver 420 , and may provide the image data DATA to the data driver 420 .

[0071] The data enable signal DE may define a period for inputting valid data, and one period may be set to correspond to one horizontal period, such as a period of a horizontal synchronization signal Hsync.

[0072] In an exemplary embodiment, Figure 1 As shown in FIG. 4 , the scan driver 410 , the data driver 420 , and the timing controller 450 are separately provided, but are not limited thereto. Alternatively, at least some of the scan driver 410 , the data driver 420 , and the timing controller 450 may be integrated together.

[0073] In an exemplary embodiment, the scan driver 410, the data driver 420, and the timing controller 450 may be mounted, for example, in various ways such as chip on glass (“COG”), chip on plastic (“COP”), tape carrier package (“TCP”), or chip on film (“COF”).

[0074] Figure 2 and Figure 3 is a diagram showing a portion of a substrate included in an OLED display according to an exemplary embodiment of the present invention. Figure 3 is shown when the substrate 110 ( Figure 5 (shown in the figure) is a diagram of the shape of the island portion and the bridge portion connected to the island portion when not stretched.

[0075] In an exemplary embodiment, the substrate 110 may have a structure supporting the pixel PXL, etc. disposed thereon, and may be stretched or retracted in one direction as a stretchable substrate.

[0076] In an exemplary embodiment, the substrate 110 may include or be made of an insulating material such as resin, etc. In such an embodiment, the substrate 110 may be made of a material having flexibility to be bent or folded, and may have a single layer structure or a multi-layer structure.

[0077] In one exemplary embodiment, for example, the substrate 110 may include at least one selected from polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0078] refer to Figure 2 and Figure 3 , the substrate 110 may include an island portion IS and a bridge portion BR defined or separated by a cutout portion Co. The cutout portion Co may be an opening formed by removing a portion of the substrate 110. In an exemplary embodiment, the substrate 110 may have a shape in which the island portion IS and a bridge portion BR connected to an edge of each island portion IS are arranged along the first direction DR1 and the second direction DR2.

[0079] refer to Figure 2 and Figure 3 , the vertex VT of the cutout portion Co positioned between the island portion IS and the bridge portion BR may be an intersection of the straight line SL and the curve CL. The straight line SL may be a portion of an edge of the island portion IS, and the curve CL may be a portion of an edge of the bridge portion BR.

[0080] A pixel structure (eg, a thin film transistor, a capacitor, an OLED, etc.) may be disposed or formed on each island portion IS, and a single pixel PXL or a plurality of pixels PXL may be disposed or formed on each island portion IS.

[0081] Wiring for supplying a power supply voltage, a data signal, a scan signal, etc. to the pixel structure may be disposed or formed on each bridge portion BR.

[0082] In such an embodiment, when the substrate 110 is stretched, the bridge portion BR may be stretched, and the distance between the island portions IS may increase or decrease. In such an embodiment, the area of ​​the cutout portion Co may increase. However, the shape of each island portion IS may not change.

[0083] In such an embodiment where the shape of each island IS does not change, when the substrate 110 is stretched, the width and height of the island IS may be constantly maintained or may not increase or decrease. Therefore, the structure of the pixel PXL disposed on the island IS may not change.

[0084] The entire substrate 110 may have, but is not limited to, a stretchable structure, or at least a portion of the substrate 110 may be stretchable.

[0085] Figure 4 It is shown Figure 1 For the convenience of illustration and description, Figure 4 Pixel PXL coupled to the i-th (i is a natural number) scan line Si and the j-th (j is a natural number) data line Dj is shown in FIG.

[0086] refer to Figure 4 , the pixel PXL may include a first transistor T1, a second transistor T2, a storage capacitor Cst, and an organic light emitting diode OLED.

[0087] The first transistor T1 may include a first electrode connected to the j-th data line Dj, a gate electrode connected to the i-th scan line Si, and a second electrode connected to the first node N1.

[0088] When a scan signal is supplied to the first transistor T1 through the i-th scan line Si, the first transistor T1 may be turned on, and a data signal received from the j-th data line Dj is supplied to the storage capacitor Cst through the turned-on first transistor T1.

[0089] The storage capacitor Cst may be charged with a voltage corresponding to the data signal.

[0090] The second transistor T2 may include a first electrode connected to the first power source ELVDD, a second electrode connected to the organic light emitting diode OLED, and a gate electrode connected to the first node N1.

[0091] The second transistor T2 may control the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst.

[0092] The organic light emitting diode OLED may include a first electrode (anode electrode) connected to the second electrode of the second transistor T2 and a second electrode (cathode electrode) connected to the second power source ELVSS.

[0093] The organic light emitting diode OLED may generate light corresponding to the amount of current supplied from the second transistor T2 .

[0094] The organic light emitting diode OLED may include an organic material that emits light of one or more primary colors (eg, red, green, and blue), and the OLED display 1 may display a desired image by a spatial sum of such primary colors.

[0095] In an exemplary embodiment, Figure 4 As shown in , the first electrode of each of the transistors T1 and T2 may be one of the source electrode and the drain electrode, and the second electrode of each of the transistors T1 and T2 may be the other of the source electrode and the drain electrode. In an exemplary embodiment, for example, when the first electrode is the source electrode, the second electrode may be the drain electrode.

[0096] In an exemplary embodiment, Figure 4 As shown in FIG. 1 , transistors T1 and T2 may be p-type metal oxide semiconductor (“PMOS”) transistors, but are not limited thereto. Alternatively, transistors T1 and T2 may be n-type metal oxide semiconductor (“NMOS”) transistors.

[0097] Figure 4 The structure of an exemplary embodiment of the pixel PXL is shown, and the exemplary embodiment of the pixel PXL of the present invention is not limited to the above structure. In this embodiment, the pixel PXL may have a circuit structure capable of providing current to the organic light emitting diode OLED, and may be any one selected from various structures currently known in the art.

[0098] In an alternative exemplary embodiment, in addition to Figure 4 In addition to the first transistor T1 and the second transistor T2 shown in FIG. 1 , the pixel PXL may further include an additional transistor and a capacitor for compensating for a current supplied to the organic light emitting diode OLED.

[0099] The first power source ELVDD may be a high voltage, and the second power source ELVSS may be a low voltage.

[0100] Figure 5 and Figure 6 It is shown Figure 4 2 is a cross-sectional view of the structure of an exemplary embodiment of a pixel PXL shown in FIG.

[0101] In an exemplary embodiment, Figure 5 and Figure 6 As shown in Figure 4 The transistors T1 and T2 included in the pixel PXL shown in FIG. 1 may be thin film transistors on the substrate 110. The storage capacitor Cst and the organic light emitting diode OLED included in the pixel PXL may be disposed or stacked on the substrate 110.

[0102] As mentioned above Figure 2 and Figure 3 As described, in exemplary embodiments, the substrate 110 may include or be made of polyimide, polyamide, polyacrylate, or the like.

[0103] In such an embodiment, a buffer layer 120 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be disposed on the substrate 110 .

[0104] The buffer layer 120 may provide a flat upper surface on the substrate 110 and may be used to prevent or minimize impurities from penetrating into layers on the substrate 110 (e.g., the semiconductor layer 135a of the first transistor T1 and the semiconductor layer 135b of the second transistor T2) through the substrate 110. The buffer layer 120 may have a single-layer structure or a multi-layer structure.

[0105] In exemplary embodiments, although not shown in the drawings, a barrier layer may be further disposed on the substrate 110 .

[0106] The first semiconductor layer 135 a and the second semiconductor layer 135 b may be disposed or formed on the buffer layer 120 to be separated from each other.

[0107] The first semiconductor layer 135 a and the second semiconductor layer 135 b may include or be made of polycrystalline silicon or an oxide semiconductor.

[0108] The oxide semiconductor may include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), and composite oxides thereof (e.g., zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO 4), indium zinc oxide (Zn-In-O), zinc tin oxide (Zn-Sn-O), indium gallium oxide (In-Ga-O), indium tin oxide (In-Sn-O), indium zirconium oxide (In-Zr-O), indium zirconium zinc oxide (In-Zr-Zn-O), indium zirconium tin oxide (In-Zr-Sn-O), indium zirconium gallium oxide (In-Zr-Ga-O), indium aluminum oxide (In-Al-O), indium zinc aluminum oxide (In-Zn-Al-O), indium tin aluminum oxide (In-Sn-Al-O), indium aluminum gallium oxide (In-Al -Ga-O), indium tantalum oxide (In-Ta-O), indium tantalum zinc oxide (In-Ta-Zn-O), indium tantalum tin oxide (In-Ta-Sn-O), indium tantalum gallium oxide (In-Ta-Ga-O), indium germanium oxide (In-Ge-O), indium germanium zinc oxide (In-Ge-Zn-O), indium germanium tin oxide (In-Ge-Sn-O), indium germanium gallium oxide (In-Ge-Ga-O), titanium indium zinc oxide (Ti-In-Zn-O) and hafnium indium zinc oxide (Hf-In-Zn-O)).

[0109] In an exemplary embodiment in which the semiconductor layers 135 a and 135 b are made of an oxide semiconductor, a separate passivation layer may be added to protect the oxide semiconductor that is susceptible to an external environment such as high temperature, etc.

[0110] Each of the first semiconductor layer 135a and the second semiconductor layer 135b may include a channel region 1355 not doped with impurities, and a source region 1356 and a drain region 1357 defined or formed by doping opposite sides of the channel region 1355 with impurities. The doping impurities may be selected according to the type of the thin film transistor, and may be n-type impurities or p-type impurities.

[0111] The channel region 1355 of the first semiconductor layer 135 a and the second semiconductor layer 135 b may include polysilicon not doped with impurities, that is, an intrinsic semiconductor.

[0112] In example embodiments, the source region 1356 and the drain region 1357 of the first and second semiconductor layers 135 a and 135 b may include polysilicon doped with conductive impurities, that is, an impurity semiconductor.

[0113] The gate insulating layer 140 may be disposed or formed on the first semiconductor layer 135a and the second semiconductor layer 135b to ensure that the first semiconductor layer 135a and the second semiconductor layer 135b are insulated from the gate electrode. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure including an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0114] The first gate electrode 125 a , the first capacitor electrode 128 , and the second gate electrode 125 b may be disposed or formed on the gate insulating layer 140 .

[0115] Although not shown in the drawings, Figure 4 The wiring corresponding to the i-th scan line Si shown in FIG. 1 may be electrically connected to the first gate electrode 125a. The first capacitor electrode 128 and the second gate electrode 125b may be located in the same layer (eg, directly on the gate insulating layer 140) and connected to each other.

[0116] In example embodiments, the first gate electrode 125 a , the first capacitor electrode 128 , and the second gate electrode 125 b positioned on the gate insulating layer 140 may include or be made of a metal.

[0117] In this embodiment, the metal may include molybdenum (Mo). Alternatively, the metal may include at least one selected from gold (Au), silver (Ag), aluminum (Al), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0118] In an exemplary embodiment, each of the first gate electrode 125a, the first capacitor electrode 128, and the second gate electrode 125b may have a single-layer structure or be formed of a single layer, but is not limited thereto. Alternatively, each of the first gate electrode 125a, the first capacitor electrode 128, and the second gate electrode 125b may have a multi-layer structure or be formed of a multi-layer in which metals and alloys of two or more materials are stacked on each other.

[0119] When viewed in a plan view in the thickness direction of the substrate 110 , each of the first gate electrode 125 a and the second gate electrode 125 b overlaps with the channel region 1355 .

[0120] An interlayer insulating layer 160 may be disposed on the first gate electrode 125 a , the first capacitor electrode 128 , and the second gate electrode 125 b .

[0121] The interlayer insulating layer 160 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0122] A source contact hole 61 and a drain contact hole 62 may be defined or formed in the interlayer insulating layer 160 and the gate insulating layer 140 to expose the source region 1356 and the drain region 1357 , respectively.

[0123] In example embodiments, a storage contact hole 63 may be defined or formed in the interlayer insulating layer 160 to expose a portion of the first capacitor electrode 128 .

[0124] The first source electrode 176 a , the second source electrode 176 b , the second capacitor electrode 178 , the first drain electrode 177 a , and the second drain electrode 177 b may be disposed on the interlayer insulating layer 160 .

[0125] In an exemplary embodiment, the electrode (or wiring) disposed on the interlayer insulating layer 160 may include a metal or be made of a metal. In an exemplary embodiment, for example, the electrode (or wiring) may be made of at least one selected from metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and alloys of metals. In such an embodiment, each of the electrodes (or wiring) may have a single-layer structure or be formed of a single layer, but is not limited thereto. Alternatively, each of the electrodes (or wiring) may have a multilayer structure or be formed of a multilayer in which metals and alloys of two or more materials are stacked on each other.

[0126] Although not shown in the drawings, a layer such as Figure 4 The j-th data line Dj shown in FIG. 1 corresponds to and is connected to the wiring of the first source electrode 176a, and is used to provide Figure 4 , and a wiring connected to the second capacitor electrode 178 and a wiring for providing the second power ELVSS, etc. In such an embodiment, the wiring may include the same material as the first source electrode 176a, the second source electrode 176b, the second capacitor electrode 178, the first drain electrode 177a, and the second drain electrode 177b or be formed of the same material as the first source electrode 176a, the second source electrode 176b, the second capacitor electrode 178, the first drain electrode 177a, and the second drain electrode 177b.

[0127] Each of the first source electrode 176 a and the second source electrode 176 b may be connected to the source region 1356 through the source contact hole 61 .

[0128] Each of the first drain electrode 177 a and the second drain electrode 177 b may be connected to the drain region 1357 through the drain contact hole 62 .

[0129] In an exemplary embodiment, the first drain electrode 177a may extend through the storage contact hole 63 defined in the interlayer insulating layer 160 to be electrically connected to the first capacitor electrode 128. In such an embodiment, although not shown in the drawings, the first drain electrode 177a may be electrically connected to the second gate electrode 125b through the contact hole.

[0130] In an exemplary embodiment, the second capacitor electrode 178 may overlap the first capacitor electrode 128 when viewed from a plan view in the thickness direction of the substrate 110. Therefore, in such an embodiment, the first capacitor electrode 128 and the second capacitor electrode 178 may form or jointly define a storage capacitor Cst with the interlayer insulating layer 160 as a dielectric material.

[0131] The first semiconductor layer 135 a , the first gate electrode 125 a , the first source electrode 176 a , and the first drain electrode 177 a may form or collectively define a switching transistor T1 .

[0132] The second semiconductor layer 135 b , the second gate electrode 125 b , the second source electrode 176 b , and the second drain electrode 177 b may form or collectively define a driving transistor T2 .

[0133] A passivation layer 180 may be disposed on the first source electrode 176 a , the second source electrode 176 b , the first drain electrode 177 a , and the second drain electrode 177 b .

[0134] In an exemplary embodiment, the passivation layer 180 may be an inorganic insulating layer including or made of an inorganic material. In such an embodiment, the inorganic material may include polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. Alternatively, the passivation layer 180 may be omitted.

[0135] The first protective layer 190 may be disposed or formed on the passivation layer 180 .

[0136] The first protective layer 190 may be an organic insulating layer made of an organic material. The organic material may include, for example, polyacrylic acid compounds, polyimide compounds, fluorocarbon compounds (eg ), organic insulating materials such as benzocyclobutene compounds, etc.

[0137] The first pixel electrode 710 may be disposed or formed on the first protective layer 190 .

[0138] The first pixel electrode 710 may include, for example, indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO), indium oxide (In 2 O 3 ) or a reflective metal such as lithium, calcium, lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), etc., or is made of the above transparent conductive materials or reflective metals.

[0139] The first pixel electrode 710 may be electrically connected to the second drain electrode 177 b of the second transistor T2 through a contact hole 181 defined in the passivation layer 180 and the first protective layer 190 , and may function as an anode of the organic light emitting diode OLED.

[0140] The pixel defining layer 350 may be disposed or formed on the first protective layer 190 and edge portions of the first pixel electrode 710. In an exemplary embodiment, the pixel defining layer 350 may include an opening exposing the first pixel electrode 710. In such an embodiment, the pixel defining layer 350 may divide a pixel region of each pixel.

[0141] The pixel defining layer 350 may be an organic insulating layer including or made of an organic material. The organic material may include, for example, polyacrylic acid-based compounds, polyimide-based compounds, fluorocarbon compounds (eg ), organic insulating materials such as benzocyclobutene compounds, etc.

[0142] The organic emission layer 720 may be disposed in the opening of the pixel defining layer 350 .

[0143] The organic emission layer 720 may include a low molecular weight material or a high molecular weight material. The low molecular weight material may include copper phthalocyanine ("CuPc"), N,N-Di(naphthalene-1-yl)-N,N'-diphenylbenzidine ("NPB"), tri-8-hydroxyquinoline aluminum ("Alq 3 ”) and the like. These materials can be formed by using vacuum deposition. The polymer material may include poly(3,4-ethylenedioxythiophene) (“PEDOT”), poly(p-phenylenevinylene) (“PPV”), polyfluorene, and the like.

[0144] The organic emission layer 720 may include a red organic emission layer emitting red light, a green organic emission layer emitting green light, and a blue organic emission layer emitting blue light. The red organic emission layer, the green organic emission layer, and the blue organic emission layer are respectively disposed on red pixels, green pixels, and blue pixels to display color images.

[0145] Alternatively, a white organic emission layer emitting white light may be disposed on each of the red, green, and blue pixels, and a red, green, or blue color filter may be disposed in each pixel to display a color image.

[0146] The second pixel electrode 730 may be disposed on the pixel defining layer 350 and the organic emission layer 720 .

[0147] The second pixel electrode 730 may include a metal layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), etc. and / or a transparent conductive layer such as ITO, IZO, zinc oxide (ZnO), indium tin zinc oxide ("ITZO"), etc., or may be made of the above metal layer and / or transparent conductive layer. In an exemplary embodiment of the present invention, the second pixel electrode 730 may have a multilayer structure or be formed of a multilayer including a metal thin film, for example, three layers of ITO / Ag / ITO.

[0148] In exemplary embodiments, as described above, the first pixel electrode 710 may be an anode electrode of the organic light emitting diode OLED, and the second pixel electrode 730 may be a cathode electrode of the organic light emitting diode OLED.

[0149] However, in an alternative exemplary embodiment, the first pixel electrode 710 may be a cathode electrode, and the second pixel electrode 730 may be an anode electrode.

[0150] The first pixel electrode 710 , the organic emission layer 720 , and the second pixel electrode 730 form or collectively define an organic light emitting diode OLED.

[0151] The encapsulation layer 200 may be disposed on the second pixel electrode 730. The encapsulation layer 200 may be used to prevent oxygen and moisture from penetrating into the organic light emitting diode OLED. The encapsulation layer 200 may include a plurality of inorganic layers (not shown) and / or a plurality of organic layers (not shown). In an exemplary embodiment, for example, the encapsulation layer 200 may include a plurality of unit encapsulation layers, the unit encapsulation layer including an inorganic layer and an organic layer disposed on the inorganic layer.

[0152] Figure 7 1 is a plan view of a configuration applied to an OLED display according to an exemplary embodiment of the present invention. For ease of illustration and description, Figure 7 1 shows one of the multiple island portions IS and a bridge portion BR connecting the one island portion IS. In addition, for the convenience of illustration and description, Figure 7 4 shows the following structures disposed on one island portion IS: the emission areas EA1 to EA3 of each pixel PXL, the edge area OIO of the emission areas EA1 to EA3, the spacer SPC, and the contact electrode CTE.

[0153] refer to Figure 7 , the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be defined in the island portion IS.

[0154] In an exemplary embodiment of the OLED display 1 according to the present invention, a plurality of pixels PXL may be disposed in each island portion IS. In an exemplary embodiment, for example, a pixel emitting red light, a pixel emitting blue light, and a pixel emitting green light may be arranged or disposed in each island portion IS.

[0155] The first emission area EA1 may correspond to the organic emission layer of the pixel emitting red light. The second emission area EA2 may correspond to the organic emission layer of the pixel emitting blue light. The third emission area EA3 may correspond to the organic emission layer of the pixel emitting green light. The positions and shapes of the emission areas EA1 to EA3 may be defined by the pixel defining layer 350.

[0156] In an exemplary embodiment, the first light emitting area EA1 and the third light emitting area EA3 may have the same shape as each other. In such an embodiment, the shapes of the first light emitting area EA1 and the third light emitting area EA3 may be symmetrical to each other. In such an embodiment, the first light emitting area EA1 and the third light emitting area EA3 may be arranged symmetrically with respect to the second light emitting area EA2 or symmetrically with respect to an imaginary line extending in the first direction DR1 passing through the center of the second light emitting area EA2.

[0157] In an exemplary embodiment, Figure 7 As shown in FIG. 1 , the first and third light emitting areas EA1 and EA3 may have a shape corresponding to a shape of a portion of the edge area OIO.

[0158] The second light emitting area EA2 may be located between the first light emitting area EA1 and the third light emitting area EA3. The area of ​​the second light emitting area EA2 may be greater than the area of ​​the first light emitting area EA1 or the third light emitting area EA3.

[0159] The island portion IS may include a first region A1 and a second region A2 separated by an edge region OIO.

[0160] The first area A1 may be an inner area of ​​the edge area OIO. That is, the first area A1 may be surrounded by the edge area OIO. The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be disposed in the first area A1.

[0161] The second area A2 may be an outer area of ​​the edge area OIO. Figure 7 As shown in FIG. 4 , the spacer SPC and the contact electrode CTE may be disposed in the second area A2 .

[0162] In the following, reference will be made to Figure 8 and Fig. 9 Detailed Description Figure 7 The edge region OIO, the spacer SPC and the contact electrode CTE are shown in FIG.

[0163] Figure 8 It is along Figure 7A cross-sectional view taken along line I1-I1'.

[0164] In exemplary embodiments, as described above, wirings for supplying power (eg, first power ELVDD and second power ELVSS), data signals, scan signals, etc. to the pixel structure on the island portion IS may be disposed on the bridge portion BR.

[0165] refer to Figure 8 , the second protective layer 195 may be disposed on the bridge portion BR of the substrate 110 .

[0166] The buffer layer 120 , the gate insulating layer 140 , and the interlayer insulating layer 160 may have an opening exposing the bridge portion BR of the substrate 110 .

[0167] In such an embodiment, most of the buffer layer 120 , the gate insulating layer 140 , and the interlayer insulating layer 160 may be disposed on the island portion IS, and only a portion of the buffer layer 120 , the gate insulating layer 140 , and the interlayer insulating layer 160 may be disposed on the bridge portion BR.

[0168] The second protective layer 195 may cover edges of the buffer layer 120 , the gate insulating layer 140 , and the interlayer insulating layer 160 defining the opening and may cover the bridge portion BR exposed by the opening.

[0169] The second protective layer 195 may be an organic insulating layer including or made of an organic material. The organic material may include, for example, polyacrylic acid-based compounds, polyimide-based compounds, fluorocarbon compounds (eg ), organic insulating materials such as benzocyclobutene compounds, etc.

[0170] The wiring DVL may be disposed or formed on the second protective layer 195. Figure 8 Only one wiring DVL is shown in FIG. 1 , but a plurality of wirings DVL may be arranged side by side on the bridge portion BR when viewed in a plan view in the thickness direction of the substrate 110 .

[0171] In an exemplary embodiment, the wiring DVL disposed on the bridge portion BR may extend along the shape of the bridge portion BR. In such an embodiment, the wiring DVL may extend to the island portion IS. The wiring DVL extending to the island portion IS may be disposed on the interlayer insulating layer 160 and may be electrically connected to the transistors T1 and T2, the storage capacitor Cst, or the organic light emitting diode OLED as described above.

[0172] In an exemplary embodiment, for example, the wiring DVL extending from the bridge portion BR to the island portion IS may be electrically connected to some of the electrodes / wirings disposed on the interlayer insulating layer 160 and may be electrically connected to some of the electrodes / wirings disposed on the gate insulating layer 140 .

[0173] The wiring DVL may include the same material as that of the source electrodes 176 a and 176 b of the transistor on the interlayer insulating layer 160 , the second capacitor electrode 178 , the drain electrodes 177 a and 177 b of the transistor, or the like, or be formed of the above materials.

[0174] The first protective layer 190 may include the wiring DVL or be formed on the wiring DVL. The first protective layer 190 disposed on the bridge BR may cover an edge of the passivation layer 180.

[0175] In an exemplary embodiment, one portion of the wiring DVL may be protected by the first protective layer 190 , and the remaining portion of the wiring DVL may be protected by the passivation layer 180 .

[0176] In an exemplary embodiment, the buffer layer 120, the gate insulating layer 140, and the interlayer insulating layer 160 including an inorganic material may be collectively referred to as an inorganic insulating layer. In such an embodiment, the first protective layer 190 and the second protective layer 195 may be collectively referred to as an organic material layer.

[0177] According to the exemplary embodiment of the present invention, the inorganic insulating layer has an opening corresponding to the bridge BR, and the bridge BR has the organic material layer filling at least a portion of the opening.

[0178] In this embodiment, the wiring DVL may extend to the island IS via the bridge BR, and the wiring DVL may be disposed on the organic material layer at the bridge BR. By using the same material as the source electrode or the drain electrode, the wiring DVL may be formed simultaneously with the source electrode or the drain electrode of the transistor during the same process.

[0179] An exemplary embodiment of the OLED display 1 according to the present invention is stretchable. In this embodiment, if the inorganic insulating layer does not have an opening in the bridge portion BR and has a continuous shape from the island portion IS to the bridge portion BR, the wiring DVL may be disposed on the inorganic insulating layer at the bridge portion BR, and a large tensile stress is thereby applied to the wiring DVL when the substrate 110 is stretched.

[0180] Specifically, since the inorganic insulating layer has a higher hardness than the organic material layer, there is a high probability that cracks etc. will occur in the inorganic insulating layer provided in the bridge portion BR. When cracks etc. occur in the inorganic insulating layer, cracks etc. may also occur in the wiring DVL on the inorganic insulating layer, which may result in a high probability of defects such as disconnection of the wiring DVL.

[0181] However, in an exemplary embodiment of a display device according to the present invention, the inorganic insulating layer is mainly disposed on the island portion IS of the substrate 110 which is almost unstressed, and is minimally disposed on the bridging portion BR which is subjected to stress when the substrate 110 is stretched, so that the wiring DVL is disposed on the organic material layer at the bridging portion BR.

[0182] Since the hardness of the organic material layer is lower than that of the inorganic insulating layer, the organic material layer may absorb the tensile stress applied to the substrate 110 , and thus the concentration of the tensile stress on the wiring DVL may be effectively minimized.

[0183] Herein, the electrodes / wirings on the gate insulating layer 140 may be collectively referred to as a first conductive layer, and the electrodes / wirings on the interlayer insulating layer 160 may be collectively referred to as a second conductive layer.

[0184] According to the exemplary embodiment of the present invention, the wiring DVL disposed on the bridge portion BR may include the same material as that included in the second conductive layer.

[0185] According to the exemplary embodiment of the present invention, the wiring DVL disposed on the bridge portion BR includes a material having high elongation or ductility, so that defects such as cracks or disconnections of the wiring DVL may not occur or be effectively prevented.

[0186] In the island portion IS, although the first conductive layer has a lower elongation than the wiring DVL, the first conductive layer may include or be formed of a material having electrical / physical properties different from those of the wiring DVL, thereby improving the efficiency of electrical signal transmission or reducing the incidence of defects in the manufacturing process.

[0187] In one exemplary embodiment, for example, the first conductive layer disposed on the island portion IS may include molybdenum, and the second conductive layer and the wiring DVL may include aluminum.

[0188] In an exemplary embodiment of the present invention, the second protective layer 195 may be disposed to cover the edge of the inorganic insulating layer and the bridge BR, and the wiring DVL may be disposed on the second protective layer 195 .

[0189] By using the same material as the second conductive layer, the wiring DVL can be formed simultaneously with the second conductive layer (eg, source electrode or drain electrode of a transistor) during the same process. After forming the conductive layer on the entire surface of the substrate, the wiring DVL can be formed by patterning the conductive layer.

[0190] For the convenience of illustration and description, Figure 8As shown in , the exemplary embodiment in which the wiring DVL is disposed on the second protective layer 195 includes a single organic insulating layer, but is not limited thereto. In an alternative exemplary embodiment, for example, the second protective layer 195 may be in the form of a stack of multiple organic insulating layers, and at least one wiring DVL may be disposed on each of the multiple organic insulating layers. In such an embodiment, the wiring DVL may be disposed on different organic insulating layers during the manufacturing process of the display device, depending on the width of the bridge BR and the number of wirings connected to the pixel.

[0191] In the case where the organic material layer does not cover the edge of the inorganic insulating layer, the conductive material may remain in the buffer layer 120, the gate insulating layer 140, the interlayer insulating layer 160, etc., without being removed when the conductive layer is patterned. The remaining conductive material may cause a short circuit between other conductive layers.

[0192] refer to Figure 8 , an edge region OIO adjacent to the bridge portion BR may be defined on the island portion IS. The edge region OIO may be a region where the first protective layer 190 and the second protective layer 195 are not disposed.

[0193] The first protective layer 190 may include an opening corresponding to the edge area OIO. A portion of the passivation layer 180 may be exposed to the outside of the first protective layer 190 through the opening defined or formed in the first protective layer 190. At least a portion of the opening in the first protective layer 190 may be filled with the second pixel electrode 730 and the encapsulation layer 200.

[0194] Only the buffer layer 120 including an inorganic material, the gate insulating layer 140, the interlayer insulating layer 160, and the passivation layer 180 may be disposed on the edge region OIO, and the first protective layer 190 and the second protective layer 195 may not be disposed on the edge region OIO. Figure 8 As shown in FIG. 1 , at least a portion of the passivation layer 180 may be in direct contact with the encapsulation layer 200 in the edge region OIO. When the encapsulation layer 200 includes at least one inorganic layer and at least one organic layer, the inorganic layer may be the lowermost layer of the encapsulation layer 200, so that the inorganic layer of the encapsulation layer 200 is in direct contact with the passivation layer 180.

[0195] Fig. 9 It is along Figure 7 A cross-sectional view taken along line I2-I2'.

[0196] refer to Figure 7 and Fig. 9 , the spacer SPC may be disposed on the pixel defining layer 350, and may be placed in the second area A2 which is an outer area of ​​the edge area OIO.

[0197] The spacer SPC may be an organic insulating layer including or made of an organic material. The organic material may include, for example, polyacrylic acid-based compounds, polyimide-based compounds, fluorocarbon compounds (e.g. ), organic insulating materials such as benzocyclobutene compounds, etc.

[0198] The spacer SPC may support the metal mask. When the spacer SPC is positioned in the second area A2, the probability of occurrence of defective pixels caused by the metal mask is lower than when the spacer SPC is positioned in the first area A1. Therefore, in this embodiment, the probability of occurrence of dark spots may be reduced.

[0199] Fig.10 It is along Figure 7 A cross-sectional view taken along line I3-I3'.

[0200] refer to Figure 7 and Fig.10 , the contact electrode CTE may be disposed on the first protective layer 190 .

[0201] The pixel defining layer 350 may be disposed on the contact electrode CTE. In such an embodiment, the pixel defining layer 350 may be disposed to cover an edge portion of the contact electrode CTE and the first protective layer 190. The pixel defining layer 350 may have an opening OA exposing the contact electrode CTE.

[0202] The second pixel electrode 730 may be disposed on the contact electrode CTE and the pixel defining layer 350. A region of the contact electrode CTE exposed by the pixel defining layer 350 may directly contact the second pixel electrode 730.

[0203] In exemplary embodiments, the contact electrode CTE may transmit the second power source ELVSS to the second pixel electrode 730. The contact electrode CTE may be connected to the wiring DVL through the contact hole 191.

[0204] In such an embodiment, the second power source ELVSS supplied to the wiring DVL may be supplied to the second pixel electrode 730 through the contact electrode CTE.

[0205] The second pixel electrode 730 disposed on the contact electrode CTE may extend to a top surface of the organic emission layer 720 disposed in the first area A1 via the edge area OIO.

[0206] The contact electrode CTE may include or be formed of the same material as the first pixel electrode 710 .

[0207] refer to Fig.10 , the passivation layer 180 may directly contact the second pixel electrode 730 in at least a portion of the edge region OIO.

[0208] like Figure 7 and Fig.10 As shown in FIG. 1 , the contact electrode CTE may be disposed in the second area A2 . However, the present invention is not limited thereto, and alternatively, the contact electrode CTE may be positioned in the first area A1 .

[0209] Fig.11 It is shown along Figure 7 A view of an alternative exemplary embodiment of a cross-sectional view taken along line I1 - I1 ′ of FIG.

[0210] In addition to routing DVL', Fig.11 The cross-sectional view in Figure 8 The cross-sectional views shown in are substantially the same. Fig.11 The same or similar elements shown in FIG. 1 have been used to describe Figure 7 and Figure 8 The exemplary embodiments of the OLED display shown in FIG. 1 are denoted by the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0211] refer to Fig.11 In an exemplary embodiment, at least a portion of the wiring DVL' disposed on the bridge BR may have a bent shape, for example, a wavy pattern shape. The wiring DVL' may have a bent shape in a third direction perpendicular to the first direction DR1 and the second direction DR2.

[0212] Therefore, in such an embodiment, stress applied to the wiring DVL′ when the substrate 110 is stretched may be minimized.

[0213] Figure 12 to Figure 14 is a plan view of a portion of the configuration of an OLED device according to an alternative exemplary embodiment of the present invention.

[0214] In addition to the spacer SPC and contact electrode CTE, Figure 12 to Figure 14 The floor plan and Figure 7 The plan views shown in are substantially the same. Figure 12 to Figure 14 The same or similar elements shown in FIG. 1 have been used to describe Figure 7 The exemplary embodiments of the OLED display shown in FIG. 1 are denoted by the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0215] like Figure 7 As shown in, for the convenience of description, Figure 12 to Figure 14 FIG. 4 shows an exemplary embodiment of an island portion IS and a bridge portion BR connected to the island portion IS. Figure 12 to Figure 14Only the emission areas EA1 to EA3 , the edge area OIO , the spacer SPC , and the contact electrode CTE of each pixel PXL in the configuration on the island portion IS are shown.

[0216] refer to Fig.12 In an alternative exemplary embodiment, the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be disposed in the first area A1 of the island portion IS.

[0217] In this embodiment of the OLED display according to the present invention, a plurality of pixels PXL may be provided in each of the island portions IS. In one exemplary embodiment, for example, a pixel PXL emitting red light (or displaying a red color), a pixel PXL emitting blue light (or displaying a blue color), and a pixel PXL emitting green light (or displaying a green color) may be provided in each island portion IS.

[0218] The first emission area EA1 may correspond to the organic emission layer of the pixel PXL emitting red light. The second emission area EA2 may correspond to the organic emission layer of the pixel PXL emitting blue light. The third emission area EA3 may correspond to the organic emission layer of the pixel PXL emitting green light.

[0219] The first light emitting area EA1 and the third light emitting area EA3 may have the same shape as each other. Fig.12 As shown in FIG. 1 , in an exemplary embodiment, for example, the first and third emission areas EA1 and EA3 may have a polygonal shape. However, the present invention is not limited thereto, and alternatively, the shapes of the first and third emission areas EA1 and EA3 may be variously changed according to the shape of the edge area OIO.

[0220] The second light emitting area EA2 may be positioned between the first light emitting area EA1 and the third light emitting area EA3. The area of ​​the second light emitting area EA2 may be greater than that of the first light emitting area EA1 or the third light emitting area EA3.

[0221] The spacer SPC and the contact electrode CTE may be disposed in the second area A2.

[0222] like Fig.12 As shown in , in an exemplary embodiment, a single spacer SPC and a single contact electrode CTE may be disposed in each island portion IS.

[0223] like Fig.13 and Fig.14 As shown in , in an alternative exemplary embodiment, the contact electrode CTE may be disposed in the first region A1 of the island IS. However, as described above, in another alternative exemplary embodiment, the spacer SPC may be positioned in the second region A2 as the outer side of the edge region OIO to effectively prevent defects caused by dark spots.

[0224] The present invention should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0225] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined in the following claims.

Claims

1. A display device, comprising: A substrate including a plurality of island portions and a plurality of bridge portions connecting the plurality of island portions; A plurality of pixels are arranged on the plurality of island portions; wiring, disposed on the plurality of bridge portions and connected to the plurality of pixels; a plurality of inorganic insulating layers stacked on the plurality of island portions; a first organic insulating layer covering the plurality of bridge portions and a portion of the plurality of island portions; as well as A packaging layer is disposed on the substrate. Wherein, the first organic insulating layer comprises an opening, and The encapsulation layer contacts one of the plurality of inorganic insulating layers through the opening.

2. The display device according to claim 1, wherein: The wiring supplies the first power and the second power, and Each of the plurality of pixels includes a light emitting element, and emits light corresponding to a current flowing from the first power to the second power via the light emitting element.

3. The display device according to claim 1 , further comprising a second organic insulating layer disposed on the plurality of bridge portions, in, The wiring is provided between the first organic insulating layer and the second organic insulating layer, and The second organic insulating layer covers an edge of at least one of the remaining inorganic insulating layers except the one of the plurality of inorganic insulating layers.

4. The display device according to claim 1, wherein: The wiring extends to the plurality of islands, and Wherein, the one of the plurality of inorganic insulating layers is disposed on the wiring.

5. The display device according to claim 1, wherein: The opening is defined by opposite edges of the first organic insulating layer.

6. The display device according to claim 1, further comprising: a pixel defining layer defining a light emitting region of each of the plurality of pixels; as well as a spacer, on the pixel defining layer, wherein each of the plurality of islands includes a first region, an edge region surrounding the first region, and a second region located outside the edge region, wherein the opening of the first organic insulating layer overlaps with the edge region, wherein the pixel defining layer is disposed on the first organic insulating layer in the plurality of island portions, and Wherein, the spacer is located in the second region.

7. A display device, comprising: a substrate including a first region, a first edge region surrounding the first region, a second region, a second edge region surrounding the second region, and a cutout portion formed between the first edge region and the second edge region; A first pixel group is arranged in the first area; a second pixel group, disposed in the second region; A plurality of inorganic insulating layers stacked on the substrate; an organic insulating layer disposed on at least one of the plurality of inorganic insulating layers; as well as A packaging layer is disposed on the substrate. wherein the organic insulating layer comprises an opening exposing one of the plurality of inorganic insulating layers, wherein the opening is located in the first edge region, and Wherein, the encapsulation layer contacts the one inorganic insulating layer through the opening.

8. The display device according to claim 7, wherein: The plurality of inorganic insulating layers include a first inorganic insulating layer, a second inorganic insulating layer, a third inorganic insulating layer, and a fourth inorganic insulating layer sequentially stacked on each other, and Wherein, the organic insulating layer covers a portion of the fourth inorganic insulating layer.

9. The display device according to claim 7, further comprising: A pixel defining layer, disposed on the organic insulating layer and defining a light emitting area; as well as A spacer is disposed on the pixel defining layer, Wherein, in a plan view, the spacer is located between the cutout portion of the substrate and the opening of the organic insulating layer adjacent to the cutout portion.

10. The display device according to claim 7, wherein: The first pixel group comprises: a first electrode, on the organic insulating layer; an emission layer, on the first electrode; a second electrode on the emitting layer; and a contact electrode disposed on at least one of the plurality of inorganic insulating layers, wherein each of the emission layer and the contact electrode is located in the first region, and The second electrode is arranged on the contact electrode, so that at least a portion of the contact electrode is in contact with the second electrode.

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